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* ppc4xx_i2c: Rewrite to model hardware more closelyBALATON Zoltan2018-07-032-143/+159
| | | | | | | | | | | | Rewrite to make it closer to how real device works so that guest OS drivers can access I2C devices. Previously this was only a hack to allow U-Boot to get past accessing SPD EEPROMs but to support other I2C devices and allow guests to access them we need to model real device more properly. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* hw/ppc: Give sam46ex its own config optionDavid Gibson2018-07-032-1/+3
| | | | | | | | | At present the Sam460ex board is activated by the general CONFIG_PPC4XX option. However that includes the board for both ppc-softmmu and (deprecated) ppcemb-softmmu builds. As Sam460ex is developed, that would require adding more things into ppcemb-softmmu, which we don't want to do. Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* fpu_helper.c: fix setting FPSCR[FI] bitJohn Arbuckle2018-07-031-0/+8
| | | | | | | | | | The FPSCR[FI] bit indicates if the last floating point instruction had a result that was rounded. Each consecutive floating point instruction is suppose to set this bit to the correct value. What currently happens is this bit is not set as often as it should be. I have verified that this is the behavior of a real PowerPC 950. This patch fixes that problem by deciding to set this bit after each floating point instruction. https://www.pdfdrive.net/powerpc-microprocessor-family-the-programming-environments-for-32-e3087633.html Page 63 in table 2-4 is where the description of this bit can be found. Signed-off-by: John Arbuckle <programmingkidx@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: Implement the rest of gen_st_atomicRichard Henderson2018-07-031-1/+25
| | | | | | | | | | | The store twin case was stubbed out. For now, implement it only within a serial context, forcing parallel execution to synchronize. It would be possible to implement with a cmpxchg loop, if we care, but the loose alignment requirements (simply no crossing 32-byte boundary) might send us back to the serial context anyway. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: Implement the rest of gen_ld_atomicRichard Henderson2018-07-031-4/+79
| | | | | | | | | These cases were stubbed out. For now, implement them only within a serial context, forcing parallel execution to synchronize. It would be possible to implement these with cmpxchg loops, if we care. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: Use atomic min/max helpersRichard Henderson2018-07-031-3/+19
| | | | | | | These operations were previously unimplemented for ppc. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: Use MO_ALIGN for EXIWX and ECOWXRichard Henderson2018-07-031-21/+4
| | | | | | | This avoids the need for gen_check_align entirely. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: Split out gen_st_atomicRichard Henderson2018-07-031-48/+49
| | | | | | | | | Move the guts of ST_ATOMIC to a function. Use foo_tl for the operations instead of foo_i32 or foo_i64 specifically. Use MO_ALIGN instead of an explicit call to gen_check_align. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: Split out gen_ld_atomicRichard Henderson2018-07-031-53/+52
| | | | | | | | | Move the guts of LD_ATOMIC to a function. Use foo_tl for the operations instead of foo_i32 or foo_i64 specifically. Use MO_ALIGN instead of an explicit call to gen_check_align. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: Split out gen_load_lockedRichard Henderson2018-07-031-17/+18
| | | | | | | | | Leave only the minimal amount of code within the LDAR macro, moving the rest of the code into gen_load_locked. Use MO_ALIGN and remove the explicit call to gen_check_align. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: Tidy gen_conditional_storeRichard Henderson2018-07-031-17/+11
| | | | | | | | | | Leave only the minimal amount of code within the STCX macro, moving the rest of the code into gen_conditional_store. Remove the explicit call to gen_check_align; the matching LDAX will have already checked alignment, and we verify the same address. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: Remove POWERPC_EXCP_STCXRichard Henderson2018-07-033-118/+22
| | | | | | | | | Always use the gen_conditional_store implementation that uses atomic_cmpxchg. Make sure and clear reserve_addr across most interrupts crossing the cpu_loop. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: Use atomic cmpxchg for STQCXRichard Henderson2018-07-033-33/+100
| | | | | | | | | When running in a parallel context, we must use a helper in order to perform the 128-bit atomic operation. When running in a serial context, do the compare before the store. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: Use atomic store for STQRichard Henderson2018-07-033-8/+45
| | | | | | | | | Section 1.4 of the Power ISA v3.0B states that this insn is single-copy atomic. As we cannot (yet) issue 128-bit stores within TCG, use the generic helpers provided. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: Use atomic load for LQ and LQARXRichard Henderson2018-07-034-25/+94
| | | | | | | | | | | | | | Section 1.4 of the Power ISA v3.0B states that both of these instructions are single-copy atomic. As we cannot (yet) issue 128-bit loads within TCG, use the generic helpers provided. Since TCG cannot (yet) return a 128-bit value, add a slot within CPUPPCState for returning the high half of a 128-bit return value. This solution is preferred to the helper assigning to architectural registers directly, as it avoids clobbering all TCG live values. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: Add do_unaligned_access hookRichard Henderson2018-07-033-1/+23
| | | | | | | | This allows faults from MO_ALIGN to have the same effect as from gen_check_align. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* ppc/pnv: fix pnv_core_realize() error handlingCédric Le Goater2018-07-031-0/+1
| | | | | | | | | | | | commit d35aefa9ae15 ("ppc/pnv: introduce a new intc_create() operation to the chip model") changed the object link in the pnv_core_realize() routine but a return was forgotten in case of error, which can lead to more problems afterwards (segv) Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* ppc/xics: rework the ICS classes inheritance treeCédric Le Goater2018-07-032-8/+6
| | | | | | | | | | | | | | | With the previous changes, we can now let the ICS_KVM class inherit directly from ICS_BASE class and not from the intermediate ICS_SIMPLE. It makes the class hierarchy much cleaner. What is left in the top classes is the low level interface to access the KVM XICS device in ICS_KVM and the XICS emulating handlers in ICS_SIMPLE. This should not break migration compatibility. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* ppc/xics: move the vmstate structures under the ics-base classCédric Le Goater2018-07-031-56/+56
| | | | | Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* ppx/xics: introduce a parent_reset in ICSStateClassCédric Le Goater2018-07-033-31/+41
| | | | | | | | Just like for the realize handlers, this makes possible to move the common ICSState code of the reset handlers in the ics-base class. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* ppc/xics: move the instance_init handler under the ics-base classCédric Le Goater2018-07-031-8/+8
| | | | | Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* ppc/xics: introduce a parent_realize in ICSStateClassCédric Le Goater2018-07-033-21/+39
| | | | | | | | This makes possible to move the common ICSState code of the realize handlers in the ics-base class. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* ppc/xics: introduce ICP DeviceRealize and DeviceReset handlersCédric Le Goater2018-07-034-21/+43
| | | | | | | | | This changes the ICP realize and reset handlers in DeviceRealize and DeviceReset handlers. parent handlers are now called from the inheriting classes which is a cleaner object pattern. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* sam460ex: Fix sam460ex device tree when booting the Linux kernelGuenter Roeck2018-07-031-0/+28
| | | | | | | | | | | | | | sam460ex (or at least this emulation) does not support the "ibm,cpm" power management. As a result, Linux crashes when trying to access it. Remove its device tree node. Also, if/when we boot the Linux kernel directly, serial port clock frequencies in the device tree file will be unset, and serial port initialization will fail. Add valid frequency values to the serial ports to be able to use it. Also set valid values for the other clock nodes otherwise set by u-boot. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* mac_newworld: always enable disable_direct_reg3_writes for ADB machinesMark Cave-Ayland2018-07-031-2/+2
| | | | | | | | | | | | | Commit 84051eb400 "adb: add property to disable direct reg 3 writes" added a workaround for MacOS 9 incorrectly setting the mouse address during boot of PMU machines. Further testing has shown that since fb6649f172 "adb: fix read reg 3 byte ordering" this can still sometimes happen with the CUDA mac99 machine, so let's enable this workaround for all New World machines using ADB for now. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* mac_dbdma: only dump commands for debug enabled channelsMark Cave-Ayland2018-07-031-10/+11
| | | | | | | | This enables us to apply the same filter in DEBUG_DBDMA_CHANMASK to the DBDMA command execution debug output. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20180702' into stagingPeter Maydell2018-07-026-57/+99
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Assorted tlb and tb caching fixes # gpg: Signature made Mon 02 Jul 2018 17:03:07 BST # gpg: using RSA key 64DF38E8AF7E215F # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-tcg-20180702: cpu: Assert asidx_from_attrs return value in range accel/tcg: Avoid caching overwritten tlb entries accel/tcg: Don't treat invalid TLB entries as needing recheck accel/tcg: Correct "is this a TLB miss" check in get_page_addr_code() tcg: Define and use new tlb_hit() and tlb_hit_page() functions translate-all: fix locking of TBs whose two pages share the same physical page Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * cpu: Assert asidx_from_attrs return value in rangeRichard Henderson2018-07-021-2/+4
| | | | | | | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * accel/tcg: Avoid caching overwritten tlb entriesRichard Henderson2018-07-021-26/+35
| | | | | | | | | | | | | | | | | | When installing a TLB entry, remove any cached version of the same page in the VTLB. If the existing TLB entry matches, do not copy into the VTLB, but overwrite it. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * accel/tcg: Don't treat invalid TLB entries as needing recheckPeter Maydell2018-07-021-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In get_page_addr_code() when we check whether the TLB entry is marked as TLB_RECHECK, we should not go down that code path if the TLB entry is not valid at all (ie the TLB_INVALID bit is set). Tested-by: Laurent Vivier <laurent@vivier.eu> Reported-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20180629161731.16239-1-peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * accel/tcg: Correct "is this a TLB miss" check in get_page_addr_code()Peter Maydell2018-07-021-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In commit 71b9a45330fe220d1 we changed the condition we use to determine whether we need to refill the TLB in get_page_addr_code() to if (unlikely(env->tlb_table[mmu_idx][index].addr_code != (addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK)))) { This isn't the right check (it will falsely fail if the input addr happens to have the low bit corresponding to TLB_INVALID_MASK set, for instance). Replace it with a use of the new tlb_hit() function, which is the correct test. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20180629162122.19376-3-peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg: Define and use new tlb_hit() and tlb_hit_page() functionsPeter Maydell2018-07-024-22/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The condition to check whether an address has hit against a particular TLB entry is not completely trivial. We do this in various places, and in fact in one place (get_page_addr_code()) we have got the condition wrong. Abstract it out into new tlb_hit() and tlb_hit_page() inline functions (one for a known-page-aligned address and one for an arbitrary address), and use them in all the places where we had the condition correct. This is a no-behaviour-change patch; we leave fixing the buggy code in get_page_addr_code() to a subsequent patch. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20180629162122.19376-2-peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * translate-all: fix locking of TBs whose two pages share the same physical pageEmilio G. Cota2018-07-021-7/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 0b5c91f ("translate-all: use per-page locking in !user-mode", 2018-06-15) introduced per-page locking. It assumed that the physical pages corresponding to a TB (at most two pages) are always distinct, which is wrong. For instance, an xtensa test provided by Max Filippov is broken by the commit, since the test maps two virtual pages to the same physical page: virt1: 7fff, virt2: 8000 phys1 6000fff, phys2 6000000 Fix it by removing the assumption from page_lock_pair. If the two physical page addresses are equal, we only lock the PageDesc once. Note that the two callers of page_lock_pair, namely page_unlock_tb and tb_link_page, are also updated so that we do not try to unlock the same PageDesc twice. Fixes: 0b5c91f74f3c83a36f37740969df8c775c997e69 Reported-by: Max Filippov <jcmvbkbc@gmail.com> Tested-by: Max Filippov <jcmvbkbc@gmail.com> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Emilio G. Cota <cota@braap.org> Message-Id: <1529944302-14186-1-git-send-email-cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | Merge remote-tracking branch ↵Peter Maydell2018-07-0220-20/+13
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/kraxel/tags/seabios-1.11.2-20180702-pull-request' into staging seabios: update to release 1.11.2, add/update configuration. vgabios: remove (old unused lgpl'ed vgabios). ramfb,bochs-display: use new vgabios roms. # gpg: Signature made Mon 02 Jul 2018 16:42:06 BST # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/seabios-1.11.2-20180702-pull-request: ramfb: enable vgabios bochs-display: enable vgabios seabios: update bios and vgabios binaries vgabios: remove submodule and build rules. seabios: enable ide dma seabios: add vga configs for bochs-display and ramfb seabios: update submodule to release 1.11.2 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | ramfb: enable vgabiosGerd Hoffmann2018-07-021-0/+1
| | | | | | | | | | | | | | | | | | Add vgabios binary to fw_cfg vgaroms. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
| * | bochs-display: enable vgabiosGerd Hoffmann2018-07-021-0/+1
| | | | | | | | | | | | | | | | | | Add vgabios binary to pci rom bar. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
| * | seabios: update bios and vgabios binariesGerd Hoffmann2018-07-0210-0/+0
| | | | | | | | | | | | | | | | | | Adds two new vgabios binaries, for ramfb and bochs-display. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
| * | vgabios: remove submodule and build rules.Gerd Hoffmann2018-07-023-19/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's the old, lgpl vgabios implementation. Was left in as fallback when we switched to seavgabios, so we could easily switch back in case we see regressions. It's unused since years now, reportedly doesn't even build, and lacks support for recently (and not so recently) added display devices. Zap it. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
| * | seabios: enable ide dmaGerd Hoffmann2018-07-022-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | QNX reportedly requires this to boot. Should also speed up booting other guests. Note: Upstream seabios defaults this to 'n' to due to known problems on physical hardware (qemu not affected), and wouldn't flip the default to 'y'. So we adjust our local build config accordingly. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
| * | seabios: add vga configs for bochs-display and ramfbGerd Hoffmann2018-07-023-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Both bochs-display and ramfb are devices with a simple framebuffer and no vga emulation or text mode. seavgabios has support for text mode emulation (at vgabios call level), we are using that to provide some vga compatibility support for these devices. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
| * | seabios: update submodule to release 1.11.2Gerd Hoffmann2018-07-021-0/+0
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git shortlog rel-1.11.1..rel-1.11.2 ----------------------------------- Gerd Hoffmann (11): optionrom: enable non-vga display devices cbvga: factor out cbvga_setup_modes() qemu: add bochs-display support cbvga_setup_modes: use real mode number instead of 0x140 cbvga_list_modes: don't list current mode twice cbvga_set_mode: disable clearmem in windows x86 emulator. bochs_display_setup: return error on failure pmm: use tmp zone on oom vgasrc: add allocate_pmm() qemu: add qemu ramfb support cbvga_set_mode: refine clear display logic Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* | Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20180702' into stagingPeter Maydell2018-07-0230-166/+543
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | s390x updates: - add bpb/ppa15 features to default cpu model for z196 and later - rework TOD handling and fix cpu hotplug under tcg - various fixes # gpg: Signature made Mon 02 Jul 2018 12:09:40 BST # gpg: using RSA key DECF6B93C6F02FAF # gpg: Good signature from "Cornelia Huck <conny@cornelia-huck.de>" # gpg: aka "Cornelia Huck <huckc@linux.vnet.ibm.com>" # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" # gpg: aka "Cornelia Huck <cohuck@kernel.org>" # gpg: aka "Cornelia Huck <cohuck@redhat.com>" # Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0 18CE DECF 6B93 C6F0 2FAF * remotes/cohuck/tags/s390x-20180702: s390x/tcg: fix locking problem with tcg_s390_tod_updated s390x/kvm: indicate alignment in legacy_s390_alloc() s390x/kvm: legacy_s390_alloc() only supports one allocation s390x/tcg: fix CPU hotplug with single-threaded TCG s390x/tcg: rearm the CKC timer during migration s390x/tcg: implement SET CLOCK s390x/tcg: SET CLOCK COMPARATOR can clear CKC interrupts s390x/tcg: properly implement the TOD s390x/tcg: drop tod_basetime s390x/tod: factor out TOD into separate device s390x/kvm: pass values instead of pointers to kvm_s390_set_clock_*() s390x/tcg: avoid overflows in time2tod/tod2time s390x/cpumodel: default enable bpb and ppa15 for z196 and later loader: Check access size when calling rom_ptr() to avoid crashes s390/ipl: fix ipl with -no-reboot Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * s390x/tcg: fix locking problem with tcg_s390_tod_updatedDavid Hildenbrand2018-07-021-10/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | tcg_s390_tod_updated() is always called with the iothread being locked (e.g. from S390TODClass->set() e.g. via HELPER(sck) or on incoming migration). The helper we call takes the lock itself - bad. Let's change that by factoring out updating the ckc timer. This now looks much nicer than having to call a helper from another function. While touching it we also make sure that env->ckc is updated even if the new value is -1ULL, for now it would not have been modified in that case. Reported-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180629170520.13671-1-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
| * s390x/kvm: indicate alignment in legacy_s390_alloc()David Hildenbrand2018-07-021-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Let's do this for completeness reason, although we don't support e.g. PCDIMM/NVDIMM, which would use the alignment for placing the memory region in guest physical memory. But maybe someday we would want to support something like this - then we don't forget about this if allowing multiple allocations in legacy_s390_alloc(). Use the same alignment as we would set in qemu_anon_ram_alloc(). Our fixed address satisfies this alignment (1MB). This implicitly sets the alignment of the underlying memory region. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180628113817.30814-3-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
| * s390x/kvm: legacy_s390_alloc() only supports one allocationDavid Hildenbrand2018-07-021-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We always allocate at a fixed address, a second allocation can therefore of course never work. We would simply overwrite mappings. This can e.g. happen in s390_memory_init(), if trying to allocate more than > 8TB. Let's just bail out, as there is no need for supporting it (legacy handling for z/VM). Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180628113817.30814-2-david@redhat.com> Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
| * s390x/tcg: fix CPU hotplug with single-threaded TCGDavid Hildenbrand2018-07-021-5/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | run_on_cpu() doesn't seem to work reliably until the CPU has been fully created if the single-threaded TCG main loop is already running. Therefore, hotplugging a CPU under single-threaded TCG does currently not work. We should use the direct call instead of going via run_on_cpu(). So let's use run_on_cpu() for KVM only - KVM requires it due to the initial CPU reset ioctl. As a nice side effect, we get rid of the ifdef. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180627134410.4901-10-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
| * s390x/tcg: rearm the CKC timer during migrationDavid Hildenbrand2018-07-023-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | If the CPU data is migrated after the TOD clock, the CKC timer of a CPU is not rearmed. Let's rearm it when loading the CPU state. Introduce tcg-stub.c just like kvm-stub.c for tcg specific stubs. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180627134410.4901-9-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
| * s390x/tcg: implement SET CLOCKDavid Hildenbrand2018-07-024-2/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | This allows a guest to change its TOD. We already take care of updating all CKC timers from within S390TODClass. Use MO_ALIGN to load the operand manually - this will properly trigger a SPECIFICATION exception. Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180627134410.4901-8-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
| * s390x/tcg: SET CLOCK COMPARATOR can clear CKC interruptsDavid Hildenbrand2018-07-021-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | Let's stop the timer and delete any pending CKC IRQ before doing anything else. While at it, add a comment why the check for ckc == -1ULL is needed. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180627134410.4901-7-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
| * s390x/tcg: properly implement the TODDavid Hildenbrand2018-07-028-34/+109
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Right now, each CPU has its own TOD. Especially, the TOD will differ based on creation time of a CPU - e.g. when hotplugging a CPU the times will differ quite a lot, resulting in stall warnings in the guest. Let's use a single TOD by implementing our new TOD device. Prepare it for TOD-clock epoch extension. Most importantly, whenever we set the TOD, we have to update the CKC timer. Introduce "tcg_s390x.h" just like "kvm_s390x.h" for tcg specific function declarations that should not go into cpu.h. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180627134410.4901-6-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>