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* Patch to reintroduce issue-2248 sr/pluginReimersS2025-10-301-0/+18
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* Aarch64 supportReimersS2025-10-291-3/+12
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* Basic pluginReimersS2025-10-282-7/+290
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* Update Focaccia plugin to execute every time that a translation executesTheofilos Augoustis2025-10-091-5/+12
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* Add flake lockTheofilos Augoustis2025-10-081-0/+61
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* Set QEMU plugin API version in base Focaccia pluginTheofilos Augoustis2025-10-081-0/+4
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* Add basic flake for building QEMU for FocacciaTheofilos Augoustis2025-10-081-0/+30
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* Add basic Focaccia stubTheofilos Augoustis2025-10-082-1/+30
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* Update version for v10.0.0-rc2 releaseStefan Hajnoczi2025-04-011-1/+1
| | | | Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
* Merge tag 'pull-aspeed-20250401' of https://github.com/legoater/qemu into ↵Stefan Hajnoczi2025-04-011-2/+14
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging aspeed queue: * Fixed SCU access size on AST2500 and AST2600 SoCs # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmfr2DsACgkQUaNDx8/7 # 7KHlHg/8D5/maW8yAfQjUBfvy2+tzpV1SvBTKxSvv5n9tP3CFDSgNjFXfDnt06qK # xNE4YzK5I7wWQ20OKXB1LfqHqaJJXT7G1Qc44ZbmfHdiISMuaZaWDjQyzXO/TDSH # e8Svb3iV4IA2J2B6dsbPOym6XMFL9awhXurhYTxfnl9oFhkvgaP1H6Ur0/m8peOq # HELkY18nyWbpeZyIArEagXtBb1n1ucn51dwaDLq9F+D5vXAe6NN8Am5RG/gEED6X # P/o6/VphxR/EmijbIrixHUWmORnuXV4KI13xdLb3hyjIOtgjFPENQuUJTczwkK/8 # mpdTOj+m8ovGMuFGmvnGy6uyYRmXQarBOSSR19XPlMF1qlO7rUUzYPTl7M8M45C5 # UuU9Q60KNSiCHdQqimdZwy/IoI8nuEHMT6g2/Vd82OUJ6K/uR3V0dVel7LVEOvVj # 1xXtNOL8Xy5W0Z84nPLOjpD1WU8Khl8m6OZR81RWR9jTj61dX9AfggkJXSzU6G0Z # Yhv6shqYRn+LpAN/cjqUP6hR1C0iBCi+lBNG6wKq3DVCDXPCg8yEW9D+NUwVj64z # 6BMF335RP3phkmpFMniJ83Ad4yxOmKubQcIIXjLvEiAdppxvDCjQBgYkKHRXkJV0 # wVYnfDwB2quDA1oS3tLibvRf366NjhPfJhMx+yiL4RgFUQ/BvfI= # =VRwA # -----END PGP SIGNATURE----- # gpg: Signature made Tue 01 Apr 2025 08:12:43 EDT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@redhat.com>" [full] # gpg: aka "Cédric Le Goater <clg@kaod.org>" [full] # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-aspeed-20250401' of https://github.com/legoater/qemu: hw/misc/aspeed_scu: Correct minimum access size for AST2500 / AST2600 hw/misc/aspeed_scu: Set MemoryRegionOps::impl::access_size to 32-bit Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * hw/misc/aspeed_scu: Correct minimum access size for AST2500 / AST2600Joel Stanley2025-04-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Guest code was performing a byte load to the SCU MMIO region, leading to the guest code crashing (it should be using proper accessors, but that is not Qemu's bug). Hardware and the documentation[1] both agree that byte loads are okay, so change all of the aspeed SCU devices to accept a minimum access size of 1. [1] See the 'ARM Address Space Mapping' table in the ASPEED docs. This is section 6.1 in the ast2400 and ast2700, and 7.1 in the ast2500 and ast2600 datasheets. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2636 Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Troy Lee <leetroy@gmail.com> Message-ID: <20241118021820.4928-1-joel@jms.id.au> [PMD: Rebased, only including SCU changes] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au> Link: https://lore.kernel.org/qemu-devel/20250331230444.88295-3-philmd@linaro.org Signed-off-by: Cédric Le Goater <clg@redhat.com>
| * hw/misc/aspeed_scu: Set MemoryRegionOps::impl::access_size to 32-bitPhilippe Mathieu-Daudé2025-04-011-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All MemoryRegionOps::read/write() handlers switch over a 32-bit aligned value, because converted using TO_REG(), which is defined as: #define TO_REG(offset) ((offset) >> 2) So all implementations are 32-bit. Set min/max access_size accordingly. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au> Link: https://lore.kernel.org/qemu-devel/20250331230444.88295-2-philmd@linaro.org Signed-off-by: Cédric Le Goater <clg@redhat.com>
* | Merge tag 'hw-misc-20250331' of https://github.com/philmd/qemu into stagingStefan Hajnoczi2025-04-0130-66/+99
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Misc HW patches - Expose v7M System Control Space as little endian (Philippe) - Deprecate MipsSim machine (Thomas) - Improve some devices categories / descriptions (Philippe) - Correct memory_rw_debug() prototype (Richard) - Do not expose i.MX 8M SoC as user-creatable (Bernhard) - Do not expose some PLL & eFuse devices as user-creatable (Philippe) - Do not reset Goldfish RTC time on machine reset (Heinrich) - Fix incorrect BCM2835 AUX interrupt ID when RX disabled (Chung-Yi) - Fix DesignWare PCI host bridge ATU_UPPER_TARGET register access (Philippe) - Memory leak fixes (Bernhard & Zheng Huang) - Prevent out-of-bound access in avr_print_insn (Richard) - Fixes around MIPS page mask (Richard) # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmfq8VYACgkQ4+MsLN6t # wN4AvhAAyTWwGhLfelpPgfj6JHCNiUFUjp4R5a3Y2ROJ19UQ8pcK0RlE5jFNzA6G # sUmy6cl4XK3ojT5EJ/FyVMlLniw9hWmOiIgHHLU+h2Ji+oCS3S2N2T2hFCs4vbT+ # SNjhN1RIdrlWnoSJZiiKM4njKcJxwvg0MCmvOgV70Njy+sVB9zu7YdA0i8yryXOy # a0PDMS71hckF2HBizYrhYAhxPISK3oVoeLRUeGGQhZBUMmu+oZoEWp0DjeuMPoQv # pUX0G7LAqNWCyhIXHEUYGAtSZJc08wEmoypbj1s9PDO5q6NEruCwiWyNHTBXzPsS # ingMM66o2xPCk8BnWSRvpocTgi2QYI/nk+S9L5Gr+FWMGmCbiFAX6c7OH6t4jqz2 # HwqKDZ1FJzBnquT/5ABR5won0cvjsTGhr76oxEyeM3xrGKyysmrBXWYYXjnaidlc # uzr4hc6UT6bYlN53SG1dZP6/aWWcK57MaqrJnjOmLi+VEUEC8p9iOjN+ED7QicBj # Wc1TPMeE8TK7EVJoeor1PAyLHWE+oGDOb8Rcyauxge9cPcqZPWYeSp3HpwhLJb+K # XbwFoSsQRCXT4acL70hkHyjfXtM1qu+g7dWFvEGPlqfuQMvfk4fOfwKbJVxb8UvO # OO96TUPnhpxiC6gYxMRJ9ZwIbzyZ9+SG3loW1OVSmx3Ndth2mh8= # =O3jG # -----END PGP SIGNATURE----- # gpg: Signature made Mon 31 Mar 2025 15:47:34 EDT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'hw-misc-20250331' of https://github.com/philmd/qemu: (23 commits) target/mips: Simplify and fix update_pagemask target/mips: Require even maskbits in update_pagemask target/mips: Revert TARGET_PAGE_BITS_VARY target/sparc: Log unimplemented ASI load/store accesses target/avr: Fix buffer read in avr_print_insn target/hppa: Remove duplicated CPU_RESOLVING_TYPE definition hw/pci-host/designware: Fix ATU_UPPER_TARGET register access hw/ufs: free irq on exit hw/char/bcm2835_aux: Fix incorrect interrupt ID when RX disabled hw/sd/sdhci: free irq on exit hw/scsi/lsi53c895a: fix memory leak in lsi_scsi_realize() hw/nvram/xlnx-efuse: Do not expose as user-creatable hw/misc/pll: Do not expose as user-creatable hw/rtc/goldfish: keep time offset when resetting hw/mips: Mark the "mipssim" machine as deprecated hw/dma/i82374: Categorize and add description hw/display/dm163: Add description hw/block/m25p80: Categorize and add description hw/core/cpu: Use size_t for memory_rw_debug len argument hw/arm/fsl-imx8mp: Remove unused define ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * target/mips: Simplify and fix update_pagemaskRichard Henderson2025-03-313-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When update_pagemask was split from helper_mtc0_pagemask, we failed to actually write to the new parameter but continue to write to env->CP0_PageMask. Thus the use within page_table_walk_refill modifies cpu state and not the local variable as expected. Simplify by renaming to compute_pagemask and returning the value directly. No need for either env or pointer return. Fixes: 074cfcb4dae ("target/mips: Implement hardware page table walker for MIPS32") Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250328175526.368121-4-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Cc: qemu-stable@nongnu.org
| * target/mips: Require even maskbits in update_pagemaskRichard Henderson2025-03-311-15/+8
| | | | | | | | | | | | | | | | | | | | | | The number of bits set in PageMask must be even. Fixes: d40b55bc1b86 ("target/mips: Fix PageMask with variable page size") Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250328175526.368121-3-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Cc: qemu-stable@nongnu.org
| * target/mips: Revert TARGET_PAGE_BITS_VARYRichard Henderson2025-03-315-14/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Revert ee3863b9d41 and a08d60bc6c2b. The logic behind changing the system page size because of what the Loongson kernel "prefers" is flawed. In the Loongson-2E manual, section 5.5, it is clear that the cpu supports a 4k page size (along with many others). Similarly for the Loongson-3 series CPUs, the 4k page size is mentioned in the section 7.7 (PageMask Register). Therefore we must continue to support a 4k page size. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250328175526.368121-2-richard.henderson@linaro.org> [PMD: Mention Loongson-3 series CPUs] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * target/sparc: Log unimplemented ASI load/store accessesPhilippe Mathieu-Daudé2025-03-311-0/+6
| | | | | | | | | | | | | | | | | | When the cache-controller feature is not implemented, log potential ASI access as unimplemented. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Clément Chigot <chigot@adacore.com> Message-Id: <20250325123927.74939-4-philmd@linaro.org>
| * target/avr: Fix buffer read in avr_print_insnRichard Henderson2025-03-311-7/+14
| | | | | | | | | | | | | | | | | | | | | | | | Do not unconditionally attempt to read 4 bytes, as there may only be 2 bytes remaining in the translator cache. Cc: qemu-stable@nongnu.org Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20250325224403.4011975-2-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * target/hppa: Remove duplicated CPU_RESOLVING_TYPE definitionPhilippe Mathieu-Daudé2025-03-311-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | The CPU_RESOLVING_TYPE definition was added in commit 0dacec874fa ("cpu: add CPU_RESOLVING_TYPE macro"), but then added again in commit d3ae32d4d20. Remove the duplication. Fixes: d3ae32d4d20 ("target/hppa: Implement cpu_list") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250321184200.4329-1-philmd@linaro.org>
| * hw/pci-host/designware: Fix ATU_UPPER_TARGET register accessPhilippe Mathieu-Daudé2025-03-311-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Fix copy/paste error writing to the ATU_UPPER_TARGET register, we want to update the upper 32 bits. Cc: qemu-stable@nongnu.org Reported-by: Joey <jeundery@gmail.com> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2861 Fixes: d64e5eabc4c ("pci: Add support for Designware IP block") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org> Message-Id: <20250331152041.74533-2-philmd@linaro.org>
| * hw/ufs: free irq on exitZheng Huang2025-03-311-0/+3
| | | | | | | | | | | | | | | | | | | | Fix a memory leak bug in ufs_init_pci() due to u->irq not being freed in ufs_exit(). Signed-off-by: Zheng Huang <hz1624917200@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <43ceb427-87aa-44ee-9007-dbaecc499bba@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * hw/char/bcm2835_aux: Fix incorrect interrupt ID when RX disabledChung-Yi Chen2025-03-311-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix a misconfiguration issue in the read implementation of the AUX_MU_IIR_REG register. This issue can lead to a transmit interrupt being incorrectly interpreted as a receive interrupt when the receive interrupt is disabled and the receive FIFO holds valid bytes. The AUX_MU_IIR_REG register (interrupt ID bits [2:1]) indicates the status of mini UART interrupts: - 00: No interrupts - 01: Transmit FIFO is empty - 10: Receive FIFO is not empty - 11: <Not possible> When the transmit interrupt is enabled and the receive interrupt is disabled, the original code incorrectly sets the interrupt ID bits. Specifically: 1. Transmit FIFO empty, receive FIFO empty - Expected 0b01, returned 0b01 (correct) 2. Transmit FIFO empty, receive FIFO not empty - Expected 0b01, returned 0b10 (incorrect) In the second case, the code sets the interrupt ID to 0b10 (receive FIFO is not empty) even if the receive interrupt is disabled. To fix this, the patch adds additional condition for setting the interrupt ID bits to also check if the receive interrupt is enabled. Reference: BCM2835 ARM Peripherals, page 13. Available on https://datasheets.raspberrypi.com/bcm2835/bcm2835-peripherals.pdf Fixes: 97398d900ca ("bcm2835_aux: add emulation of BCM2835 AUX (aka UART1) block") Signed-off-by: Chung-Yi Chen <yeechen0207@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250328123725.94176-1-yeechen0207@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * hw/sd/sdhci: free irq on exitZheng Huang2025-03-311-0/+2
| | | | | | | | | | | | | | | | | | | | | | Fix a memory leak bug in sdhci_pci_realize() due to s->irq not being freed in sdhci_pci_exit(). Signed-off-by: Zheng Huang <hz1624917200@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <09ddf42b-a6db-42d5-954b-148d09d8d6cc@gmail.com> [PMD: Moved qemu_free_irq() call before sdhci_common_unrealize()] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * hw/scsi/lsi53c895a: fix memory leak in lsi_scsi_realize()Zheng Huang2025-03-311-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Address a memory leak bug in the usages of timer_del(). The issue arises from the incorrect use of the ambiguous timer API timer_del(), which does not free the timer object. The LeakSanitizer report this issue during fuzzing. The correct API timer_free() freed the timer object instead. ================================================================= ==2586273==ERROR: LeakSanitizer: detected memory leaks Direct leak of 48 byte(s) in 1 object(s) allocated from: #0 0x55f2afd89879 in calloc /llvm-project/compiler-rt/lib/asan/asan_malloc_linux.cpp:75:3 #1 0x7f443b93ac50 in g_malloc0 (/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x5ec50) #2 0x55f2b053962e in timer_new include/qemu/timer.h:542:12 #3 0x55f2b0514771 in timer_new_us include/qemu/timer.h:582:12 #4 0x55f2b0514288 in lsi_scsi_realize hw/scsi/lsi53c895a.c:2350:24 #5 0x55f2b0452d26 in pci_qdev_realize hw/pci/pci.c:2174:9 Signed-off-by: Zheng Huang <hz1624917200@outlook.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <73cd69f9-ff9b-4cd4-b8aa-265f9d6067b9@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * hw/nvram/xlnx-efuse: Do not expose as user-creatablePhilippe Mathieu-Daudé2025-03-311-0/+2
| | | | | | | | | | | | | | | | | | This device is part of SoC components thus can not be created manually. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20250325224310.8785-10-philmd@linaro.org>
| * hw/misc/pll: Do not expose as user-creatablePhilippe Mathieu-Daudé2025-03-313-0/+18
| | | | | | | | | | | | | | | | | | All these devices are part of SoC components and can not be created manually. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20250325224310.8785-9-philmd@linaro.org>
| * hw/rtc/goldfish: keep time offset when resettingHeinrich Schuchardt2025-03-311-7/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently resetting the leads to resynchronizing the Goldfish RTC with the system clock of the host. In real hardware an RTC reset would not change the wall time. Other RTCs like pl031 do not show this behavior. Move the synchronization of the RTC with the system clock to the instance realization. Cc: qemu-stable@nongnu.org Reported-by: Frederik Du Toit Lotter <fred.lotter@canonical.com> Fixes: 9a5b40b8427 ("hw: rtc: Add Goldfish RTC device") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250321221248.17764-1-heinrich.schuchardt@canonical.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * hw/mips: Mark the "mipssim" machine as deprecatedThomas Huth2025-03-311-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | We are not aware of anybody still using this machine, support for it has been withdrawn from the Linux kernel (i.e. there also won't be any future development anymore), and we are not aware of any binaries online that could be used for regression testing to avoid that the machine bitrots ... thus let's mark it as deprecated now. Signed-off-by: Thomas Huth <thuth@redhat.com> Acked-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250121103655.1285596-1-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * hw/dma/i82374: Categorize and add descriptionPhilippe Mathieu-Daudé2025-03-311-0/+2
| | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20250325224310.8785-5-philmd@linaro.org>
| * hw/display/dm163: Add descriptionPhilippe Mathieu-Daudé2025-03-311-1/+1
| | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20250325224310.8785-4-philmd@linaro.org>
| * hw/block/m25p80: Categorize and add descriptionPhilippe Mathieu-Daudé2025-03-311-0/+2
| | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20250325224310.8785-3-philmd@linaro.org>
| * hw/core/cpu: Use size_t for memory_rw_debug len argumentRichard Henderson2025-03-313-3/+3
| | | | | | | | | | | | | | | | | | | | Match the prototype of cpu_memory_rw_debug(). Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250325224403.4011975-4-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * hw/arm/fsl-imx8mp: Remove unused defineBernhard Beschow2025-03-311-1/+0
| | | | | | | | | | | | | | | | | | | | | | The SoC has three SPI controllers, not four. Remove the extra define of an SPI IRQ. Fixes: 06908a84f036 "hw/arm/fsl-imx8mp: Add SPI controllers" Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-ID: <20250318205709.28862-4-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * hw/arm/fsl-imx8mp: Derive struct FslImx8mpState from TYPE_SYS_BUS_DEVICEBernhard Beschow2025-03-313-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Deriving from TYPE_SYS_BUS_DEVICE fixes the SoC object to be reset upon machine reset. It also makes the SoC implementation not user-creatable which can trigger the following crash: $ ./qemu-system-aarch64 -M virt -device fsl-imx8mp ** ERROR:../../devel/qemu/tcg/tcg.c:1006:tcg_register_thread: assertion failed: (n < tcg_max_ctxs) Bail out! ERROR:../../devel/qemu/tcg/tcg.c:1006:tcg_register_thread: assertion failed: (n < tcg_max_ctxs) Aborted (core dumped) Fixes: a4eefc69b237 "hw/arm: Add i.MX 8M Plus EVK board" Reported-by: Thomas Huth <thuth@redhat.com> Suggested-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-ID: <20250318205709.28862-3-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * hw/arm/imx8mp-evk: Fix reference count of SoC objectBernhard Beschow2025-03-311-1/+1
| | | | | | | | | | | | | | | | | | | | | | TYPE_FSL_IMX8MP is created using object_new(), so must be realized with qdev_realize_and_unref() to keep the reference counting intact. Fixes: a4eefc69b237 "hw/arm: Add i.MX 8M Plus EVK board" Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-ID: <20250318205709.28862-2-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * hw/arm/armv7m: Expose and access System Control Space as little endianPhilippe Mathieu-Daudé2025-03-311-7/+7
|/ | | | | | | | | | | | | | | | | | | | | We only build ARM system emulators using little endianness, so the MO_TE definition always expands to MO_LE, and DEVICE_TARGET_ENDIAN to DEVICE_LITTLE_ENDIAN. Replace the definitions by their expanded value, making it closer to the Armv7-M Architecture Reference Manual (ARM DDI 0403E) description: The System Control Space (SCS, address range 0xE000E000 to 0xE000EFFF) is a memory-mapped 4KB address space that provides 32-bit registers for configuration, status reporting and control. All accesses to the SCS are little endian. Fixes: d5d680cacc ("memory: Access MemoryRegion with endianness") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250312104821.1012-1-philmd@linaro.org>
* Merge tag 'pull-riscv-to-apply-20250328' of ↵Stefan Hajnoczi2025-03-283-9/+4
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://github.com/alistair23/qemu into staging Fifth RISC-V PR for 10.0 * Add docs/specs/riscv-iommu.rst to MAINTAINERS * Fix broken link to external risv iommu document * Revert scounteren and senvcfg to fixup older kernel boots # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmfmR0UACgkQr3yVEwxT # gBOdqw/9GeSsIO4DDQ9Zu6C+v4pj9SXuvdpJrO0JBKXdrhp3OH9kVVR5nGvGA1pt # S155AhH8D/pjpMM1exYfBylqTB+CiwjCZnvakvlxx8FkBuDQ/xPBEoPz00TAFAli # 93TDys83HJWk0UDXCCr8Ch7VhaEX07IyFNFz9TQiNNm0zsK4DRtfmYgGQ+RbkIny # 9PxZf6Dz1vfASXGu66EMA1CFaFzXXpxQZtx39OKwfJ4tRj8J/jUFvUtPnP4/sOxH # lyGKIgOfBaSW2AenCoYjPGlRbbdET2YG+IMiqvo5Ie94lZASA6g/8p6zZaBH0RIC # eUNJM7QjimZAIhzhS9xr/Jz/JGY/aeHgVcyPzWVMSty1Qa3a1hsuD/2UFxXadelL # 2QGcVRn2o/3GqgjL+8s7A4c79vjQ8kRSI2GqSaUJ5PGdq/xHC6+f08VfqoZZRWEE # YtzaPh96f6MZT0UdIqCLAG7UfUpYySabzMyYSop7Wqy+O4/bMK2LFtA4IDpomdha # +ZSvCYYarvBDWaTYcbeX2hRnRoF0H5HVK3GYgt088mp4qL+6hM5oxMS2AK/iMuEi # rW2TVk8CfwvGGgLXVj/fmMJ6P6XaIPvo0mvJ2Er67aQFXN+o2IzDqtIH9VUjJFhr # EKiPq0RpX2BBeoi6vtU1Qf2kUj3GHPENACvErC8BlgyywXReb74= # =Xno2 # -----END PGP SIGNATURE----- # gpg: Signature made Fri 28 Mar 2025 02:52:53 EDT # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20250328' of https://github.com/alistair23/qemu: Revert "target/riscv/kvm: add missing KVM CSRs" docs/specs/riscv-iommu: Fixed broken link to external risv iommu document docs: Added docs/specs/riscv-iommu.rst in MAINTAINERS file. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * Revert "target/riscv/kvm: add missing KVM CSRs"Daniel Henrique Barboza2025-03-281-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit breaks KVM boot on older kernels, like reported in [1], due to senvcfg not being available in them. There's also another problem related to scounteren. Using a recent enough guest buildroot, 'ping' will be build with rdtime support. In this case, doing a ping in a KVM guest while exposing scounteren will result in an error. The root cause relates to how KVM handles scounteren, but QEMU can work around it by initializing scounteren with the host value during init(). Fixing these issues in a non-rushed-bandaid manner results in an amount of design changes that I don't feel comfortable pushing during code freeze, so for 10.0 we'll remove the CSRs and re-introduce them in 10.1 with the adequate support. This reverts commit 4db19d5b21e058e6eb3474b6be470d1184afaa9e. [1] https://lore.kernel.org/qemu-riscv/CABJz62OfUDHYkQ0T3rGHStQprf1c7_E0qBLbLKhfv=+jb0SYAw@mail.gmail.com/ Reported-by: Andrea Bolognani <abologna@redhat.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20250327152052.707657-1-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * docs/specs/riscv-iommu: Fixed broken link to external risv iommu documenthemanshu.khilari.foss2025-03-281-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | The links to riscv iommu specification document are incorrect. This patch updates all the said link to point to correct location. Cc: qemu-stable@nongnu.org Cc: qemu-riscv@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2808 Signed-off-by: hemanshu.khilari.foss <hemanshu.khilari.foss@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250323063404.13206-1-hemanshu.khilari.foss@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * docs: Added docs/specs/riscv-iommu.rst in MAINTAINERS file.hemanshu.khilari.foss2025-03-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Added docs/specs/riscv-iommu.rst under `RISC-V TCG CPUs` section in in MAINTAINERS file since `scripts/get_maintainer.pl -f docs/specs/riscv-iommu.rst` doesn't list any maintainers. Signed-off-by: hemanshu.khilari.foss <hemanshu.khilari.foss@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250323140151.9994-1-hemanshu.khilari.foss@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* | Merge tag 'pull-loongarch-20250327' of https://github.com/gaosong715/qemu ↵Stefan Hajnoczi2025-03-282-1/+7
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging bug fix for 10.0 # -----BEGIN PGP SIGNATURE----- # # iLMEAAEKAB0WIQS4/x2g0v3LLaCcbCxAov/yOSY+3wUCZ+VEzQAKCRBAov/yOSY+ # 33HaBADRMzbDPYWLlJpaovU7y3mdX/TAMS+sCBiQa2BqqzC65Pgqmu42gdCUrupa # 32xz+7Bb0p65c3kXcjlMUb8mrEGvp/eFBW1mJWCcx9+LfW5qL6jQrjvUw/TYrMCv # 8OvkvfROiDDV02su4Y7cErvyB5sGyVKtI2AwYH9xp+KDxvyrKQ== # =D4AD # -----END PGP SIGNATURE----- # gpg: Signature made Thu 27 Mar 2025 08:30:05 EDT # gpg: using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF # gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C 6C2C 40A2 FFF2 3926 3EDF * tag 'pull-loongarch-20250327' of https://github.com/gaosong715/qemu: target/loongarch: Fix the cpu unplug resource leak Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * | target/loongarch: Fix the cpu unplug resource leakXianglai Li2025-03-272-1/+7
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the cpu is created, qemu_add_vm_change_state_handler is called in the kvm_arch_init_vcpu function to create the VMChangeStateEntry resource. However, the resource is not released when the cpu is destroyed. This results in a qemu process segment error when the virtual machine restarts after the cpu is unplugged. This patch solves the problem by adding the corresponding resource release process to the kvm_arch_destroy_vcpu function. Signed-off-by: Xianglai Li <lixianglai@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn> Message-Id: <20250324123328.518076-1-lixianglai@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
* | Merge tag 'migration-20250327-pull-request' of ↵Stefan Hajnoczi2025-03-281-7/+13
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.com/farosas/qemu into staging Migration pull request Fix crash due to cpr migration blocker (affects SEV-SNP guest) # -----BEGIN PGP SIGNATURE----- # # iQJEBAABCAAuFiEEqhtIsKIjJqWkw2TPx5jcdBvsMZ0FAmflnA4QHGZhcm9zYXNA # c3VzZS5kZQAKCRDHmNx0G+wxnToTEACblWuLFBjnjJNZoW1f4LT27cT8s98huolA # audigd4xqYQEya1VTiyYckeJKeGp/aC7A4YkjrsFNCwknmIpzqGh4bhRdezerM16 # hlv/mfD9GGDYBS5jMXs8pMo442Lpn7/q78UUflfZwi+ad+XE4xdHkbh0i/GYuuj/ # Z4E2F62tboUfJ0RGeDcV/xjiaxnWkru2x9fMX5BCEez2Jj0Axk80W2lcfcu6tZL4 # s/uEmc235B5f6JtoIVdnr4IllenaukzBt+vPSD+QwweiPwLDTZ+IjBk/Q8Dh4jb8 # Q6E1Paf7ZfeHRlRM1XqZgRACPBQ/gTeCslbCDxjQgCfiS4dL70rdbTSpWOQyYUc3 # DYtqGnJO6t0dHFcH2m2envYT5u5cN+S80yVU+hA4LjefJ1cCu2IWiHwMF5EIYfO4 # eE9CNPALW09mi8OkPNsXRiplLZekIjQPV7znmLh82GWWaTa2GpJYZhD5jhUmyRex # jvdrsLBK1dLgv5PjMMhO6cQobgZQaxbzHMGW+IvobEZ2jjGCNTCZ2/YfXQOGcPcs # pN5Q+8U5IvmhVCTiN7kVRL6TThwT2KqAdWA/UXi5lLQiTHTrEEVJip6JWLJs4zmf # q3g9VIhr8x7Room6TKex6pkeO/7OqSik/pjOvjVCE6RGfi6yNd9a3KLfvCePDjdN # kLWoyan8eQ== # =fZ+v # -----END PGP SIGNATURE----- # gpg: Signature made Thu 27 Mar 2025 14:42:22 EDT # gpg: using RSA key AA1B48B0A22326A5A4C364CFC798DC741BEC319D # gpg: issuer "farosas@suse.de" # gpg: Good signature from "Fabiano Rosas <farosas@suse.de>" [unknown] # gpg: aka "Fabiano Almeida Rosas <fabiano.rosas@suse.com>" [unknown] # gpg: WARNING: The key's User ID is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: AA1B 48B0 A223 26A5 A4C3 64CF C798 DC74 1BEC 319D * tag 'migration-20250327-pull-request' of https://gitlab.com/farosas/qemu: migration: Avoid SNP guest crash due to duplicate cpr blocker Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * | migration: Avoid SNP guest crash due to duplicate cpr blockerSteve Sistare2025-03-271-7/+13
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With aux-ram-share=off, booting an SNP guest fails with: ../util/error.c:68: error_setv: Assertion `*errp == NULL' failed. This is because a CPR blocker for the guest_memfd ramblock is added twice, once in ram_block_add_cpr_blocker because aux-ram-share=off so rb->fd < 0, and once in ram_block_add for a specific guest_memfd blocker. To fix, add the guest_memfd blocker iff a generic one would not be added by ram_block_add_cpr_blocker. Fixes: 094a3dbc55df ("migration: ram block cpr blockers") Reported-by: Tom Lendacky <thomas.lendacky@amd.com> Reported-by: Michael Roth <michael.roth@amd.com> Tested-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Message-ID: <1743087130-429075-1-git-send-email-steven.sistare@oracle.com> [reword subject line] Signed-off-by: Fabiano Rosas <farosas@suse.de>
* | Merge tag 'pull-request-2025-03-27' of https://gitlab.com/thuth/qemu into ↵Stefan Hajnoczi2025-03-2713-9/+45
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging * Make some functional tests more robust * Fix a typo in the s390x code # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmflBdQRHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbVE8Q//RRi0ufAhOd9YfPYqteLvJDDl27rDMmsr # Q0laGYe3ylyUQi9ALglUvfaKNRzJahURwNUqMTyGbTDh/JciQ2mgfYOu7+RsUrBp # fw5HlGIYJt4p/m5MqiqqiJbQ1LMuEehs93WsywhXdrZ5dLrdeWytkddVd/wj9VG4 # EDYizESc1/8Gl6qOM5ZHa7nMs8KD9SnCrzhXFO2m6sPc9hsAJYfU0NJTPBQ/VDd7 # AyFq43fGNdmHbnERueSJa2CeVfIvoHwSMbVvTkBVdKm2N+09q8ZxqUcj7d5Ziz7f # Dehn1DvbY3TTR7fR2PPx9EWdDkJ+s8LmJiO1/KsyQC502wCVgzucQxiuTBVs2wG3 # hnkTQ90DcuCAS7ci/1PisdvJSiEiwAV2YlkEWyTmrCCZzjafzARkc8g8QZhuYCSQ # giz0yMpCla9zI9T/O5NMSsOWDBhy0iNeGwMH8+rDvFraX5a1w2tRTyCa00VWItxb # rRGcEa8fizEB0eX4lpSjOgY9lkzXhUseS/sQoRlI+hNc0ZqSI6CjeiDemFIIEBTd # OllPnvhRG7JMdqmDcQXys7uxc/1D9ZNM92P9BhR3VZswNW7O0hy/qfrgDxHkhPIN # /CrqYgvmeqc1BIcPLIEQzd9nTgpOkggptR+WFGl4VQsDSPOtji9iBzOdsIhSVZlb # eK0gOrb4Vks= # =2v5a # -----END PGP SIGNATURE----- # gpg: Signature made Thu 27 Mar 2025 04:01:24 EDT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2025-03-27' of https://gitlab.com/thuth/qemu: tests/functional/test_vnc: Skip test if VNC support is not available tests/functional/test_aarch64_virt_gpu: Skip if "dbus" display isn't available target/s390x: Fix a typo in s390_cpu_class_init() tests/functional: Add missing require_netdev('user') statements tests/functional/meson.build: Bump arm_aspeed_bletchley timeout tests/functional/test_ppc64_replay: Mark the e500 test as flaky Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * tests/functional/test_vnc: Skip test if VNC support is not availableThomas Huth2025-03-271-4/+22
| | | | | | | | | | | | | | | | | | | | These tests currently fail if VNC support has not been compiled into the QEMU binary. Let's add some checks to skip the tests in that case instead. Message-ID: <20250325064715.278876-1-thuth@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * tests/functional/test_aarch64_virt_gpu: Skip if "dbus" display isn't availableThomas Huth2025-03-272-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | This test currently fails if the "dbus" display has not been compiled into the binary (which can happen when CFI has been enabled, for example). Check for the error message to skip the test in that case. While we're at it, also make sure that this test is covered in the right section in the MAINTAINERS file. Message-ID: <20250325061609.272847-1-thuth@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * target/s390x: Fix a typo in s390_cpu_class_init()Philippe Mathieu-Daudé2025-03-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | Replace the comma at the end of the line by a semicolon. Fixes: 41868f846d2 ("s390x/cpumodel: "host" and "qemu" as CPU subclasses") Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250324165356.39540-1-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * tests/functional: Add missing require_netdev('user') statementsThomas Huth2025-03-277-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | A bunch of tests are using "-netdev user" but fail to check for the availability of SLIRP in the binary, so these tests fail if QEMU has been configured with "--disable-slirp" (most of the tests are disabled by default with a decorator, that's likely why nobody noticed this problem yet). Add the missing self.require_netdev('user') statements to skip the tests if SLIRP is not available. Message-ID: <20250324123450.111307-1-thuth@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * tests/functional/meson.build: Bump arm_aspeed_bletchley timeoutPeter Maydell2025-03-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The arm_aspeed_bletchley timeout takes more than its current 120s timeout on a debug Rust config: $ time (cd build/rust; PYTHONPATH=../../python:../../tests/functional QEMU_TEST_QEMU_BINARY=./qemu-system-arm ./pyvenv/bin/python3 ../../tests/functional/test_arm_aspeed_bletchley.py) TAP version 13 ok 1 test_arm_aspeed_bletchley.BletchleyMachine.test_arm_ast2600_bletchley_openbmc 1..1 real 2m15.536s user 3m21.444s sys 0m11.558s Bump it up to 480s, same as arm_aspeed_rainier. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20250321155806.1888867-1-peter.maydell@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>