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* Revert "hw/386: Add EPYC mode topology decoding functions"Babu Moger2020-09-021-100/+0
| | | | | | | | | | | | This reverts commit 7568b205555a6405042f62c64af3268f4330aed5. Remove the EPYC specific apicid decoding and use the generic default decoding. Signed-off-by: Babu Moger <babu.moger@amd.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <159889936871.21294.1454526726636639780.stgit@naples-babu.amd.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* Revert "target/i386: Cleanup and use the EPYC mode topology functions"Babu Moger2020-09-021-34/+127
| | | | | | | | | | | | This reverts commit dd08ef0318e2b61d14bc069590d174913f7f437a. Remove the EPYC specific apicid decoding and use the generic default decoding. Signed-off-by: Babu Moger <babu.moger@amd.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <159889936257.21294.1786224705357428082.stgit@naples-babu.amd.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* Revert "hw/i386: Introduce apicid functions inside X86MachineState"Babu Moger2020-09-022-14/+0
| | | | | | | | | | | | This reverts commit 6121c7fbfd98dbc3af1b00b56ff2eef66df87828. Remove the EPYC specific apicid decoding and use the generic default decoding. Signed-off-by: Babu Moger <babu.moger@amd.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <159889935648.21294.8095493980805969544.stgit@naples-babu.amd.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* Revert "i386: Introduce use_epyc_apic_id_encoding in X86CPUDefinition"Babu Moger2020-09-022-17/+0
| | | | | | | | | | | | This reverts commit 0c1538cb1a26287c072645f4759b9872b1596d79. Remove the EPYC specific apicid decoding and use the generic default decoding. Signed-off-by: Babu Moger <babu.moger@amd.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <159889935015.21294.1425332462852607813.stgit@naples-babu.amd.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* Revert "hw/i386: Move arch_id decode inside x86_cpus_init"Babu Moger2020-09-022-33/+10
| | | | | | | | | | | | This reverts commit 2e26f4ab3bf8390a2677d3afd9b1a04f015d7721. Remove the EPYC specific apicid decoding and use the generic default decoding. Signed-off-by: Babu Moger <babu.moger@amd.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <159889934379.21294.15323080164340490855.stgit@naples-babu.amd.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* Revert "target/i386: Enable new apic id encoding for EPYC based cpus models"Babu Moger2020-09-021-2/+0
| | | | | | | | | | | | This reverts commit 247b18c593ec298446645af8d5d28911daf653b1. Remove the EPYC specific apicid decoding and use the generic default decoding. Signed-off-by: Babu Moger <babu.moger@amd.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <159889933756.21294.13999336052652073520.stgit@naples-babu.amd.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* Revert "i386: Fix pkg_id offset for EPYC cpu models"Babu Moger2020-09-023-7/+4
| | | | | | | | | | | | | | This reverts commit 7b225762c8c05fd31d4c2be116aedfbc00383f8b. Remove the EPYC specific apicid decoding and use the generic default decoding. Also fix all the references of pkg_offset. Signed-off-by: Babu Moger <babu.moger@amd.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <159889933119.21294.8112825730577505757.stgit@naples-babu.amd.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* tls-cipher-suites: Correct instance_sizeEduardo Habkost2020-09-021-1/+1
| | | | | | | | | | | | We do have a QCryptoTLSCipherSuites struct. It must be used when setting instance_size of the QOM type. Luckily this never caused problems because the QCryptoTLSCipherSuites struct has only a parent_obj field and nothing else. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20200826171005.4055015-5-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* hda-audio: Set instance_size at base classEduardo Habkost2020-09-021-3/+1
| | | | | | | | | | | Setting instance_size correctly at the base class will help us avoid mistakes when declaring new subclasses. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20200826171005.4055015-3-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* rx: Move typedef RXCPU to cpu-qom.hEduardo Habkost2020-09-022-1/+1
| | | | | | | | | | Move the typedef closer to the QOM type checking macros. This will make future conversion to OBJECT_DECLARE* easier. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20200825192110.3528606-54-ehabkost@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* rx: Rename QOM type check macrosEduardo Habkost2020-09-026-17/+17
| | | | | | | | | | | | | | | | | | Currently we have a RXCPU typedef and a RXCPU type checking macro, but OBJECT_DECLARE* would transform the RXCPU macro into a function, and the function name would conflict with the typedef name. Rename the RXCPU* QOM type check macros to RX_CPU*, so we will avoid the conflict and make the macro names consistent with the TYPE_RX_CPU constant name. This will make future conversion to OBJECT_DECLARE* easier. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20200825192110.3528606-53-ehabkost@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* arm: Fix typo in AARCH64_CPU_GET_CLASS definitionEduardo Habkost2020-09-021-1/+1
| | | | | | | | | | There's a typo in the type name of AARCH64_CPU_GET_CLASS. This was never detected because the macro is not used by any code. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20200825192110.3528606-52-ehabkost@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* rdma: Rename INTERFACE_RDMA_PROVIDER_CLASS macroEduardo Habkost2020-09-022-2/+2
| | | | | | | | | | | Rename the macro to be consistent with RDMA_PROVIDER and RDMA_PROVIDER_GET_CLASS. This will make future conversion to OBJECT_DECLARE* easier. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20200825192110.3528606-48-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* x86-iommu: Rename QOM type macrosEduardo Habkost2020-09-025-6/+6
| | | | | | | | | | | | | Some QOM macros were using a X86_IOMMU_DEVICE prefix, and others were using a X86_IOMMU prefix. Rename all of them to use the same X86_IOMMU_DEVICE prefix. This will make future conversion to OBJECT_DECLARE* easier. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20200825192110.3528606-47-ehabkost@redhat.com> Acked-by: Peter Xu <peterx@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* mos6522: Rename QOM macrosEduardo Habkost2020-09-025-19/+19
| | | | | | | | | | | | Rename the MOS6522_DEVICE_CLASS and MOS6522_DEVICE_GET_CLASS macros to be consistent with the TYPE_MOS6522 and MOS6522 macros. This will make future conversion to OBJECT_DECLARE* easier. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20200825192110.3528606-46-ehabkost@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* imx_ccm: Rename IMX_GET_CLASS macroEduardo Habkost2020-09-022-2/+2
| | | | | | | | | | | | Rename it to IMX_CCM_GET_CLASS to be consistent with the existing IMX_CCM and IXM_CCM_CLASS macro. This will make future conversion to OBJECT_DECLARE* easier. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20200825192110.3528606-45-ehabkost@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* Merge remote-tracking branch ↵Peter Maydell2020-09-0116-806/+1824
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/pmaydell/tags/pull-target-arm-20200901' into staging target-arm queue: * Implement fp16 support for AArch32 VFP and Neon * hw/arm/sbsa-ref: add "reg" property to DT cpu nodes * hw/arm/sbsa-ref : Add embedded controller in secure memory # gpg: Signature made Tue 01 Sep 2020 16:17:23 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20200901: (47 commits) hw/arm/sbsa-ref : Add embedded controller in secure memory hw/misc/sbsa_ec : Add an embedded controller for sbsa-ref hw/arm/sbsa-ref: add "reg" property to DT cpu nodes target/arm: Enable FP16 in '-cpu max' target/arm: Implement fp16 for Neon VMUL, VMLA, VMLS target/arm/vec_helper: Add gvec fp indexed multiply-and-add operations target/arm/vec_helper: Handle oprsz less than 16 bytes in indexed operations target/arm: Implement fp16 for Neon VRINTX target/arm: Implement fp16 for Neon VRINT-with-specified-rounding-mode target/arm: Implement fp16 for Neon VCVT with rounding modes target/arm: Implement fp16 for Neon VCVT fixed-point target/arm: Convert Neon VCVT fixed-point to gvec target/arm: Implement fp16 for Neon float-integer VCVT target/arm: Implement fp16 for Neon pairwise fp ops target/arm: Implement fp16 for Neon VRSQRTS target/arm: Implement fp16 for Neon VRECPS target/arm: Implement fp16 for Neon fp compare-vs-0 target/arm: Implement fp16 for Neon VFMA, VMFS target/arm: Implement fp16 for Neon VMLA, VMLS operations target/arm: Implement fp16 for Neon VMAXNM, VMINNM ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/sbsa-ref : Add embedded controller in secure memoryGraeme Gregory2020-09-011-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | Add the previously created sbsa-ec device to the sbsa-ref machine in secure memory so the PSCI implementation in ARM-TF can access it, but not expose it to non secure firmware or OS except by via ARM-TF. Signed-off-by: Graeme Gregory <graeme@nuviainc.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com> Tested-by: Leif Lindholm <leif@nuviainc.com> Message-id: 20200826141952.136164-3-graeme@nuviainc.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/misc/sbsa_ec : Add an embedded controller for sbsa-refGraeme Gregory2020-09-012-0/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A difference between sbsa platform and the virt platform is PSCI is handled by ARM-TF in the sbsa platform. This means that the PSCI code there needs to communicate some of the platform power changes down to the qemu code for things like shutdown/reset control. Space has been left to extend the EC if we find other use cases in future where ARM-TF and qemu need to communicate. Signed-off-by: Graeme Gregory <graeme@nuviainc.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com> Tested-by: Leif Lindholm <leif@nuviainc.com> Message-id: 20200826141952.136164-2-graeme@nuviainc.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/sbsa-ref: add "reg" property to DT cpu nodesLeif Lindholm2020-09-011-6/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sbsa-ref platform uses a minimal device tree to pass amount of memory as well as number of cpus to the firmware. However, when dumping that minimal dtb (with -M sbsa-virt,dumpdtb=<file>), the resulting blob generates a warning when decompiled by dtc due to lack of reg property. Add a simple reg property per cpu, representing a 64-bit MPIDR_EL1. This also ends up being cleaner than having the firmware calculating its own IDs for generating APCI. Signed-off-by: Leif Lindholm <leif@nuviainc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200827124335.30586-1-leif@nuviainc.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Enable FP16 in '-cpu max'Peter Maydell2020-09-012-7/+6
| | | | | | | | | | | | | | | | | | Set the MVFR1 ID register FPHP and SIMDHP fields to indicate that our "-cpu max" has v8.2-FP16. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-46-peter.maydell@linaro.org
| * target/arm: Implement fp16 for Neon VMUL, VMLA, VMLSPeter Maydell2020-09-011-55/+55
| | | | | | | | | | | | | | | | | | Convert the Neon floating-point VMUL, VMLA and VMLS to use gvec, and use this to implement fp16 support. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-45-peter.maydell@linaro.org
| * target/arm/vec_helper: Add gvec fp indexed multiply-and-add operationsPeter Maydell2020-09-012-5/+32
| | | | | | | | | | | | | | | | Add gvec helpers for doing Neon-style indexed non-fused fp multiply-and-accumulate operations. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200828183354.27913-44-peter.maydell@linaro.org
| * target/arm/vec_helper: Handle oprsz less than 16 bytes in indexed operationsPeter Maydell2020-09-011-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | In the gvec helper functions for indexed operations, for AArch32 Neon the oprsz (total size of the vector) can be less than 16 bytes if the operation is on a D reg. Since the inner loop in these helpers always goes from 0 to segment, we must clamp it based on oprsz to avoid processing a full 16 byte segment when asked to handle an 8 byte wide vector. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-43-peter.maydell@linaro.org
| * target/arm: Implement fp16 for Neon VRINTXPeter Maydell2020-09-013-42/+9
| | | | | | | | | | | | | | | | | | Convert the Neon VRINTX insn to use gvec, and use this to implement fp16 support for it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-42-peter.maydell@linaro.org
| * target/arm: Implement fp16 for Neon VRINT-with-specified-rounding-modePeter Maydell2020-09-014-79/+30
| | | | | | | | | | | | | | | | | | Convert the Neon VRINT-with-specified-rounding-mode insns to gvec, and use this to implement the fp16 versions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-41-peter.maydell@linaro.org
| * target/arm: Implement fp16 for Neon VCVT with rounding modesPeter Maydell2020-09-013-67/+66
| | | | | | | | | | | | | | | | | | Convert the Neon VCVT with-specified-rounding-mode instructions to gvec, and use this to implement fp16 support for them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-40-peter.maydell@linaro.org
| * target/arm: Implement fp16 for Neon VCVT fixed-pointPeter Maydell2020-09-014-1/+21
| | | | | | | | | | | | | | | | | | Implement fp16 for the Neon VCVT insns which convert between float and fixed-point. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-39-peter.maydell@linaro.org
| * target/arm: Convert Neon VCVT fixed-point to gvecPeter Maydell2020-09-013-17/+43
| | | | | | | | | | | | | | | | | | Convert the Neon VCVT float<->fixed-point insns to a gvec style, in preparation for adding fp16 support. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-38-peter.maydell@linaro.org
| * target/arm: Implement fp16 for Neon float-integer VCVTPeter Maydell2020-09-013-11/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the Neon float-integer VCVT insns to gvec, and use this to implement fp16 support for them. Note that unlike the VFP int<->fp16 VCVT insns we converted earlier and which convert to/from a 32-bit integer, these Neon insns convert to/from 16-bit integers. So we can use the existing vfp conversion helpers for the f32<->u32/i32 case but need to provide our own for f16<->u16/i16. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-37-peter.maydell@linaro.org
| * target/arm: Implement fp16 for Neon pairwise fp opsPeter Maydell2020-09-013-26/+68
| | | | | | | | | | | | | | | | | | | | | | Convert the Neon pairwise fp ops to use a single gvic-style helper to do the full operation instead of one helper call for each 32-bit part. This allows us to use the same framework to implement the fp16. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-36-peter.maydell@linaro.org
| * target/arm: Implement fp16 for Neon VRSQRTSPeter Maydell2020-09-014-36/+34
| | | | | | | | | | | | | | | | | | | | | | | | Convert the Neon VRSQRTS insn to using a gvec helper, and use this to implement the fp16 case. As with VRECPS, we adjust the phrasing of the new implementation slightly so that the fp32 version parallels the fp16 one. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-35-peter.maydell@linaro.org
| * target/arm: Implement fp16 for Neon VRECPSPeter Maydell2020-09-014-34/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | Convert the Neon VRECPS insn to using a gvec helper, and use this to implement the fp16 case. The phrasing of the new float32_recps_nf() is slightly different from the old recps_f32() so that it parallels the f16 version; for f16 we can't assume that flush-to-zero is always enabled. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-34-peter.maydell@linaro.org
| * target/arm: Implement fp16 for Neon fp compare-vs-0Peter Maydell2020-09-013-28/+45
| | | | | | | | | | | | | | | | | | | | Convert the neon floating-point vector compare-vs-0 insns VCEQ0, VCGT0, VCLE0, VCGE0 and VCLT0 to use a gvec helper, and use this to implement the fp16 case. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-33-peter.maydell@linaro.org
| * target/arm: Implement fp16 for Neon VFMA, VMFSPeter Maydell2020-09-013-91/+40
| | | | | | | | | | | | | | | | | | | | | | | | Convert the neon floating-point vector operations VFMA and VFMS to use a gvec helper, and use this to implement the fp16 case. This is the last use of do_3same_fp() so we can now delete that function. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-32-peter.maydell@linaro.org
| * target/arm: Implement fp16 for Neon VMLA, VMLS operationsPeter Maydell2020-09-013-31/+50
| | | | | | | | | | | | | | | | | | Convert the Neon floating-point VMLA and VMLS insns over to using a gvec helper, and use this to implement the fp16 case. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-31-peter.maydell@linaro.org
| * target/arm: Implement fp16 for Neon VMAXNM, VMINNMPeter Maydell2020-09-013-8/+27
| | | | | | | | | | | | | | | | | | Convert the Neon floating point VMAXNM and VMINNM insns to using a gvec helper and use this to implement the fp16 case. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-30-peter.maydell@linaro.org
| * target/arm: Implement fp16 for Neon VMAX, VMINPeter Maydell2020-09-013-3/+14
| | | | | | | | | | | | | | | | | | Convert the Neon float-point VMAX and VMIN insns over to using a gvec helper, and use this to implement the fp16 case. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-29-peter.maydell@linaro.org
| * target/arm: Implement fp16 for VACGE, VACGTPeter Maydell2020-09-013-2/+34
| | | | | | | | | | | | | | | | | | | | Convert the neon floating-point vector absolute comparison ops VACGE and VACGT over to using a gvec hepler and use this to implement the fp16 case. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-28-peter.maydell@linaro.org
| * target/arm: Implement fp16 for VCEQ, VCGE, VCGT comparisonsPeter Maydell2020-09-013-3/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the Neon floating-point vector comparison ops VCEQ, VCGE and VCGT over to using a gvec helper and use this to implement the fp16 case. (We put the float16_ceq() etc functions above the DO_2OP() macro definition because later when we convert the compare-against-zero instructions we'll want their definitions to be visible at that point in the source file.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-27-peter.maydell@linaro.org
| * target/arm: Implement fp16 for Neon VABS, VNEG of floatsPeter Maydell2020-09-011-6/+28
| | | | | | | | | | | | | | | | | | Rewrite Neon VABS/VNEG of floats to use gvec logical AND and XOR, so that we can implement the fp16 version of the insns. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-26-peter.maydell@linaro.org
| * target/arm: Implement fp16 for Neon VRECPE, VRSQRTE using gvecPeter Maydell2020-09-011-2/+29
| | | | | | | | | | | | | | | | | | | | We already have gvec helpers for floating point VRECPE and VRQSRTE, so convert the Neon decoder to use them and add the fp16 support. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-25-peter.maydell@linaro.org
| * target/arm: Implement FP16 for Neon VADD, VSUB, VABD, VMULPeter Maydell2020-09-013-17/+26
| | | | | | | | | | | | | | | | | | | | | | | | Implement FP16 support for the Neon insns which use the DO_3S_FP_GVEC macro: VADD, VSUB, VABD, VMUL. For VABD this requires us to implement a new gvec_fabd_h helper using the machinery we have already for the other helpers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-24-peter.maydell@linaro.org
| * target/arm: Implement VFP fp16 VMOV between gp and halfprec registersPeter Maydell2020-09-012-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | Implement the VFP fp16 variant of VMOV that transfers a 16-bit value between a general purpose register and a VFP register. Note that Rt == 15 is UNPREDICTABLE; since this insn is v8 and later only we have no need to replicate the old "updates CPSR.NZCV" behaviour that the singleprec version of this insn does. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-22-peter.maydell@linaro.org
| * target/arm: Implement new VFP fp16 insn VMOVXPeter Maydell2020-09-012-0/+28
| | | | | | | | | | | | | | | | | | | | | | The fp16 extension includes a new instruction VMOVX, which copies the upper 16 bits of a 32-bit source VFP register into the lower 16 bits of the destination and zeroes the high half of the destination. Implement it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-21-peter.maydell@linaro.org
| * target/arm: Implement new VFP fp16 insn VINSPeter Maydell2020-09-012-0/+31
| | | | | | | | | | | | | | | | | | | | The fp16 extension includes a new instruction VINS, which copies the lower 16 bits of a 32-bit source VFP register into the upper 16 bits of the destination. Implement it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-20-peter.maydell@linaro.org
| * target/arm: Implement VFP fp16 VRINT*Peter Maydell2020-09-015-8/+122
| | | | | | | | | | | | | | | | Implement the fp16 version of the VFP VRINT* insns. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-19-peter.maydell@linaro.org
| * target/arm: Implement VFP fp16 VSELPeter Maydell2020-09-012-6/+16
| | | | | | | | | | | | | | | | Implement the fp16 versions of the VFP VSEL instruction. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-18-peter.maydell@linaro.org
| * target/arm: Implement VFP vp16 VCVT-with-specified-rounding-modePeter Maydell2020-09-012-10/+28
| | | | | | | | | | | | | | | | | | | | Implement the fp16 versions of the VFP VCVT instruction forms which convert between floating point and integer with a specified rounding mode. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-17-peter.maydell@linaro.org
| * target/arm: Implement VFP fp16 VCVT between float and fixed-pointPeter Maydell2020-09-012-0/+61
| | | | | | | | | | | | | | | | | | Implement the fp16 versions of the VFP VCVT instruction forms which convert between floating point and fixed-point. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-16-peter.maydell@linaro.org