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| * | target/arm: Add ARM_FEATURE_V8_RDMRichard Henderson2018-03-022-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Not enabled anywhere yet. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180228193125.20577-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | mps2-an505: New board model: MPS2 with AN505 Cortex-M33 FPGA imagePeter Maydell2018-03-022-0/+504
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define a new board model for the MPS2 with an AN505 FPGA image containing a Cortex-M33. Since the FPGA images for TrustZone cores (AN505, and the similar AN519 for Cortex-M23) have a significantly different layout of devices to the non-TrustZone images, we use a new source file rather than shoehorning them into the existing mps2.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-20-peter.maydell@linaro.org
| * | hw/arm/iotkit: Model Arm IOT KitPeter Maydell2018-03-024-0/+709
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Model the Arm IoT Kit documented in http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html The Arm IoT Kit is a subsystem which includes a CPU and some devices, and is intended be extended by adding extra devices to form a complete system. It is used in the MPS2 board's AN505 image for the Cortex-M33. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-19-peter.maydell@linaro.org
| * | hw/misc/iotkit-secctl: Add remaining simple registersPeter Maydell2018-03-022-6/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add remaining easy registers to iotkit-secctl: * NSCCFG just routes its two bits out to external GPIO lines * BRGINSTAT/BRGINTCLR/BRGINTEN can be dummies, because QEMU's bus fabric can never report errors Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180220180325.29818-18-peter.maydell@linaro.org
| * | hw/misc/iotkit-secctl: Add handling for PPCsPeter Maydell2018-03-022-19/+315
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The IoTKit Security Controller includes various registers that expose to software the controls for the Peripheral Protection Controllers in the system. Implement these. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-17-peter.maydell@linaro.org
| * | hw/misc/iotkit-secctl: Arm IoT Kit security controller initial skeletonPeter Maydell2018-03-025-0/+496
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Arm IoT Kit includes a "security controller" which is largely a collection of registers for controlling the PPCs and other bits of glue in the system. This commit provides the initial skeleton of the device, implementing just the ID registers, and a couple of read-only read-as-zero registers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-16-peter.maydell@linaro.org
| * | hw/misc/tz-ppc: Model TrustZone peripheral protection controllerPeter Maydell2018-03-025-0/+418
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a model of the TrustZone peripheral protection controller (PPC), which is used to gate transactions to non-TZ-aware peripherals so that secure software can configure them to not be accessible to non-secure software. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-15-peter.maydell@linaro.org
| * | hw/misc/mps2-fpgaio: FPGA control block for MPS2 AN505Peter Maydell2018-03-025-0/+227
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MPS2 AN505 FPGA image includes a "FPGA control block" which is a small set of registers handling LEDs, buttons and some counters. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-14-peter.maydell@linaro.org
| * | hw/core/split-irq: Device that splits IRQ linesPeter Maydell2018-03-024-1/+150
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some board or SoC models it is necessary to split a qemu_irq line so that one input can feed multiple outputs. We currently have qemu_irq_split() for this, but that has several deficiencies: * it can only handle splitting a line into two * it unavoidably leaks memory, so it can't be used in a device that can be deleted Implement a qdev device that encapsulates splitting of IRQs, with a configurable number of outputs. (This is in some ways the inverse of the TYPE_OR_IRQ device.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-13-peter.maydell@linaro.org
| * | qdev: Add new qdev_init_gpio_in_named_with_opaque()Peter Maydell2018-03-022-5/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The function qdev_init_gpio_in_named() passes the DeviceState pointer as the opaque data pointor for the irq handler function. Usually this is what you want, but in some cases it would be helpful to use some other data pointer. Add a new function qdev_init_gpio_in_named_with_opaque() which allows the caller to specify the data pointer they want. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-12-peter.maydell@linaro.org
| * | include/hw/or-irq.h: Add missing include guardPeter Maydell2018-03-021-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The or-irq.h header file is missing the customary guard against multiple inclusion, which means compilation fails if it gets included twice. Fix the omission. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-11-peter.maydell@linaro.org
| * | hw/misc/unimp: Move struct to header filePeter Maydell2018-03-022-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the definition of the struct for the unimplemented-device from unimp.c to unimp.h, so that users can embed the struct in their own device structs if they prefer. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-10-peter.maydell@linaro.org
| * | target/arm: Add Cortex-M33Peter Maydell2018-03-021-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a Cortex-M33 definition. The M33 is an M profile CPU which implements the ARM v8M architecture, including the M profile Security Extension. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-9-peter.maydell@linaro.org
| * | armv7m: Forward init-svtor property to CPU objectPeter Maydell2018-03-022-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | Create an "init-svtor" property on the armv7m container object which we can forward to the CPU object. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-8-peter.maydell@linaro.org
| * | target/arm: Define init-svtor property for the reset secure VTOR valuePeter Maydell2018-03-022-4/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Cortex-M33 allows the system to specify the reset value of the secure Vector Table Offset Register (VTOR) by asserting config signals. In particular, guest images for the MPS2 AN505 board rely on the MPS2's initial VTOR being correct for that board. Implement a QEMU property so board and SoC code can set the reset value to the correct value. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-7-peter.maydell@linaro.org
| * | armv7m: Forward idau property to CPU objectPeter Maydell2018-03-022-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create an "idau" property on the armv7m container object which we can forward to the CPU object. Annoyingly, we can't use object_property_add_alias() because the CPU object we want to forward to doesn't exist until the armv7m container is realized. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-6-peter.maydell@linaro.org
| * | target/arm: Define an IDAU interfacePeter Maydell2018-03-024-3/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In v8M, the Implementation Defined Attribution Unit (IDAU) is a small piece of hardware typically implemented in the SoC which provides board or SoC specific security attribution information for each address that the CPU performs MPU/SAU checks on. For QEMU, we model this with a QOM interface which is implemented by the board or SoC object and connected to the CPU using a link property. This commit defines the new interface class, adds the link property to the CPU object, and makes the SAU checking code call the IDAU interface if one is present. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-5-peter.maydell@linaro.org
| * | hw/arm/armv7m: Honour CPU's address space for image loadsPeter Maydell2018-03-021-3/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of loading guest images to the system address space, use the CPU's address space. This is important if we're trying to load the file to memory or via an alias memory region that is provided by an SoC object and thus not mapped into the system address space. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-4-peter.maydell@linaro.org
| * | hw/arm/boot: Honour CPU's address space for image loadsPeter Maydell2018-03-021-43/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of loading kernels, device trees, and the like to the system address space, use the CPU's address space. This is important if we're trying to load the file to memory or via an alias memory region that is provided by an SoC object and thus not mapped into the system address space. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-3-peter.maydell@linaro.org
| * | loader: Add new load_ramdisk_as()Peter Maydell2018-03-022-2/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a function load_ramdisk_as() which behaves like the existing load_ramdisk() but allows the caller to specify the AddressSpace to use. This matches the pattern we have already for various other loader functions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-2-peter.maydell@linaro.org
| * | decodetree: Propagate return value from translate subroutinesRichard Henderson2018-03-021-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow the translate subroutines to return false for invalid insns. At present we can of course invoke an invalid insn exception from within the translate subroutine, but in the short term this consolidates code. In the long term it would allow the decodetree language to support overlapping patterns for ISA extensions. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180227232618.2908-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | xlnx-zynqmp: Connect the RTC deviceAlistair Francis2018-03-022-0/+16
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | xlnx-zynqmp-rtc: Add basic time supportAlistair Francis2018-03-023-0/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow the guest to determine the time set from the QEMU command line. This includes adding a trace event to debug the new time. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | xlnx-zynqmp-rtc: Initial commitAlistair Francis2018-03-023-0/+299
| |/ | | | | | | | | | | | | | | Initial commit of the ZynqMP RTC device. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2018-03-01' into ↵Peter Maydell2018-03-027-32/+72
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging nbd patches for 2018-03-01 - Eric Blake: nbd: Honor server's advertised minimum block size - Vladimir Sementsov-Ogievskiy: partial: nbd block status base:allocation # gpg: Signature made Thu 01 Mar 2018 21:01:22 GMT # gpg: using RSA key A7A16B4A2527436A # gpg: Good signature from "Eric Blake <eblake@redhat.com>" # gpg: aka "Eric Blake (Free Software Programmer) <ebb9@byu.net>" # gpg: aka "[jpeg image of size 6874]" # Primary key fingerprint: 71C2 CC22 B1C4 6029 27D2 F3AA A7A1 6B4A 2527 436A * remotes/ericb/tags/pull-nbd-2018-03-01: nbd/client: fix error messages in nbd_handle_reply_err nbd: BLOCK_STATUS constants nbd: change indenting in nbd.h nbd: Honor server's advertised minimum block size Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * nbd/client: fix error messages in nbd_handle_reply_errVladimir Sementsov-Ogievskiy2018-03-013-18/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. NBD_REP_ERR_INVALID is not only about length, so, make message more general 2. hex format is not very good: it's hard to read something like "option a (set meta context)", so switch to dec. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-Id: <1518702707-7077-6-git-send-email-vsementsov@virtuozzo.com> [eblake: expand scope of patch: ALL uses of nbd_opt_lookup and nbd_rep_lookup are now decimal] Signed-off-by: Eric Blake <eblake@redhat.com>
| * nbd: BLOCK_STATUS constantsVladimir Sementsov-Ogievskiy2018-03-012-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | Expose the new constants and structs that will be used by both server and client implementations of NBD_CMD_BLOCK_STATUS (the command is currently experimental at https://github.com/NetworkBlockDevice/nbd/blob/extension-blockstatus/doc/proto.md but will hopefully be stabilized soon). Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-Id: <1518702707-7077-4-git-send-email-vsementsov@virtuozzo.com> [eblake: split from larger patch on server implementation] Signed-off-by: Eric Blake <eblake@redhat.com>
| * nbd: change indenting in nbd.hVladimir Sementsov-Ogievskiy2018-03-011-11/+11
| | | | | | | | | | | | | | | | Prepared indenting for the following patch. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-Id: <1518702707-7077-3-git-send-email-vsementsov@virtuozzo.com> Signed-off-by: Eric Blake <eblake@redhat.com>
| * nbd: Honor server's advertised minimum block sizeEric Blake2018-03-012-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 79ba8c98 (v2.7) changed the setting of request_alignment to occur only during bdrv_refresh_limits(), rather than at at bdrv_open() time; but at the time, NBD was unaffected, because it still used sector-based callbacks, so the block layer defaulted NBD to use 512 request_alignment. Later, commit 70c4fb26 (also v2.7) changed NBD to use byte-based callbacks, without setting request_alignment. This resulted in NBD using request_alignment of 1, which works great when the server supports it (as is the case for qemu-nbd), but falls apart miserably if the server requires alignment (but only if qemu actually sends a sub-sector request; qemu-io can do it, but most qemu operations still perform on sectors or larger). Even later, the NBD protocol was updated to document that clients should learn the server's minimum alignment during NBD_OPT_GO; and recommended that clients should assume a minimum size of 512 unless the server understands NBD_OPT_GO and replied with a smaller size. Commit 081dd1fe (v2.10) attempted to do that, by assigning request_alignment to whatever was learned from the server; but it has two flaws: the assignment is done during bdrv_open() so it gets unconditionally wiped out back to 1 during any later bdrv_refresh_limits(); and the code is not using a default of 512 when the server did not report a minimum size. Fix these issues by moving the assignment to request_alignment to the right function, and by using a sane default when the server does not advertise a minimum size. CC: qemu-stable@nongnu.org Signed-off-by: Eric Blake <eblake@redhat.com> Message-Id: <20180215032905.27146-1-eblake@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy<vsementsov@virtuozzo.com>
* | Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell2018-03-0122-15/+1246
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | virtio,vhost,pci,pc: features, fixes and cleanups - documentation updates - vhost fixes - new crypto vhost device Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Thu 01 Mar 2018 16:27:25 GMT # gpg: using RSA key 281F0DB8D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: cryptodev-vhost-user: set the key length cryptodev-vhost-user: add crypto session handler cryptodev: add vhost support cryptodev: add vhost-user as a new cryptodev backend docs/vmcoreinfo: detail unsupported host format behaviour vhost: fix incorrect check in vhost_verify_ring_mappings vhost: avoid to start/stop virtqueue which is not ready vhost: fix memslot limit check docs: pcie: Spell out machine type needs for PCIe features docs: document virtio-balloon stats intel-iommu: Accept 64-bit writes to FEADDR virtio-pci: trivial fixes in error message vhost-user: fix memory leak Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * cryptodev-vhost-user: set the key lengthGonglei2018-03-012-0/+7
| | | | | | | | | | | | Signed-off-by: Gonglei <arei.gonglei@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * cryptodev-vhost-user: add crypto session handlerGonglei2018-03-014-11/+175
| | | | | | | | | | | | | | | | | | | | | | | | Introduce two vhost-user meassges: VHOST_USER_CREATE_CRYPTO_SESSION and VHOST_USER_CLOSE_CRYPTO_SESSION. At this point, the QEMU side support crypto operation in cryptodev host-user backend. Signed-off-by: Gonglei <arei.gonglei@huawei.com> Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com> Signed-off-by: Jay Zhou <jianjay.zhou@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * cryptodev: add vhost supportGonglei2018-03-017-0/+398
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Impliment the vhost-crypto's funtions, such as startup, stop and notification etc. Introduce an enum QCryptoCryptoDevBackendOptionsType in order to identify the cryptodev vhost backend is vhost-user or vhost-kernel-module (If exist). At this point, the cryptdoev-vhost-user works. Signed-off-by: Gonglei <arei.gonglei@huawei.com> Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com> Signed-off-by: Jay Zhou <jianjay.zhou@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * cryptodev: add vhost-user as a new cryptodev backendGonglei2018-03-017-0/+622
| | | | | | | | | | | | | | | | | | | | | | | | | | Usage: -chardev socket,id=charcrypto0,path=/path/to/your/socket -object cryptodev-vhost-user,id=cryptodev0,chardev=charcrypto0 -device virtio-crypto-pci,id=crypto0,cryptodev=cryptodev0 Signed-off-by: Gonglei <arei.gonglei@huawei.com> Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com> Signed-off-by: Jay Zhou <jianjay.zhou@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * docs/vmcoreinfo: detail unsupported host format behaviourMarc-André Lureau2018-03-011-0/+4
| | | | | | | | | | | | | | Suggested-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * vhost: fix incorrect check in vhost_verify_ring_mappingsJia He2018-03-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | In commit 0ca1fd2d6878 ("vhost: Simplify ring verification checks"), it checks the virtqueue desc mapping for 3 times. Fixed: commit 0ca1fd2d6878 ("vhost: Simplify ring verification checks") Signed-off-by: Jia He <jia.he@hxt-semitech.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
| * vhost: avoid to start/stop virtqueue which is not readyJia He2018-03-011-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In our Armv8a server, we try to configure the vhost scsi but fail to boot up the guest (-machine virt-2.10). The guest's boot failure is very early, even earlier than grub. There are 3 virtqueues (ctrl, event and cmd) for virtio scsi device, but ovmf and seabios will only set the physical address for the 3rd one (cmd). Then in vhost_virtqueue_start(), virtio_queue_get_desc_addr will be 0 for ctrl and event vq when qemu negotiates with ovmf. So vhost_memory_map fails with ENOMEM. This patch just fixs it by early quitting the virtqueue start/stop when virtio_queue_get_desc_addr is 0. Btw, after guest kernel starts, all the 3 queues will be initialized and set address correctly. Already tested on Arm64 and X86_64 qemu. Signed-off-by: Jia He <jia.he@hxt-semitech.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * vhost: fix memslot limit checkJay Zhou2018-03-011-7/+12
| | | | | | | | | | | | | | | | | | | | | | Since used_memslots will be updated to the actual value after registering memory listener for the first time, move the memslots limit checking to the right place. Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Jay Zhou <jianjay.zhou@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * docs: pcie: Spell out machine type needs for PCIe featuresKashyap Chamarthy2018-03-011-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCIe features are available only via the 'q35' machine type for x86 and the 'virt' machine type for AArch64 architecture. Mention that explicitly. Thanks: Daniel Berrangé Signed-off-by: Kashyap Chamarthy <kchamart@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * docs: document virtio-balloon statsTomáš Golembiovský2018-03-011-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Document statistics added in commits commit a0d06486b445985b8d128df172daefbae205bffd Author: Denis V. Lunev <den@openvz.org> Date: Wed Feb 24 10:50:48 2016 +0300 virtio-balloon: add 'available' counter and commit bf1e7140ef0b3a149860ab9f05b36665133238f6 Author: Tomáš Golembiovský <tgolembi@redhat.com> Date: Tue Dec 5 13:14:46 2017 +0100 virtio-balloon: include statistics of disk/file caches Signed-off-by: Tomáš Golembiovský <tgolembi@redhat.com> Reviewed-by: Jonathan Helman <jonathan.helman@oracle.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * intel-iommu: Accept 64-bit writes to FEADDRJan Kiszka2018-03-011-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | Xen is doing this [1] and currently triggers an abort. [1] http://xenbits.xenproject.org/gitweb/?p=xen.git;a=blob;f=xen/drivers/passthrough/vtd/iommu.c;h=daaed0abbdd06b6ba3d948ea103aadf02651e83c;hb=refs/heads/master#l1108 Reported-by: Luis Lloret <luis_lloret@mentor.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * virtio-pci: trivial fixes in error messageGreg Kurz2018-03-011-1/+1
| | | | | | | | | | | | Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * vhost-user: fix memory leaklinzhecheng2018-03-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | g_free() was moved from vhost_net_cleanup in commit e6bcb1b, so we should free net after vhost_net_cleanup Signed-off-by: linzhecheng <linzhecheng@huawei.com> Reviewed-by: Marc-André Lureau < marcandre.lureau@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
* | Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20180301-v2' into ↵Peter Maydell2018-03-0140-606/+1222
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging - add query-cpus-fast and deprecate query-cpus, while adding s390 cpu information - remove s390x memory hotplug implementation, which is not useable in this form - add boot menu support in the s390-ccw bios - expose s390x guest crash information - fixes and cleaups # gpg: Signature made Thu 01 Mar 2018 12:54:47 GMT # gpg: using RSA key DECF6B93C6F02FAF # gpg: Good signature from "Cornelia Huck <conny@cornelia-huck.de>" # gpg: aka "Cornelia Huck <huckc@linux.vnet.ibm.com>" # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" # gpg: aka "Cornelia Huck <cohuck@kernel.org>" # gpg: aka "Cornelia Huck <cohuck@redhat.com>" # Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0 18CE DECF 6B93 C6F0 2FAF * remotes/cohuck/tags/s390x-20180301-v2: (27 commits) s390x/tcg: fix loading 31bit PSWs with the highest bit set s390x: remove s390_get_memslot_count s390x/sclp: remove memory hotplug support s390x/cpumodel: document S390FeatDef.bit not applicable hmp: change hmp_info_cpus to use query-cpus-fast qemu-doc: deprecate query-cpus qmp: add architecture specific cpu data for query-cpus-fast qmp: add query-cpus-fast qmp: expose s390-specific CPU info s390x/tcg: add various alignment checks s390x/tcg: fix disabling/enabling DAT s390/stattrib: Make SaveVMHandlers data static s390x/cpu: expose the guest crash information pc-bios/s390: Rebuild the s390x firmware images with the boot menu changes s390-ccw: interactive boot menu for scsi s390-ccw: use zipl values when no boot menu options are present s390-ccw: set cp_receive mask only when needed and consume pending service irqs s390-ccw: read user input for boot index via the SCLP console s390-ccw: print zipl boot menu s390-ccw: read stage2 boot loader data to find menu ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | s390x/tcg: fix loading 31bit PSWs with the highest bit setDavid Hildenbrand2018-03-011-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Let's also put the 31-bit hack in front of the REAL MMU, otherwise right now we get errors when loading a PSW where the highest bit is set (e.g. via s390-netboot.img). The highest bit is not masked away, therefore we inject addressing exceptions into the guest. The proper fix will later be to do all address wrapping before accessing the MMU - so we won't get any "wrong" entries in there (which makes flushing also easier). But that will require more work (wrapping in load_psw, wrapping when incrementing the PC, wrapping every memory access). This fixes the tests/pxe-test test. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180301120826.6847-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
| * | Merge tag 'tags/s390-ccw-bios-2018-02-26' into s390-nextCornelia Huck2018-02-2715-126/+757
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Boot menu patches by Collin L. Walling # gpg: Signature made Mon 26 Feb 2018 11:24:21 AM CET # gpg: using RSA key 2ED9D774FE702DB5 # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [undefined] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [undefined] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] * tag 'tags/s390-ccw-bios-2018-02-26': pc-bios/s390: Rebuild the s390x firmware images with the boot menu changes s390-ccw: interactive boot menu for scsi s390-ccw: use zipl values when no boot menu options are present s390-ccw: set cp_receive mask only when needed and consume pending service irqs s390-ccw: read user input for boot index via the SCLP console s390-ccw: print zipl boot menu s390-ccw: read stage2 boot loader data to find menu s390-ccw: set up interactive boot menu parameters s390-ccw: parse and set boot menu options s390-ccw: move auxiliary IPL data to separate location s390-ccw: update libc s390-ccw: refactor IPL structs s390-ccw: refactor eckd_block_num to use CHS s390-ccw: refactor boot map table code
| | * | pc-bios/s390: Rebuild the s390x firmware images with the boot menu changesThomas Huth2018-02-262-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide a new s390-ccw.img binary with the boot menu patches by Collin. Though there should not be any visible changes for the network booting, the s390-netboot.img binary has been rebuilt, too, since some of the changes affected the shared source files. Signed-off-by: Thomas Huth <thuth@redhat.com>
| | * | s390-ccw: interactive boot menu for scsiCollin L. Walling2018-02-265-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Interactive boot menu for scsi. This follows a similar procedure as the interactive menu for eckd dasd. An example follows: s390x Enumerated Boot Menu. 3 entries detected. Select from index 0 to 2. Signed-off-by: Collin L. Walling <walling@linux.vnet.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> [thuth: Added additional "break;" statement to avoid analyzer warnings] Signed-off-by: Thomas Huth <thuth@redhat.com>
| | * | s390-ccw: use zipl values when no boot menu options are presentCollin L. Walling2018-02-265-2/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If no boot menu options are present, then flag the boot menu to use the zipl options that were set in the zipl configuration file (and stored on disk by zipl). These options are found at some offset prior to the start of the zipl boot menu banner. The zipl timeout value is limited to a 16-bit unsigned integer and stored as seconds, so we take care to convert it to milliseconds in order to conform to the rest of the boot menu functionality. This is limited to CCW devices. For reference, the zipl configuration file uses the following fields in the menu section: prompt=1 enable the boot menu timeout=X set the timeout to X seconds To explicitly disregard any boot menu options, then menu=off or <bootmenu enable='no' ... /> must be specified. Signed-off-by: Collin L. Walling <walling@linux.vnet.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
| | * | s390-ccw: set cp_receive mask only when needed and consume pending service irqsCollin L. Walling2018-02-263-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is possible while waiting for multiple types of external interrupts that we might have pending irqs remaining between irq consumption and irq-type disabling. Those interrupts could potentially propagate to the guest after IPL completes and cause unwanted behavior. As it is today, the SCLP will only recognize write events that are enabled by the control program's send and receive masks. To limit the window for, and prevent further irqs from, ASCII console events (specifically keystrokes), we should only enable the control program's receive mask when we need it. While we're at it, remove assignment of the (non control program) send and receive masks, as those are actually set by the SCLP. Signed-off-by: Collin L. Walling <walling@linux.vnet.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>