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* qapi: Convert simple union TransactionAction to flat oneMarkus Armbruster2021-09-271-26/+113
| | | | | | | | | | | | | | | | | | | Simple unions predate flat unions. Having both complicates the QAPI schema language and the QAPI generator. We haven't been using simple unions in new code for a long time, because they are less flexible and somewhat awkward on the wire. To prepare for their removal, convert simple union TransactionAction to an equivalent flat one. Adds some boilerplate to the schema, which is a bit ugly, but a lot easier to maintain than the simple union feature. Cc: Kevin Wolf <kwolf@redhat.com> Cc: Hanna Reitz <hreitz@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Acked-by: Hanna Reitz <hreitz@redhat.com> Message-Id: <20210917143134.412106-11-armbru@redhat.com>
* qapi: Convert simple union ImageInfoSpecific to flat oneMarkus Armbruster2021-09-271-7/+52
| | | | | | | | | | | | | | | | | | | | | | Simple unions predate flat unions. Having both complicates the QAPI schema language and the QAPI generator. We haven't been using simple unions in new code for a long time, because they are less flexible and somewhat awkward on the wire. To prepare for their removal, convert simple union ImageInfoSpecific to an equivalent flat one. Adds some boilerplate to the schema, which is a bit ugly, but a lot easier to maintain than the simple union feature. Implicit enum ImageInfoSpecificKind becomes explicit. It duplicates part of enum BlockdevDriver. We could reuse BlockdevDriver instead. Cc: Kevin Wolf <kwolf@redhat.com> Cc: Hanna Reitz <hreitz@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Acked-by: Hanna Reitz <hreitz@redhat.com> Message-Id: <20210917143134.412106-10-armbru@redhat.com>
* qapi: Convert simple union SocketAddressLegacy to flat oneMarkus Armbruster2021-09-275-19/+51
| | | | | | | | | | | | | | | | | | Simple unions predate flat unions. Having both complicates the QAPI schema language and the QAPI generator. We haven't been using simple unions in new code for a long time, because they are less flexible and somewhat awkward on the wire. To prepare for their removal, convert simple union SocketAddressLegacy to an equivalent flat one, with existing enum SocketAddressType replacing implicit enum type SocketAddressLegacyKind. Adds some boilerplate to the schema, which is a bit ugly, but a lot easier to maintain than the simple union feature. Cc: "Daniel P. Berrangé" <berrange@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Message-Id: <20210917143134.412106-9-armbru@redhat.com>
* qapi: Convert simple union ChardevBackend to flat oneMarkus Armbruster2021-09-271-22/+168
| | | | | | | | | | | | | | | | | | | Simple unions predate flat unions. Having both complicates the QAPI schema language and the QAPI generator. We haven't been using simple unions in new code for a long time, because they are less flexible and somewhat awkward on the wire. To prepare for their removal, convert simple union ChardevBackend to an equivalent flat one. Adds some boilerplate to the schema, which is a bit ugly, but a lot easier to maintain than the simple union feature. Cc: "Marc-André Lureau" <marcandre.lureau@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Message-Id: <20210917143134.412106-8-armbru@redhat.com> [Missing conditionals added]
* qapi: Convert simple union MemoryDeviceInfo to flat oneMarkus Armbruster2021-09-271-4/+38
| | | | | | | | | | | | | | | | | | Simple unions predate flat unions. Having both complicates the QAPI schema language and the QAPI generator. We haven't been using simple unions in new code for a long time, because they are less flexible and somewhat awkward on the wire. To prepare for their removal, convert simple union MemoryDeviceInfo to an equivalent flat one. Adds some boilerplate to the schema, which is a bit ugly, but a lot easier to maintain than the simple union feature. Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Message-Id: <20210917143134.412106-7-armbru@redhat.com>
* qapi: Convert simple union TpmTypeOptions to flat oneMarkus Armbruster2021-09-274-8/+28
| | | | | | | | | | | | | | | | | | | | Simple unions predate flat unions. Having both complicates the QAPI schema language and the QAPI generator. We haven't been using simple unions in new code for a long time, because they are less flexible and somewhat awkward on the wire. To prepare for their removal, convert simple union TpmTypeOptions to an equivalent flat one, with existing enum TpmType replacing implicit enum TpmTypeOptionsKind. Adds some boilerplate to the schema, which is a bit ugly, but a lot easier to maintain than the simple union feature. Cc: Stefan Berger <stefanb@linux.vnet.ibm.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Acked-by: Stefan Berger <stefanb@linux.ibm.com> Reviewed-by: Eric Blake <eblake@redhat.com> Message-Id: <20210917143134.412106-6-armbru@redhat.com> [Indentation tidied up]
* qapi: Convert simple union InputEvent to flat oneMarkus Armbruster2021-09-251-4/+38
| | | | | | | | | | | | | | | | Simple unions predate flat unions. Having both complicates the QAPI schema language and the QAPI generator. We haven't been using simple unions in new code for a long time, because they are less flexible and somewhat awkward on the wire. To prepare for their removal, convert simple union InputEvent to an equivalent flat one. Adds some boilerplate to the schema, which is a bit ugly, but a lot easier to maintain than the simple union feature. Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Message-Id: <20210917143134.412106-5-armbru@redhat.com>
* qapi: Convert simple union KeyValue to flat oneMarkus Armbruster2021-09-251-2/+28
| | | | | | | | | | | | | | | | Simple unions predate flat unions. Having both complicates the QAPI schema language and the QAPI generator. We haven't been using simple unions in new code for a long time, because they are less flexible and somewhat awkward on the wire. To prepare for their removal, convert simple union KeyValue to an equivalent flat one. Adds some boilerplate to the schema, which is a bit ugly, but a lot easier to maintain than the simple union feature. Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Message-Id: <20210917143134.412106-4-armbru@redhat.com>
* qapi: Stop enforcing "type name should not end in 'Kind'Markus Armbruster2021-09-255-8/+3
| | | | | | | | | | | | | I'm about to convert simple unions to flat unions, then drop simple union support. The conversion involves making the implict enum types explicit. To reduce churn, I'd like to name them exactly like the implicit types they replace. However, these names are reserved for the generator's use. They won't be once simple unions are gone. Stop enforcing this naming rule now rather than then. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Message-Id: <20210917143134.412106-3-armbru@redhat.com>
* qapi: Tidy up unusual line breaksMarkus Armbruster2021-09-254-24/+24
| | | | | | | | Break lines between members instead of within members. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20210917143134.412106-2-armbru@redhat.com>
* Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20210921' into stagingRichard Henderson2021-09-2434-315/+119
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move cpu_signal_handler declaration. Restrict cpu_handle_halt to sysemu. Make do_unaligned_access noreturn. Misc tcg/mips cleanup Misc tcg/sparc cleanup Misc tcg/riscv cleanup # gpg: Signature made Tue 21 Sep 2021 10:47:29 PM EDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate] * remotes/rth/tags/pull-tcg-20210921: tcg/riscv: Remove add with zero on user-only memory access hw/core: Make do_unaligned_access noreturn tcg/sparc: Introduce tcg_out_mov_delay tcg/sparc: Drop inline markers tcg/mips: Drop special alignment for code_gen_buffer tcg/mips: Unset TCG_TARGET_HAS_direct_jump tcg/mips: Allow JAL to be out of range in tcg_out_bswap_subr tcg/mips: Drop inline markers accel/tcg: Restrict cpu_handle_halt() to sysemu include/exec: Move cpu_signal_handler declaration Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg/riscv: Remove add with zero on user-only memory accessRichard Henderson2021-09-211-8/+2
| | | | | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * hw/core: Make do_unaligned_access noreturnRichard Henderson2021-09-2112-21/+23
| | | | | | | | | | | | | | | | | | | | While we may have had some thought of allowing system-mode to return from this hook, we have no guests that require this. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg/sparc: Introduce tcg_out_mov_delayRichard Henderson2021-09-211-6/+15
| | | | | | | | | | | | | | | | | | | | | | This version of tcg_out_mov is emits a nop to fill the delay slot if the move is not required. The only current use, for INDEX_op_goto_ptr, will always require the move but properly documents the delay slot. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg/sparc: Drop inline markersRichard Henderson2021-09-211-23/+22
| | | | | | | | | | | | | | Let the compiler decide about inlining. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg/mips: Drop special alignment for code_gen_bufferRichard Henderson2021-09-211-91/+0
| | | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg/mips: Unset TCG_TARGET_HAS_direct_jumpRichard Henderson2021-09-212-25/+10
| | | | | | | | | | | | | | | | Only use indirect jumps. Finish weaning away from the unique alignment requirements for code_gen_buffer. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg/mips: Allow JAL to be out of range in tcg_out_bswap_subrRichard Henderson2021-09-211-2/+4
| | | | | | | | | | | | | | | | | | | | Weaning off of unique alignment requirements, so allow JAL to not reach the target. TCG_TMP1 is always available for use as a scratch because it is clobbered by the subroutine being called. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg/mips: Drop inline markersRichard Henderson2021-09-211-49/+27
| | | | | | | | | | | | | | | | Let the compiler decide about inlining. Remove tcg_out_ext8s and tcg_out_ext16s as unused. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * accel/tcg: Restrict cpu_handle_halt() to sysemuPhilippe Mathieu-Daudé2021-09-211-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 372579427a5 ("tcg: enable thread-per-vCPU") added the following comment describing EXCP_HALTED in qemu_tcg_cpu_thread_fn(): case EXCP_HALTED: /* during start-up the vCPU is reset and the thread is * kicked several times. If we don't ensure we go back * to sleep in the halted state we won't cleanly * start-up when the vCPU is enabled. * * cpu->halted should ensure we sleep in wait_io_event */ g_assert(cpu->halted); break; qemu_wait_io_event() is sysemu-specific, so we can restrict the cpu_handle_halt() call in cpu_exec() to system emulation. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210912172731.789788-2-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * include/exec: Move cpu_signal_handler declarationRichard Henderson2021-09-2122-89/+13
| | | | | | | | | | | | | | | | | | | | There is nothing target specific about this. The implementation is host specific, but the declaration is 100% common. Reviewed-By: Warner Losh <imp@bsdimp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | Merge remote-tracking branch ↵Peter Maydell2021-09-244-69/+46
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/vivier2/tags/linux-user-for-6.2-pull-request' into staging Pull request linux-user 20210924 Clean up siginfo_t handling for arm, aarch64 # gpg: Signature made Fri 24 Sep 2021 14:56:12 BST # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/linux-user-for-6.2-pull-request: linux-user/aarch64: Use force_sig_fault() linux-user/arm: Use force_sig_fault() linux-user: Provide new force_sig_fault() function linux-user: Zero out target_siginfo_t in force_sig() linux-user/arm: Use force_sig() to deliver fpa11 emulation SIGFPE linux-user/arm: Set siginfo_t addr field for SIGTRAP signals linux-user/aarch64: Set siginfo_t addr field for SIGTRAP signals Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | linux-user/aarch64: Use force_sig_fault()Peter Maydell2021-09-231-25/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the new force_sig_fault() function instead of setting up a target_siginfo_t and calling queue_signal(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210813131809.28655-8-peter.maydell@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * | linux-user/arm: Use force_sig_fault()Peter Maydell2021-09-231-38/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the new force_sig_fault() function instead of setting up a target_siginfo_t and calling queue_signal(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210813131809.28655-7-peter.maydell@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * | linux-user: Provide new force_sig_fault() functionPeter Maydell2021-09-232-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In many places in the linux-user code we need to queue a signal for the guest using the QEMU_SI_FAULT si_type. This requires that the caller sets up and passes us a target_siginfo, including setting the appropriate part of the _sifields union for the si_type. In a number of places the code forgets to set the _sifields union field. Provide a new force_sig_fault() function, which does the same thing as the Linux kernel function of that name -- it takes the signal number, the si_code value and the address to use in _sifields._sigfault, and assembles the target_siginfo itself. This makes the callsites simpler and means it's harder to forget to pass in an address value. We follow force_sig() and the kernel's force_sig_fault() in not requiring the caller to pass in the CPU pointer but always acting on the CPU of the current thread. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210813131809.28655-6-peter.maydell@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * | linux-user: Zero out target_siginfo_t in force_sig()Peter Maydell2021-09-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The target_siginfo_t we populate in force_sig() will eventually get copied onto the target's stack. Zero it out so that any extra padding in the sifields union is consistently zero when the guest sees it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210813131809.28655-5-peter.maydell@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * | linux-user/arm: Use force_sig() to deliver fpa11 emulation SIGFPEPeter Maydell2021-09-231-7/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the Arm target code, when the fpa11 emulation code tells us we need to send the guest a SIGFPE, we do this with queue_signal(), but we are using the wrong si_type, and we aren't setting the _sifields union members corresponding to either the si_type we are using or the si_type we should be using. As the existing comment notes, the kernel code for this calls the old send_sig() function to deliver the signal. This eventually results in the kernel's signal handling code fabricating a siginfo_t with a SI_KERNEL code and a zero pid and uid. For QEMU this means we need to use QEMU_SI_KILL. We already have a function for that: force_sig() sets up the whole target_siginfo_t the way we need it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210813131809.28655-4-peter.maydell@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * | linux-user/arm: Set siginfo_t addr field for SIGTRAP signalsPeter Maydell2021-09-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When generating a TRAP_BRKPT SIGTRAP, set the siginfo_t addr field to the PC where the breakpoint/singlestep trap occurred; this is what the kernel does for this signal for this architecture. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210813131809.28655-3-peter.maydell@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * | linux-user/aarch64: Set siginfo_t addr field for SIGTRAP signalsPeter Maydell2021-09-231-0/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | When generating a TRAP_BRKPT SIGTRAP, set the siginfo_t addr field to the PC where the breakpoint/singlestep trap occurred; this is what the kernel does for this signal for this architecture. Fixes: Coverity 1459154 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210813131809.28655-2-peter.maydell@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* | Merge remote-tracking branch 'remotes/nvme/tags/nvme-next-pull-request' into ↵Peter Maydell2021-09-243-13/+25
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging hw/nvme updates # gpg: Signature made Fri 24 Sep 2021 07:44:23 BST # gpg: using RSA key 522833AA75E2DCE6A24766C04DE1AF316D4F0DE9 # gpg: Good signature from "Klaus Jensen <its@irrelevant.dk>" [unknown] # gpg: aka "Klaus Jensen <k.jensen@samsung.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: DDCA 4D9C 9EF9 31CC 3468 4272 63D5 6FC5 E55D A838 # Subkey fingerprint: 5228 33AA 75E2 DCE6 A247 66C0 4DE1 AF31 6D4F 0DE9 * remotes/nvme/tags/nvme-next-pull-request: hw/nvme: Return error for fused operations hw/nvme: fix verification of select field in namespace attachment hw/nvme: fix validation of ASQ and ACQ Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/nvme: Return error for fused operationsPankaj Raghav2021-09-241-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, FUSED operations are not supported by QEMU. As per the 1.4 SPEC, controller should abort the command that requested a fused operation with an INVALID FIELD error code if they are not supported. Changes from v1: Added FUSE flag check also to the admin cmd processing as the FUSED operations are mentioned in the general SQE section in the SPEC. Signed-off-by: Pankaj Raghav <p.raghav@samsung.com> Reviewed-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
| * hw/nvme: fix verification of select field in namespace attachmentNaveen Nagar2021-09-242-3/+17
| | | | | | | | | | | | | | | | | | Fix is added to check for reserved value in select field for namespace attachment CC: Minwoo Im <minwoo.im.dev@gmail.com> Signed-off-by: Naveen Nagar <naveen.n1@samsung.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
| * hw/nvme: fix validation of ASQ and ACQKlaus Jensen2021-09-242-10/+0
|/ | | | | | | | Address 0x0 is a valid address. Fix the admin submission and completion queue address validation to not error out on this. Signed-off-by: Klaus Jensen <k.jensen@samsung.com> Reviewed-by: Keith Busch <kbusch@kernel.org>
* Merge remote-tracking branch ↵Richard Henderson2021-09-2134-669/+1844
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/alistair23/tags/pull-riscv-to-apply-20210921' into staging Second RISC-V PR for QEMU 6.2 - ePMP CSR address updates - Convert internal interrupts to use QEMU GPIO lines - SiFive PWM support - Support for RISC-V ACLINT - SiFive PDMA fixes - Update to u-boot instructions for sifive_u - mstatus.SD bug fix for hypervisor extensions - OpenTitan fix for USB dev address # gpg: Signature made Mon 20 Sep 2021 11:52:26 PM PDT # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair23/tags/pull-riscv-to-apply-20210921: (21 commits) hw/riscv: opentitan: Correct the USB Dev address target/riscv: csr: Rename HCOUNTEREN_CY and friends target/riscv: Backup/restore mstatus.SD bit when virtual register swapped docs/system/riscv: sifive_u: Update U-Boot instructions hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer hw/dma: sifive_pdma: allow non-multiple transaction size transactions hw/dma: sifive_pdma: claim bit must be set before DMA transactions hw/dma: sifive_pdma: reset Next* registers when Control.claim is set hw/riscv: virt: Add optional ACLINT support to virt machine hw/riscv: virt: Re-factor FDT generation hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT hw/intc: Rename sifive_clint sources to riscv_aclint sources sifive_u: Connect the SiFive PWM device hw/timer: Add SiFive PWM support hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines hw/intc: sifive_clint: Use RISC-V CPU GPIO lines target/riscv: Expose interrupt pending bits as GPIO lines target/riscv: Fix satp write ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * hw/riscv: opentitan: Correct the USB Dev addressAlistair Francis2021-09-211-1/+1
| | | | | | | | | | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: d6cb4dfe75a2f536f217d7075b750ece3acb1535.1631767043.git.alistair.francis@wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: csr: Rename HCOUNTEREN_CY and friendsBin Meng2021-09-212-16/+16
| | | | | | | | | | | | | | | | | | | | | | The macro name HCOUNTEREN_CY suggests it is for CSR HCOUNTEREN, but in fact it applies to M-mode and S-mode CSR too. Rename these macros to have the COUNTEREN_ prefix. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210915084601.24304-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: Backup/restore mstatus.SD bit when virtual register swappedFrank Chang2021-09-211-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When virtual registers are swapped, mstatus.SD bit should also be backed up/restored. Otherwise, mstatus.SD bit will be incorrectly kept across the world switches. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Vincent Chen <vincent.chen@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210914013717.881430-1-frank.chang@sifive.com [ Changes by AF: - Convert variable to a uint64_t to fix clang error ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * docs/system/riscv: sifive_u: Update U-Boot instructionsBin Meng2021-09-211-23/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In U-Boot v2021.07 release, there were 2 major changes for the SiFive Unleashed board support: - Board config name was changed from sifive_fu540_defconfig to sifive_unleashed_defconfig - The generic binman tool was used to generate the FIT image (combination of U-Boot proper, DTB and OpenSBI firmware) which make the existing U-Boot instructions out of date. Update the doc with latest instructions. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210911153431.10362-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transferFrank Chang2021-09-211-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Real PDMA doesn't set Control.error if there are 0 bytes to be transferred. The DMA transfer is still success. The following result is PDMA tested in U-Boot on Unmatched board: => mw.l 0x3000000 0x0 <= Disclaim channel 0 => mw.l 0x3000000 0x1 <= Claim channel 0 => mw.l 0x3000004 0x55000000 <= wsize = rsize = 5 (2^5 = 32 bytes) => mw.q 0x3000008 0x0 <= NextBytes = 0 => mw.q 0x3000010 0x84000000 <= NextDestination = 0x84000000 => mw.q 0x3000018 0x84001000 <= NextSource = 0x84001000 => mw.l 0x84000000 0x87654321 <= Fill test data to dst => mw.l 0x84001000 0x12345678 <= Fill test data to src => md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents 84000000: 87654321 !Ce. 84001000: 12345678 xV4. => md.l 0x3000000 8 <= Dump PDMA status 03000000: 00000001 55000000 00000000 00000000 .......U........ 03000010: 84000000 00000000 84001000 00000000 ................ => mw.l 0x3000000 0x3 <= Set channel 0 run and claim bits => md.l 0x3000000 8 <= Dump PDMA status 03000000: 40000001 55000000 00000000 00000000 ...@...U........ 03000010: 84000000 00000000 84001000 00000000 ................ => md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents 84000000: 87654321 !Ce. 84001000: 12345678 xV4. Signed-off-by: Frank Chang <frank.chang@sifive.com> Tested-by: Max Hsu <max.hsu@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210912130553.179501-5-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * hw/dma: sifive_pdma: allow non-multiple transaction size transactionsGreen Wan2021-09-211-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Real PDMA is able to deal with non-multiple transaction size transactions. The following result is PDMA tested in U-Boot on Unmatched board: => mw.l 0x3000000 0x0 <= Disclaim channel 0 => mw.l 0x3000000 0x1 <= Claim channel 0 => mw.l 0x3000004 0x11000000 <= wsize = rsize = 1 (2^1 = 2 bytes) => mw.q 0x3000008 0x3 <= NextBytes = 3 => mw.q 0x3000010 0x84000000 <= NextDestination = 0x84000000 => mw.q 0x3000018 0x84001000 <= NextSource = 0x84001000 => mw.l 0x84000000 0x87654321 <= Fill test data to dst => mw.l 0x84001000 0x12345678 <= Fill test data to src => md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents 84000000: 87654321 !Ce. 84001000: 12345678 xV4. => md.l 0x3000000 8 <= Dump PDMA status 03000000: 00000001 11000000 00000003 00000000 ................ 03000010: 84000000 00000000 84001000 00000000 ................ => mw.l 0x3000000 0x3 <= Set channel 0 run and claim bits => md.l 0x3000000 8 <= Dump PDMA status 03000000: 40000001 11000000 00000003 00000000 ...@............ 03000010: 84000000 00000000 84001000 00000000 ................ => md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents 84000000: 87345678 xV4. 84001000: 12345678 xV4. Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Tested-by: Max Hsu <max.hsu@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-id: 20210912130553.179501-4-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * hw/dma: sifive_pdma: claim bit must be set before DMA transactionsFrank Chang2021-09-211-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Real PDMA must have Control.claim bit to be set before Control.run bit is set to start any DMA transactions. Otherwise nothing will be transferred. The following result is PDMA tested in U-Boot on Unmatched board: => mw.l 0x3000000 0x0 <= Disclaim channel 0 (Channel 0 is not claimed) => mw.l 0x3000004 0x55000000 <= wsize = rsize = 5 (2^5 = 32 bytes) => mw.q 0x3000008 0x2 <= NextBytes = 2 => mw.q 0x3000010 0x84000000 <= NextDestination = 0x84000000 => mw.q 0x3000018 0x84001000 <= NextSource = 0x84001000 => mw.l 0x84000000 0x87654321 <= Fill test data to dst => mw.l 0x84001000 0x12345678 <= Fill test data to src => md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents 84000000: 87654321 !Ce. 84001000: 12345678 xV4. => md.l 0x3000000 8 <= Dump PDMA status 03000000: 00000000 55000000 00000002 00000000 .......U........ 03000010: 84000000 00000000 84001000 00000000 ................ => mw.l 0x3000000 0x3 <= Set channel 0 run and claim bits => md.l 0x3000000 8 <= Dump PDMA status 03000000: 00000001 66000000 00000000 00000000 .......f........ 03000010: 00000000 00000000 00000000 00000000 ................ => md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents 84000000: 87654321 !Ce. 84001000: 12345678 xV4. Signed-off-by: Frank Chang <frank.chang@sifive.com> Tested-by: Max Hsu <max.hsu@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210912130553.179501-3-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * hw/dma: sifive_pdma: reset Next* registers when Control.claim is setFrank Chang2021-09-211-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | Setting Control.claim clears all of the chanel's Next registers. This is effective only when Control.claim is set from 0 to 1. Signed-off-by: Frank Chang <frank.chang@sifive.com> Tested-by: Max Hsu <max.hsu@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210912130553.179501-2-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * hw/riscv: virt: Add optional ACLINT support to virt machineAnup Patel2021-09-213-1/+124
| | | | | | | | | | | | | | | | | | | | | | We extend virt machine to emulate ACLINT devices only when "aclint=on" parameter is passed along with machine name in QEMU command-line. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210831110603.338681-5-anup.patel@wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * hw/riscv: virt: Re-factor FDT generationAnup Patel2021-09-211-200/+327
| | | | | | | | | | | | | | | | | | | | | | | | We re-factor and break the FDT generation into smaller functions so that it is easier to modify FDT generation for different configurations of virt machine. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210831110603.338681-4-anup.patel@wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINTAnup Patel2021-09-218-156/+339
| | | | | | | | | | | | | | | | | | | | | | | | | | The RISC-V ACLINT is more modular and backward compatible with original SiFive CLINT so instead of duplicating the original SiFive CLINT implementation we upgrade the current SiFive CLINT implementation to RISC-V ACLINT implementation. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210831110603.338681-3-anup.patel@wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * hw/intc: Rename sifive_clint sources to riscv_aclint sourcesAnup Patel2021-09-2111-15/+15
| | | | | | | | | | | | | | | | | | | | | | We will be upgrading SiFive CLINT implementation into RISC-V ACLINT implementation so let's first rename the sources. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210831110603.338681-2-anup.patel@wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * sifive_u: Connect the SiFive PWM deviceAlistair Francis2021-09-214-2/+69
| | | | | | | | | | | | | | | | Connect the SiFive PWM device and expose it via the device tree. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 22f98648b4e012f78529a56f5ca60b0b27852a4d.1631159656.git.alistair.francis@wdc.com
| * hw/timer: Add SiFive PWM supportAlistair Francis2021-09-215-0/+540
| | | | | | | | | | | | | | | | | | | | | | | | This is the initial commit of the SiFive PWM timer. This is used by guest software as a timer and is included in the SiFive FU540 SoC. Signed-off-by: Justin Restivo <jrestivo@draper.com> Signed-off-by: Alexandra Clifford <aclifford@draper.com> Signed-off-by: Amanda Strnad <astrnad@draper.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 9f70a210acbfaf0e1ea6ad311ab892ac69134d8b.1631159656.git.alistair.francis@wdc.com
| * hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO linesAlistair Francis2021-09-213-5/+17
| | | | | | | | | | | | | | | | | | | | Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V CPU GPIO lines to set the timer MIP bits. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 84d5b1d5783d2e79eee69a2f7ac480cc0c070db3.1630301632.git.alistair.francis@wdc.com
| * hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis2021-09-217-12/+33
| | | | | | | | | | | | | | | | | | | | | | | | Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V CPU GPIO lines to set the external MIP bits. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 0364190bfa935058a845c0fa1ecf650328840ad5.1630301632.git.alistair.francis@wdc.com