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* hw/arm/aspeed_ast27x0 Introduce vbootrom memory regionJamin Lin2025-05-052-0/+11
| | | | | | | | | | | | | | | | | Introduce a new vbootrom memory region. The region is mapped at address "0x00000000" and has a size of 128KB, identical to the SRAM region size. This memory region is intended for loading a vbootrom image file as part of the boot process. The vbootrom registered in the SoC's address space using the ASPEED_DEV_VBOOTROM index. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Nabih Estefan <nabihestefan@google.com> Tested-by: Nabih Estefan <nabihestefan@google.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250424075135.3715128-2-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
* tests/functional/aspeed: extract boot and login sequence into helper functionJamin Lin2025-05-051-5/+7
| | | | | | | | | | Extracted repeated boot and login steps into a new helper function. No change in functional behavior. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250423072350.541742-10-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
* tests/functional/aspeed: Update test ASPEED SDK v09.06Jamin Lin2025-05-051-10/+10
| | | | | | | Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250423072350.541742-9-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
* tests/functional/aspeed: Move I2C test into shared helper for AST2700 reuseJamin Lin2025-05-051-13/+15
| | | | | | | | | | | | Move the I2C test case into a common helper function (do_ast2700_i2c_test) so it can be reused across multiple AST2700-based test cases. This reduces duplication and improves maintainability. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Nabih Estefan <nabihestefan@google.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250423072350.541742-8-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
* hw/arm/aspeed_ast27x0: Rename variable sram_name to name in ast2700 realizeJamin Lin2025-05-051-4/+4
| | | | | | | | | | | | The variable "sram_name" was only used for naming the SRAM memory region. Rename it to "name" for consistency with similar code and avoid unnecessary new local variable declarations. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Tested-by: Nabih Estefan <nabihestefan@google.com> Link: https://lore.kernel.org/qemu-devel/20250423072350.541742-2-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
* tests/functional/aspeed: Update test ASPEED SDK v03.00 for AST1030Jamin Lin2025-05-051-5/+5
| | | | | | | Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250423014008.147542-4-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
* tests/functional/aspeed: Update test ASPEED SDK v09.06 for AST2600Jamin Lin2025-05-051-7/+8
| | | | | | | | | Update test for AST2600 production revision A3. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250423014008.147542-3-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
* tests/functional/aspeed: Update test ASPEED SDK v09.06 for AST2500Jamin Lin2025-05-051-4/+4
| | | | | | | Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250423014008.147542-2-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
* hw/ssi/aspeed_smc: Allow 64-bit wide flash accessesJoe Komlodi2025-05-051-2/+2
| | | | | | | | | | | | | | | cde3247651dc998da5dc1005148302a90d72f21f fixed atomicity for LDRD, which ends up making accesses 64-bits wide. However, the AST2600 bootloader can sometimes compile with LDRD instructions, which causes the acceses to fail when accessing the memory-mapped SPI flash. To fix this, increase the MMIO region valid access size to allow for 64-bit accesses. Signed-off-by: Joe Komlodi <komlodi@google.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250422002747.2593465-1-komlodi@google.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
* hw/arm: ast27x0: Wire up EHCI controllersTroy Lee2025-05-052-1/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AST27x0 has 4 EHCI controllers, where each CPU and I/O die has 2 instances. This patch use existing TYPE_PLATFORM_EHCI. After wiring up the EHCI controller, the ast2700a1-evb can find up to 4 USB EHCI interfaces. ehci-platform 12061000.usb: EHCI Host Controller ehci-platform 12061000.usb: new USB bus registered, assigned bus number 2 ehci-platform 12063000.usb: EHCI Host Controller ehci-platform 12063000.usb: new USB bus registered, assigned bus number 3 ehci-platform 12061000.usb: irq 88, io mem 0x12061000 ehci-platform 12063000.usb: irq 90, io mem 0x12063000 ehci-platform 14121000.usb: EHCI Host Controller ehci-platform 14123000.usb: EHCI Host Controller ehci-platform 12061000.usb: USB 2.0 started, EHCI 1.00 ehci-platform 14121000.usb: new USB bus registered, assigned bus number 5 ehci-platform 14123000.usb: new USB bus registered, assigned bus number 6 ehci-platform 14121000.usb: irq 91, io mem 0x14121000 ehci-platform 14123000.usb: irq 92, io mem 0x14123000 ehci-platform 12063000.usb: USB 2.0 started, EHCI 1.00 usb usb2: Manufacturer: Linux 6.6.78-dirty-bafd2830c17c-gbafd2830c17c-dirty ehci_hcd usb usb3: Manufacturer: Linux 6.6.78-dirty-bafd2830c17c-gbafd2830c17c-dirty ehci_hcd ehci-platform 14121000.usb: USB 2.0 started, EHCI 1.00 usb usb5: Manufacturer: Linux 6.6.78-dirty-bafd2830c17c-gbafd2830c17c-dirty ehci_hcd ehci-platform 14123000.usb: USB 2.0 started, EHCI 1.00 usb usb6: Manufacturer: Linux 6.6.78-dirty-bafd2830c17c-gbafd2830c17c-dirty ehci_hcd Note that, AST27x0A0 only has 2 EHCI controllers due to hw issue. Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250317065938.1902272-2-troy_lee@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
* pc-bios: Add AST27x0 vBootromJamin Lin2025-05-024-0/+8
| | | | | | | | | | | | | | | | | | | The boot ROM is a minimal implementation designed to load an AST27x0 boot image. Its source code is available at: https://github.com/google/vbootrom Commit id: d6e3386709b3e49322a94ffadc2aaab9944ab77b Build Information: ``` Build Date : Apr 29 2025 01:23:18 FW Version : git-d6e3386 ``` Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Nabih Estefan <nabihestefan@google.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Tested-by: Nabih Estefan <nabihestefan@google.com> Link: https://lore.kernel.org/qemu-devel/20250429062822.1184920-2-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
* Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into stagingStefan Hajnoczi2025-04-301-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull request Kevin's fix for the divide-by-zero in my recent discard commit, triggered when a host block device does not support discard. # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEEhpWov9P5fNqsNXdanKSrs4Grc8gFAmgSRfsACgkQnKSrs4Gr # c8hGBwf8CBoDZzCJAE1sw2GSKnnd3J2qGf4Kg6CcMYOSZ8TLssDKQj6HG2gfWaJZ # it9g9zq7TsodWCyV/qXrzOy5aa7WX8Tsf10O/87baFqGOp82KMPX8jQK1csRnTTF # QyDocZhIvO+QJXnmnFjtvY7qfaxkzaT/8U+mWgaQM2zG83BNGg3uNyRPyz+RAfYl # tVM3xNf2ETbN3D8SIOcpr80/tiWP8dZ8xTLyTfBYPbIP59QX2+Iu8BtLFt9npwT6 # kABnFkqnE/pA6FJz0ZIVenduOBs7IUSQFNvmxAjYIwxowQKsk4WFfjJEKHIHzwwO # a64i43DcH8XgjCcueJ11DnmoB5RfAg== # =yODA # -----END PGP SIGNATURE----- # gpg: Signature made Wed 30 Apr 2025 11:47:07 EDT # gpg: using RSA key 8695A8BFD3F97CDAAC35775A9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" [ultimate] # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" [ultimate] # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * tag 'block-pull-request' of https://gitlab.com/stefanha/qemu: file-posix: Fix crash on discard_granularity == 0 Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * file-posix: Fix crash on discard_granularity == 0Kevin Wolf2025-04-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Block devices that don't support discard have a discard_granularity of 0. Currently, this results in a division by zero when we try to make sure that it's a multiple of request_alignment. Only try to update bs->bl.pdiscard_alignment when we got a non-zero discard_granularity from sysfs. Fixes: f605796aae4 ('file-posix: probe discard alignment on Linux block devices') Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Message-ID: <20250429155654.102735-1-kwolf@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
* | Merge tag 'pull-tcg-20250429' of https://gitlab.com/rth7680/qemu into stagingStefan Hajnoczi2025-04-3060-9322/+11882
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert TCG backend code generators to TCGOutOp structures, decomposing the monolithic tcg_out_op functions. # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmgRDgcdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV+0SQf9Ef8IE5QWjXEws706 # q+1deeDV2xa1sKAHG5fnskk1bXM31Cy4koNdDQbHTtDWedNEzWKyR7FxjlRm+zSW # 6CposaEEsCGxdKUbvraflGbWuf2NUZpJoreNGo9BYZkfNWE9yJ0HlypjpxclziRA # G0Ro4XMevi+yVA3cd8lEmft9cW+woFrVWu5I4tucMwY/8gzWRiHV4Z5YCeCEjD3C # 3YYukhRTaA+7Lyd1G3rcqh8uSsAGGv2NLO26upK1mnVtZOoS/CgKWfBq5enVEuDd # X6T544ipz8Z3eXFgzTzK4nl7TpmO+XEUbja3op7psrLHU84puX1/47HLk4TkHlE+ # 6/95eA== # =vzOx # -----END PGP SIGNATURE----- # gpg: Signature made Tue 29 Apr 2025 13:36:07 EDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20250429' of https://gitlab.com/rth7680/qemu: (161 commits) tcg/sparc64: Implement CTPOP tcg/sparc64: Unexport use_vis3_instructions tcg: Remove tcg_out_op tcg: Convert qemu_st{2} to TCGOutOpLdSt{2} tcg: Convert qemu_ld{2} to TCGOutOpLoad{2} tcg: Merge INDEX_op_{ld,st}_{i32,i64,i128} tcg: Remove INDEX_op_qemu_st8_* tcg: Stash MemOp size in TCGOP_FLAGS tcg: Merge INDEX_op_st*_{i32,i64} tcg: Convert st to TCGOutOpStore tcg: Merge INDEX_op_ld*_{i32,i64} tcg: Convert ld to TCGOutOpLoad tcg: Formalize tcg_out_goto_ptr tcg: Formalize tcg_out_br tcg: Formalize tcg_out_mb tcg: Remove add2/sub2 opcodes tcg/tci: Implement add/sub carry opcodes tcg/sparc64: Implement add/sub carry opcodes tcg/sparc64: Hoist tcg_cond_to_bcond lookup out of tcg_out_movcc tcg/s390x: Use ADD LOGICAL WITH SIGNED IMMEDIATE ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * tcg/sparc64: Implement CTPOPRichard Henderson2025-04-281-5/+22
| | | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg/sparc64: Unexport use_vis3_instructionsRichard Henderson2025-04-282-8/+4
| | | | | | | | | | | | | | This variable is no longer used outside tcg-target.c.inc. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg: Remove tcg_out_opRichard Henderson2025-04-2811-79/+3
| | | | | | | | | | | | | | | | All integer opcodes are now converted to TCGOutOp. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg: Convert qemu_st{2} to TCGOutOpLdSt{2}Richard Henderson2025-04-2811-259/+272
| | | | | | | | | | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg: Convert qemu_ld{2} to TCGOutOpLoad{2}Richard Henderson2025-04-2811-133/+283
| | | | | | | | | | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg: Merge INDEX_op_{ld,st}_{i32,i64,i128}Richard Henderson2025-04-2815-304/+198
| | | | | | | | | | | | | | | | | | Merge into INDEX_op_{ld,st,ld2,st2}, where "2" indicates that two inputs or outputs are required. This simplifies the processing of i64/i128 depending on host word size. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg: Remove INDEX_op_qemu_st8_*Richard Henderson2025-04-2817-44/+7
| | | | | | | | | | | | | | | | | | The i386 backend can now check TCGOP_FLAGS to select the correct set of constraints. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg: Stash MemOp size in TCGOP_FLAGSRichard Henderson2025-04-281-2/+6
| | | | | | | | | | | | | | | | | | This will enable removing INDEX_op_qemu_st8_*_i32, by exposing the operand size to constraint selection. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg: Merge INDEX_op_st*_{i32,i64}Richard Henderson2025-04-286-108/+50
| | | | | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg: Convert st to TCGOutOpStoreRichard Henderson2025-04-2811-312/+341
| | | | | | | | | | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg: Merge INDEX_op_ld*_{i32,i64}Richard Henderson2025-04-286-120/+81
| | | | | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg: Convert ld to TCGOutOpLoadRichard Henderson2025-04-2811-419/+721
| | | | | | | | | | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg: Formalize tcg_out_goto_ptrRichard Henderson2025-04-2811-80/+71
| | | | | | | | | | | | | | | | | | Split these functions out from tcg_out_op. Define outop_goto_ptr generically. Call tcg_out_goto_ptr from tcg_reg_alloc_op. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg: Formalize tcg_out_brRichard Henderson2025-04-2811-53/+60
| | | | | | | | | | | | | | | | Split these functions out from tcg_out_op. Call it directly from tcg_gen_code. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg: Formalize tcg_out_mbRichard Henderson2025-04-2811-51/+28
| | | | | | | | | | | | | | | | | | | | Most tcg backends already have a function for this; the rest can split one out from tcg_out_op. Call it directly from tcg_gen_code. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg: Remove add2/sub2 opcodesRichard Henderson2025-04-2816-217/+3
| | | | | | | | | | | | | | | | All uses have been replaced by add/sub carry opcodes. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg/tci: Implement add/sub carry opcodesRichard Henderson2025-04-284-101/+125
| | | | | | | | | | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg/sparc64: Implement add/sub carry opcodesRichard Henderson2025-04-283-110/+201
| | | | | | | | | | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg/sparc64: Hoist tcg_cond_to_bcond lookup out of tcg_out_movccRichard Henderson2025-04-281-10/+11
| | | | | | | | | | | | | | | | | | Pass the sparc COND_* value not the tcg TCG_COND_* value. This makes the usage within add2/sub2 clearer. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg/s390x: Use ADD LOGICAL WITH SIGNED IMMEDIATERichard Henderson2025-04-281-1/+21
| | | | | | | | | | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg/s390x: Implement add/sub carry opcodesRichard Henderson2025-04-283-68/+95
| | | | | | | | | | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg/s390x: Add TCG_CT_CONST_N32Richard Henderson2025-04-283-3/+8
| | | | | | | | | | | | | | | | | | | | We were using S32 | U32 for add2/sub2. But the ALGFI and SLGFI insns that implement this both have uint32_t immediates. This makes the composite range balanced and enables use of -0xffffffff ... -0x80000001. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg/s390x: Honor carry_live in tcg_out_moviRichard Henderson2025-04-281-14/+21
| | | | | | | | | | | | | | | | | | Do not clobber flags if they're live. Required in order to perform register allocation on add/sub carry opcodes. LA and AGHI are the same size, so use LA unconditionally. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg/ppc: Implement add/sub carry opcodesRichard Henderson2025-04-284-89/+153
| | | | | | | | | | | | Tested-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg/arm: Implement add/sub carry opcodesRichard Henderson2025-04-283-59/+161
| | | | | | | | | | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg/aarch64: Implement add/sub carry opcodesRichard Henderson2025-04-283-88/+150
| | | | | | | | | | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/tricore: Use tcg_gen_addcio_i32 for gen_addc_CCRichard Henderson2025-04-281-6/+2
| | | | | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/sparc: Use tcg_gen_addcio_tl for gen_op_addcc_intRichard Henderson2025-04-281-2/+1
| | | | | | | | | | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/sh4: Use tcg_gen_addcio_i32 for addcRichard Henderson2025-04-281-8/+2
| | | | | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/s390x: Use tcg_gen_addcio_i64 for op_addc64Richard Henderson2025-04-281-5/+1
| | | | | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/ppc: Use tcg_gen_addcio_tl for ADD and SUBFRichard Henderson2025-04-281-7/+4
| | | | | | | | | | | | | | | | Tested-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/openrisc: Use tcg_gen_addcio_* for ADDCRichard Henderson2025-04-281-2/+1
| | | | | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/microblaze: Use tcg_gen_addcio_i32Richard Henderson2025-04-281-8/+2
| | | | | | | | | | | | | | | | | | Use this in gen_addc and gen_rsubc, both of which need add with carry-in and carry-out. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/hppa: Use tcg_gen_addcio_i64Richard Henderson2025-04-281-11/+6
| | | | | | | | | | | | | | | | | | Use this in do_add, do_sub, and do_ds, all of which need add with carry-in and carry-out. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/arm: Use tcg_gen_addcio_* for ADCSRichard Henderson2025-04-282-20/+5
| | | | | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg: Add tcg_gen_addcio_{i32,i64,tl}Richard Henderson2025-04-283-0/+101
| | | | | | | | | | | | | | | | Create a function for performing an add with carry-in and producing carry out. The carry-out result is boolean. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>