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* | | | Merge tag 'pull-target-arm-20240308' of https://git.linaro.org/people/pmaydel...Peter Maydell2024-03-0831-457/+1963
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| * | | target/arm: Move v7m-related code from cpu32.c into a separate fileThomas Huth2024-03-084-261/+296
| * | | hw/rtc/sun4v-rtc: Relicense to GPLv2-or-laterPeter Maydell2024-03-072-2/+2
| * | | target/arm: Fix 32-bit SMOPARichard Henderson2024-03-074-34/+148
| * | | tests/qtest: Add STM32L4x5 GPIO QTest testcaseInès Varhol2024-03-072-1/+553
| * | | hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoCInès Varhol2024-03-076-18/+63
| * | | hw/gpio: Implement STM32L4x5 GPIOInès Varhol2024-03-077-1/+559
| * | | target/arm: Enable FEAT_ECV for 'max' CPUPeter Maydell2024-03-072-0/+2
| * | | target/arm: Implement FEAT_ECV CNTPOFF_EL2 handlingPeter Maydell2024-03-074-2/+73
| * | | target/arm: Define CNTPCTSS_EL0 and CNTVCTSS_EL0Peter Maydell2024-03-071-0/+43
| * | | target/arm: Implement new FEAT_ECV trap bitsPeter Maydell2024-03-072-5/+51
| * | | target/arm: Don't allow RES0 CNTHCTL_EL2 bits to be writtenPeter Maydell2024-03-071-0/+18
| * | | target/arm: use FIELD macro for CNTHCTL bit definitionsPeter Maydell2024-03-072-7/+29
| * | | target/arm: Timer _EL02 registers UNDEF for E2H == 0Peter Maydell2024-03-071-1/+1
| * | | target/arm: Move some register related defines to internals.hPeter Maydell2024-03-072-128/+128
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* | | Merge tag 'pull-riscv-to-apply-20240308-1' of https://github.com/alistair23/q...Peter Maydell2024-03-0850-347/+1213
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| * | target/riscv: fix ACPI MCFG tableIlya Chugin2024-03-081-2/+2
| * | target/riscv: Fix privilege mode of G-stage translation for debuggingHiroaki Yamamoto2024-03-081-1/+1
| * | hw/intc/riscv_aplic: Fix in_clrip[x] read emulationAnup Patel2024-03-081-2/+15
| * | hw/intc/riscv_aplic: Fix setipnum_le write emulation for APLIC MSI-modeAnup Patel2024-03-081-4/+16
| * | target/riscv: Fix shift count overflowdemin.han2024-03-081-3/+2
| * | trans_rvv.c.inc: remove 'is_store' bool from load/store fnsDaniel Henrique Barboza2024-03-081-29/+29
| * | trans_rvv.c.inc: mark_vs_dirty() before loads and storesDaniel Henrique Barboza2024-03-081-15/+8
| * | target/riscv: mcountinhibit, mcounteren, scounteren, hcounteren is 32-bitVadim Shakirov2024-03-082-12/+12
| * | target/riscv: move ratified/frozen exts to non-experimentalDaniel Henrique Barboza2024-03-081-13/+9
| * | target/riscv/kvm: update KVM exts to Linux 6.8Daniel Henrique Barboza2024-03-081-0/+29
| * | linux-headers: Update to Linux v6.8-rc6Daniel Henrique Barboza2024-03-0823-112/+381
| * | tests: riscv64: Use 'zfa' instead of 'Zfa'Christoph Müllner2024-03-081-1/+1
| * | linux-user/riscv: Add Ztso extension to hwprobeChristoph Müllner2024-03-081-0/+3
| * | RISC-V: Add support for ZtsoPalmer Dabbelt2024-03-086-5/+48
| * | tests/libqos: add riscv/virt machine nodesDaniel Henrique Barboza2024-03-082-0/+138
| * | hw/riscv/virt.c: make aclint compatible with 'qtest' accelDaniel Henrique Barboza2024-03-081-25/+27
| * | hw/riscv/virt.c: add virtio-iommu-pci hotplug supportDaniel Henrique Barboza2024-03-081-1/+35
| * | hw/riscv/virt.c: create '/soc/pci@...' fdt node earlierDaniel Henrique Barboza2024-03-081-1/+8
| * | hw/riscv/virt-acpi-build.c: Add SRAT and SLIT ACPI tablesHaibo Xu2024-03-081-0/+60
| * | target/riscv: Add missing include guard in pmu.hFrank Chang2024-03-081-0/+5
| * | target/riscv: UPDATE xATP write CSRIrina Ryapolova2024-03-081-23/+29
| * | target/riscv: FIX xATP_MODE validationIrina Ryapolova2024-03-081-2/+2
| * | target/riscv: Promote svade to a normal extensionAndrew Jones2024-03-082-7/+8
| * | target/riscv: Gate hardware A/D PTE bit updatingAndrew Jones2024-03-083-15/+22
| * | target/riscv: Reset henvcfg to zeroAndrew Jones2024-03-082-3/+2
| * | target/riscv: add remaining named featuresDaniel Henrique Barboza2024-03-083-7/+43
| * | target/riscv: add riscv,isa to named featuresDaniel Henrique Barboza2024-03-083-16/+23
| * | target/riscv/tcg: set 'mmu' with 'satp' in cpu_set_profile()Daniel Henrique Barboza2024-03-081-0/+1
| * | linux-user/riscv: Sync hwprobe keys with LinuxChristoph Müllner2024-03-081-8/+92
| * | linux-user/riscv: Add Zicboz extensions to hwprobeChristoph Müllner2024-03-081-0/+3
| * | hw: riscv: Allow large kernels to boot by moving the initrd further away in RAMAlexandre Ghiti2024-03-081-6/+6
| * | hw/riscv/virt-acpi-build.c: Generate SPCR tableSia Jee Heng2024-03-081-0/+39
| * | hw/arm/virt-acpi-build.c: Migrate SPCR creation to common locationSia Jee Heng2024-03-084-41/+117
| * | target/riscv: Update $ra with current $pc in trans_cm_jalt()Jason Chien2024-03-081-1/+5
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