summary refs log tree commit diff stats
Commit message (Collapse)AuthorAgeFilesLines
* Merge tag 'pull-tcg-20250117' of https://gitlab.com/rth7680/qemu into stagingStefan Hajnoczi2025-01-2178-2280/+2867
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | tcg: - Add TCGOP_TYPE, TCGOP_FLAGS. - Pass type and flags to tcg_op_supported, tcg_target_op_def. - Split out tcg-target-has.h and unexport from tcg.h. - Reorg constraint processing; constify TCGOpDef. - Make extract, sextract, deposit opcodes mandatory. - Merge ext{8,16,32}{s,u} opcodes into {s}extract. tcg/mips: Expand bswap unconditionally tcg/riscv: Use SRAIW, SRLIW for {s}extract_i64 tcg/riscv: Use BEXTI for single-bit extractions tcg/sparc64: Use SRA, SRL for {s}extract_i64 disas/riscv: Guard dec->cfg dereference for host disassemble util/cpuinfo-riscv: Detect Zbs accel/tcg: Call tcg_tb_insert() for one-insn TBs linux-user: Add missing /proc/cpuinfo fields for sparc # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmeKnzUdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV+Kvgf+LG9UjXlWF9GK923E # TllBL2rLf1OOdtTXWO15VcvGMoWDwB3tVBdhihdvXmnWju+WbfMk6mct5NhzsKn9 # LmuugMIZs+hMROj+bgMK8x47jRIh5N2rDYxcEgmyfIpYb2o9qvyqKecGVRlSJTCE # bmt5UFbvPThBb8upoMfq3F6evuMx0szBP7wrOwSR/VGpmzIr20UTEWo6I1ALp4uj # paFaysYol4em3dIhkiuV9cL7E0EIObaNa7l9RUci/BmTq+JaVxUnW1Y2i0PEwKwG # FJSfYTJk3wBgAVxC2zC2g3ZM7uKuecSXMpiFopTiuyQLp7Q61i9kCNvEq0qY5tdb # DaqR/g== # =cv4O # -----END PGP SIGNATURE----- # gpg: Signature made Fri 17 Jan 2025 13:19:33 EST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20250117' of https://gitlab.com/rth7680/qemu: (68 commits) softfloat: Constify helpers returning float_status field accel/tcg: Call tcg_tb_insert() for one-insn TBs tcg: Document tb_lookup() and tcg_tb_lookup() linux-user: Add missing /proc/cpuinfo fields for sparc tcg/riscv: Use BEXTI for single-bit extractions util/cpuinfo-riscv: Detect Zbs tcg: Remove TCG_TARGET_HAS_deposit_{i32,i64} tcg: Remove TCG_TARGET_HAS_{s}extract_{i32,i64} tcg/tci: Remove assertions for deposit and extract tcg/tci: Provide TCG_TARGET_{s}extract_valid tcg/sparc64: Use SRA, SRL for {s}extract_i64 tcg/s390x: Fold the ext{8,16,32}[us] cases into {s}extract tcg/riscv: Use SRAIW, SRLIW for {s}extract_i64 tcg/riscv64: Fold the ext{8,16,32}[us] cases into {s}extract tcg/ppc: Fold the ext{8,16,32}[us] cases into {s}extract tcg/mips: Fold the ext{8,16,32}[us] cases into {s}extract tcg/loongarch64: Fold the ext{8,16,32}[us] cases into {s}extract tcg/arm: Add full [US]XT[BH] into {s}extract tcg/aarch64: Expand extract with offset 0 with andi tcg/aarch64: Provide TCG_TARGET_{s}extract_valid ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * softfloat: Constify helpers returning float_status fieldPhilippe Mathieu-Daudé2025-01-171-11/+14
| | | | | | | | | | | | | | | | | | These helpers don't alter float_status. Make it const. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250116214359.67295-1-philmd@linaro.org>
| * accel/tcg: Call tcg_tb_insert() for one-insn TBsIlya Leoshkevich2025-01-171-9/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently one-insn TBs created from I/O memory are not added to region_trees. Therefore, when they generate exceptions, they are not handled by cpu_restore_state_from_tb(). For x86 this is not a problem, because x86_restore_state_to_opc() only restores pc and cc, which already have the correct values if the first TB instruction causes an exception. However, on several other architectures, restore_state_to_opc() is not stricly limited to state restoration and affects some exception-related registers, where guests can notice incorrect values, for example: - arm's exception.syndrome; - hppa's unwind_breg; - riscv's excp_uw2; - s390x's int_pgm_ilen. Fix by always calling tcg_tb_insert(). This may increase the size of region_trees, but tcg_region_reset_all() clears it once code_gen_buffer fills up, so it will not grow uncontrollably. Do not call tb_link_page(), which would add such TBs to the QHT, to prevent tb_lookup() from finding them. These TBs are single-use, since subsequent reads from I/O memory may return different values; they are not removed from code_gen_buffer only in order to keep things simple. Co-developed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250116213214.5695-2-iii@linux.ibm.com>
| * tcg: Document tb_lookup() and tcg_tb_lookup()Ilya Leoshkevich2025-01-172-1/+55
| | | | | | | | | | | | | | | | | | | | | | | | These similarly named functions serve different purposes; add docstrings to highlight them. Suggested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250116213214.5695-1-iii@linux.ibm.com>
| * linux-user: Add missing /proc/cpuinfo fields for sparcHelge Deller2025-01-161-1/+19
| | | | | | | | | | | | | | | | | | Add some missing fields which may be parsed by userspace applications. Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <Z39B1wzNNpndmOxZ@p100>
| * tcg/riscv: Use BEXTI for single-bit extractionsRichard Henderson2025-01-162-3/+16
| | | | | | | | | | | | Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250102181601.1421059-3-richard.henderson@linaro.org>
| * util/cpuinfo-riscv: Detect ZbsRichard Henderson2025-01-162-4/+19
| | | | | | | | | | | | | | Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250102181601.1421059-2-richard.henderson@linaro.org>
| * tcg: Remove TCG_TARGET_HAS_deposit_{i32,i64}Richard Henderson2025-01-1615-65/+35
| | | | | | | | | | | | | | | | | | Make deposit "unconditional" in the sense that the opcode is always present. Rely instead on TCG_TARGET_deposit_valid, now always defined. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg: Remove TCG_TARGET_HAS_{s}extract_{i32,i64}Richard Henderson2025-01-1614-70/+8
| | | | | | | | | | | | | | | | | | Make extract and sextract "unconditional" in the sense that the opcodes are always present. Rely instead on TCG_TARGET_HAS_{s}extract_valid, now always defined. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg/tci: Remove assertions for deposit and extractRichard Henderson2025-01-161-18/+2
| | | | | | | | | | | | | | We already have these assertions during opcode creation. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg/tci: Provide TCG_TARGET_{s}extract_validRichard Henderson2025-01-161-0/+3
| | | | | | | | | | | | | | Trivially mirrors TCG_TARGET_HAS_{s}extract_*. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg/sparc64: Use SRA, SRL for {s}extract_i64Richard Henderson2025-01-162-4/+20
| | | | | | | | | | | | | | Extracts which abut bit 32 may use 32-bit shifts. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg/s390x: Fold the ext{8,16,32}[us] cases into {s}extractRichard Henderson2025-01-162-2/+57
| | | | | | | | | | | | | | | | Accept byte and word extensions with the extract opcodes. This is preparatory to removing the specialized extracts. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg/riscv: Use SRAIW, SRLIW for {s}extract_i64Richard Henderson2025-01-162-21/+19
| | | | | | | | | | | | | | Extracts which abut bit 32 may use 32-bit shifts. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg/riscv64: Fold the ext{8,16,32}[us] cases into {s}extractRichard Henderson2025-01-162-4/+69
| | | | | | | | | | | | | | | | Accept byte and word extensions with the extract opcodes. This is preparatory to removing the specialized extracts. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg/ppc: Fold the ext{8,16,32}[us] cases into {s}extractRichard Henderson2025-01-162-2/+44
| | | | | | | | | | | | | | | | Accept byte and word extensions with the extract opcodes. This is preparatory to removing the specialized extracts. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg/mips: Fold the ext{8,16,32}[us] cases into {s}extractRichard Henderson2025-01-162-7/+52
| | | | | | | | | | | | | | | | Accept AND, ext32u, ext32s extensions with the extract opcodes. This is preparatory to removing the specialized extracts. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg/loongarch64: Fold the ext{8,16,32}[us] cases into {s}extractRichard Henderson2025-01-162-4/+45
| | | | | | | | | | | | | | | | Accept byte and word extensions with the extract opcodes. This is preparatory to removing the specialized extracts. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg/arm: Add full [US]XT[BH] into {s}extractRichard Henderson2025-01-162-8/+67
| | | | | | | | | | | | | | | | | | The armv6 uxt and sxt opcodes have a 2-bit rotate field which supports extractions from ofs = {0,8,16,24}. Special case ofs = 0, len <= 8 as AND. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg/aarch64: Expand extract with offset 0 with andiRichard Henderson2025-01-161-1/+6
| | | | | | | | | | | | | | | | We're about to change canonicalization of masks as extract instead of and. Retain the andi expansion here. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg/aarch64: Provide TCG_TARGET_{s}extract_validRichard Henderson2025-01-161-0/+3
| | | | | | | | | | | | | | Trivially mirrors TCG_TARGET_HAS_{s}extract_*. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg/i386: Fold the ext{8,16,32}[us] cases into {s}extractRichard Henderson2025-01-165-36/+107
| | | | | | | | | | | | | | | | Accept byte and word extensions with the extract opcodes. This is preparatory to removing the specialized extracts. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg/i386: Handle all 8-bit extensions for i686Richard Henderson2025-01-161-4/+19
| | | | | | | | | | | | | | | | | | When we generalize {s}extract_i32, we'll lose the specific register constraints on ext8u and ext8s. It's just as easy to emit a couple of insns instead. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg/mips: Expand bswap unconditionallyRichard Henderson2025-01-161-4/+4
| | | | | | | | | | | | | | | | We always provide bswap subroutines, whether they are optimized using mips32r2 when available or not. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg: Replace IMPLVEC with TCG_OPF_VECTORRichard Henderson2025-01-166-79/+76
| | | | | | | | | | | | | | This is now a direct replacement. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg: Drop implementation checks from tcg-opc.hRichard Henderson2025-01-161-171/+147
| | | | | | | | | | | | | | | | | | Now that we use a functional interface to query whether the opcode is supported, we can drop the TCG_OPF_NOT_PRESENT bit mapping from TCG_TARGET_HAS_foo in tcg-opc.h Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg: Remove TCG_OPF_64BITRichard Henderson2025-01-162-13/+11
| | | | | | | | | | | | | | This flag is no longer used. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg: Add TCGType argument to tcg_out_opRichard Henderson2025-01-1611-24/+19
| | | | | | | | | | | | | | | | | | | | Pass TCGOp.type to the output function. For aarch64 and tci, use this instead of testing TCG_OPF_64BIT. For s390x, use this instead of testing INDEX_op_deposit_i64. For i386, use this to initialize rexw. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg: Pass type and flags to tcg_target_op_defRichard Henderson2025-01-1611-12/+22
| | | | | | | | | | | | | | Allow the backend to make constraint choices based on more parameters. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg: Add TCG_OPF_NOT_PRESENT to opcodes without inputs or outputsRichard Henderson2025-01-162-7/+4
| | | | | | | | | | | | | | | | | | | | The br, mb, goto_tb and exit_tb opcodes do not have register operands, only constants, flags, or labels. Remove the special case in opcode_args_ct by including TCG_OPF_NOT_PRESENT in the flags for these opcodes. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg: Validate op supported in opcode_args_ctRichard Henderson2025-01-161-0/+4
| | | | | | | | | | | | | | | | | | We should have checked that the op is supported before emitting it. The backend cannot be expected to have a constraint set for unsupported ops. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg: Constify tcg_op_defsRichard Henderson2025-01-163-3/+3
| | | | | | | | | | | | | | | | Now that we're no longer assigning to TCGOpDef.args_ct, we can make the array constant. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg: Remove args_ct from TCGOpDefRichard Henderson2025-01-163-43/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | Introduce a new function, opcode_args_ct, to look up the argument set for an opcode. We lose the ability to assert the correctness of the map from TCGOpcode to constraint sets at startup, but we can still validate at runtime upon lookup. Rename process_op_defs to process_constraint_sets, as it now does nothing to TCGOpDef. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg: Reorg process_op_defsRichard Henderson2025-01-162-147/+140
| | | | | | | | | | | | | | | | | | Process each TCGConstraintSetIndex first. Allocate TCGArgConstraint arrays based on those. Only afterward process the TCGOpcodes and share those TCGArgConstraint arrays. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg: Change have_vec to has_type in tcg_op_supportedRichard Henderson2025-01-161-23/+43
| | | | | | | | | | | | | | | | Test each vector type, not just lumping them all together. Add tests for I32 (always true) and I64 (64-bit hosts). Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg: Use C_NotImplemented in tcg_target_op_defRichard Henderson2025-01-1611-14/+16
| | | | | | | | | | | | | | | | | | Return C_NotImplemented instead of asserting for opcodes not implemented by the backend. For now, the assertion moves to process_op_defs. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg: Split out tcg-target-mo.hRichard Henderson2025-01-1622-32/+136
| | | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * tcg: Only include 'tcg-has.h' when necessaryRichard Henderson2025-01-169-4/+8
| | | | | | | | | | | | | | | | | | TCG_TARGET_HAS_* definitions don't need to be exposed by "tcg/tcg.h". Only include 'tcg-has.h' when necessary. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250108215156.8731-15-philmd@linaro.org>
| * tcg: Include 'tcg-target-has.h' once in 'tcg-has.h'Richard Henderson2025-01-1611-20/+2
| | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250108215156.8731-14-philmd@linaro.org>
| * tcg/tci: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h'Richard Henderson2025-01-162-74/+84
| | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250108215156.8731-13-philmd@linaro.org>
| * tcg/sparc64: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h'Richard Henderson2025-01-162-76/+88
| | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250108215156.8731-12-philmd@linaro.org>
| * tcg/s390x: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h'Richard Henderson2025-01-162-113/+125
| | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250108215156.8731-11-philmd@linaro.org>
| * tcg/riscv: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h'Richard Henderson2025-01-162-101/+113
| | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250108215156.8731-10-philmd@linaro.org>
| * tcg/ppc: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h'Richard Henderson2025-01-162-113/+125
| | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250108215156.8731-9-philmd@linaro.org>
| * tcg/mips: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h'Richard Henderson2025-01-162-111/+123
| | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250108215156.8731-8-philmd@linaro.org>
| * tcg/loongarch64: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h'Richard Henderson2025-01-162-101/+114
| | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250108215156.8731-7-philmd@linaro.org>
| * tcg/i386: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h'Richard Henderson2025-01-162-128/+140
| | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250108215156.8731-6-philmd@linaro.org>
| * tcg/arm: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h'Richard Henderson2025-01-162-73/+86
| | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250108215156.8731-5-philmd@linaro.org>
| * tcg/aarch64: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h'Richard Henderson2025-01-162-108/+120
| | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250108215156.8731-4-philmd@linaro.org>
| * tcg: Extract default TCG_TARGET_HAS_foo definitions to 'tcg-has.h'Richard Henderson2025-01-162-104/+116
| | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250108215156.8731-3-philmd@linaro.org>