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* block/reqlist: add reqlist_wait_all()Vladimir Sementsov-Ogievskiy2022-03-072-0/+16
| | | | | | | | | | | Add function to wait for all intersecting requests. To be used in the further commit. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Nikita Lapshin <nikita.lapshin@virtuozzo.com> Reviewed-by: Hanna Reitz <hreitz@redhat.com> Message-Id: <20220303194349.2304213-10-vsementsov@virtuozzo.com> Signed-off-by: Hanna Reitz <hreitz@redhat.com>
* block/dirty-bitmap: introduce bdrv_dirty_bitmap_status()Vladimir Sementsov-Ogievskiy2022-03-074-0/+53
| | | | | | | | | | Add a convenient function similar with bdrv_block_status() to get status of dirty bitmap. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Hanna Reitz <hreitz@redhat.com> Message-Id: <20220303194349.2304213-9-vsementsov@virtuozzo.com> Signed-off-by: Hanna Reitz <hreitz@redhat.com>
* block/reqlist: reqlist_find_conflict(): use ranges_overlap()Vladimir Sementsov-Ogievskiy2022-03-071-1/+2
| | | | | | | | | Let's reuse convenient helper. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Hanna Reitz <hreitz@redhat.com> Message-Id: <20220303194349.2304213-8-vsementsov@virtuozzo.com> Signed-off-by: Hanna Reitz <hreitz@redhat.com>
* block: intoduce reqlistVladimir Sementsov-Ogievskiy2022-03-075-80/+184
| | | | | | | | | | | | Split intersecting-requests functionality out of block-copy to be reused in copy-before-write filter. Note: while being here, fix tiny typo in MAINTAINERS. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Hanna Reitz <hreitz@redhat.com> Message-Id: <20220303194349.2304213-7-vsementsov@virtuozzo.com> Signed-off-by: Hanna Reitz <hreitz@redhat.com>
* block/block-copy: add block_copy_reset()Vladimir Sementsov-Ogievskiy2022-03-072-8/+14
| | | | | | | | | | Split block_copy_reset() out of block_copy_reset_unallocated() to be used separately later. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Hanna Reitz <hreitz@redhat.com> Message-Id: <20220303194349.2304213-6-vsementsov@virtuozzo.com> Signed-off-by: Hanna Reitz <hreitz@redhat.com>
* block/copy-before-write: add bitmap open parameterVladimir Sementsov-Ogievskiy2022-03-072-2/+59
| | | | | | | | | This brings "incremental" mode to copy-before-write filter: user can specify bitmap so that filter will copy only "dirty" areas. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-Id: <20220303194349.2304213-5-vsementsov@virtuozzo.com> Signed-off-by: Hanna Reitz <hreitz@redhat.com>
* block/block-copy: block_copy_state_new(): add bitmap parameterVladimir Sementsov-Ogievskiy2022-03-073-2/+15
| | | | | | | | | | This will be used in the following commit to bring "incremental" mode to copy-before-write filter. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Hanna Reitz <hreitz@redhat.com> Message-Id: <20220303194349.2304213-4-vsementsov@virtuozzo.com> Signed-off-by: Hanna Reitz <hreitz@redhat.com>
* block/dirty-bitmap: bdrv_merge_dirty_bitmap(): add return valueVladimir Sementsov-Ogievskiy2022-03-073-7/+9
| | | | | | | | | | That simplifies handling failure in existing code and in further new usage of bdrv_merge_dirty_bitmap(). Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Hanna Reitz <hreitz@redhat.com> Message-Id: <20220303194349.2304213-3-vsementsov@virtuozzo.com> Signed-off-by: Hanna Reitz <hreitz@redhat.com>
* block/block-copy: move copy_bitmap initialization to block_copy_state_new()Vladimir Sementsov-Ogievskiy2022-03-072-4/+1
| | | | | | | | | | | | | | | | We are going to complicate bitmap initialization in the further commit. And in future, backup job will be able to work without filter (when source is immutable), so we'll need same bitmap initialization in copy-before-write filter and in backup job. So, it's reasonable to do it in block-copy. Note that for now cbw_open() is the only caller of block_copy_state_new(). Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Hanna Reitz <hreitz@redhat.com> Message-Id: <20220303194349.2304213-2-vsementsov@virtuozzo.com> Signed-off-by: Hanna Reitz <hreitz@redhat.com>
* iotests: Write test output to TEST_DIRHanna Reitz2022-03-074-16/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Drop the use of OUTPUT_DIR (test/qemu-iotests under the build directory), and instead write test output files (.out.bad, .notrun, and .casenotrun) to TEST_DIR. With this, the same test can be run concurrently without the separate instances interfering, because they will need separate TEST_DIRs anyway. Running the same test separately is useful when running the iotests with various format/protocol combinations in parallel, or when you just want to aggressively exercise a single test (e.g. when it fails only sporadically). Putting this output into TEST_DIR means that it will stick around for inspection after the test run is done (though running the same test in the same TEST_DIR will overwrite it, just as it used to be); but given that TEST_DIR is a scratch directory, it should be clear that users can delete all of its content at any point. (And if TEST_DIR is on tmpfs, it will just disappear on shutdown.) Contrarily, alternative approaches that would put these output files into OUTPUT_DIR with some prefix to differentiate between separate test runs might easily lead to cluttering OUTPUT_DIR. (This change means OUTPUT_DIR is no longer written to by the iotests, so we can drop its usage altogether.) Signed-off-by: Hanna Reitz <hreitz@redhat.com> Message-Id: <20220221172909.762858-1-hreitz@redhat.com> [hreitz: Simplified `Path(os.path.join(x, y))` to `Path(x, y)`, as suggested by Vladimir; and rebased on 9086c7639822b6 ("tests/qemu-iotests: Rework the checks and spots using GNU sed")] Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
* tests/qemu-iotests/testrunner: Quote "case not run" lines in TAP modeThomas Huth2022-03-071-1/+4
| | | | | | | | | | | | | | | | | | | In TAP mode, the stdout is reserved for the TAP protocol, so we have to make sure to mark other lines with a comment '#' character at the beginning to avoid that the TAP parser at the other end gets confused. To test this condition, run "configure" for example with: --block-drv-rw-whitelist=copy-before-write,qcow2,raw,file,host_device,blkdebug,null-co,copy-on-read so that iotest 041 will report that some tests are not run due to the missing "quorum" driver. Without this change, "make check-block" fails since the meson tap parser gets confused by these messages. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220223124353.3273898-1-thuth@redhat.com> Signed-off-by: Hanna Reitz <hreitz@redhat.com>
* tests/qemu-iotests/040: Skip TestCommitWithFilters without 'throttle'Thomas Huth2022-03-071-0/+1
| | | | | | | | | | | | | iotest 040 already has some checks for the availability of the 'throttle' driver, but some new code has been added in the course of time that depends on 'throttle' but does not check for its availability. Add a check to the TestCommitWithFilters class so that this iotest now also passes again if 'throttle' has not been enabled in the QEMU binaries. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220223123127.3206042-1-thuth@redhat.com> Signed-off-by: Hanna Reitz <hreitz@redhat.com>
* block: fix preallocate filter: don't do unaligned preallocate requestsVladimir Sementsov-Ogievskiy2022-03-073-4/+18
| | | | | | | | | | | | | | | | | | | | | | There is a bug in handling BDRV_REQ_NO_WAIT flag: we still may wait in wait_serialising_requests() if request is unaligned. And this is possible for the only user of this flag (preallocate filter) if underlying file is unaligned to its request_alignment on start. So, we have to fix preallocate filter to do only aligned preallocate requests. Next, we should fix generic block/io.c somehow. Keeping in mind that preallocate is the only user of BDRV_REQ_NO_WAIT and that we have to fix its behavior now, it seems more safe to just assert that we never use BDRV_REQ_NO_WAIT with unaligned requests and add corresponding comment. Let's do so. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Denis V. Lunev <den@openvz.org> Message-Id: <20220215121609.38570-1-vsementsov@virtuozzo.com> [hreitz: Rebased on block GS/IO split] Signed-off-by: Hanna Reitz <hreitz@redhat.com>
* block/curl.c: Check error return from curl_easy_setopt()Peter Maydell2022-03-071-33/+57
| | | | | | | | | | | | | | | | | Coverity points out that we aren't checking the return value from curl_easy_setopt() for any of the calls to it we make in block/curl.c. Some of these options are documented as always succeeding (e.g. CURLOPT_VERBOSE) but others have documented failure cases (e.g. CURLOPT_URL). For consistency we check every call, even the ones that theoretically cannot fail. Fixes: Coverity CID 1459336, 1459482, 1460331 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220222152341.850419-3-peter.maydell@linaro.org> Reviewed-by: Hanna Reitz <hreitz@redhat.com> Signed-off-by: Hanna Reitz <hreitz@redhat.com>
* block/curl.c: Set error message string if curl_init_state() failsPeter Maydell2022-03-071-0/+2
| | | | | | | | | | | | | | | | | | In curl_open(), the 'out' label assumes that the state->errmsg string has been set (either by curl_easy_perform() or by manually copying a string into it); however if curl_init_state() fails we will jump to that label without setting the string. Add the missing error string setup. (We can't be specific about the cause of failure: the documentation of curl_easy_init() just says "If this function returns NULL, something went wrong".) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220222152341.850419-2-peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Hanna Reitz <hreitz@redhat.com> Signed-off-by: Hanna Reitz <hreitz@redhat.com>
* ide: Increment BB in-flight counter for TRIM BHHanna Reitz2022-03-071-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When we still have an AIOCB registered for DMA operations, we try to settle the respective operation by draining the BlockBackend associated with the IDE device. However, this assumes that every DMA operation is associated with an increment of the BlockBackend’s in-flight counter (e.g. through some ongoing I/O operation), so that draining the BB until its in-flight counter reaches 0 will settle all DMA operations. That is not the case: For TRIM, the guest can issue a zero-length operation that will not result in any I/O operation forwarded to the BlockBackend, and also not increment the in-flight counter in any other way. In such a case, blk_drain() will be a no-op if no other operations are in flight. It is clear that if blk_drain() is a no-op, the value of s->bus->dma->aiocb will not change between checking it in the `if` condition and asserting that it is NULL after blk_drain(). The particular problem is that ide_issue_trim() creates a BH (ide_trim_bh_cb()) to settle the TRIM request: iocb->common.cb() is ide_dma_cb(), which will either create a new request, or find the transfer to be done and call ide_set_inactive(), which clears s->bus->dma->aiocb. Therefore, the blk_drain() must wait for ide_trim_bh_cb() to run, which currently it will not always do. To fix this issue, we increment the BlockBackend's in-flight counter when the TRIM operation begins (in ide_issue_trim(), when the ide_trim_bh_cb() BH is created) and decrement it when ide_trim_bh_cb() is done. Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=2029980 Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Hanna Reitz <hreitz@redhat.com> Message-Id: <20220120142259.120189-1-hreitz@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: John Snow <jsnow@redhat.com> Tested-by: John Snow <jsnow@redhat.com>
* Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220305' into ↵Peter Maydell2022-03-059-196/+190
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging ppc-7.0 queue : * Clang fixes * Vector/VSX instruction batch fixes # gpg: Signature made Sat 05 Mar 2022 08:18:06 GMT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * remotes/legoater/tags/pull-ppc-20220305: target/ppc: Add missing helper_reset_fpstatus to helper_XVCVSPBF16 target/ppc: Add missing helper_reset_fpstatus to VSX_MAX_MINC target/ppc: split XXGENPCV macros for readability target/ppc: use andc in vrlqmi target/ppc: use extract/extract2 to create vrlqnm mask target/ppc: use ext32u and deposit in do_vx_vmulhw_i64 target/ppc: Fix vmul[eo]* instructions marked 2.07 tests/tcg/ppc64le: Use Altivec register names in clobber list tests/tcg/ppc64le: emit bcdsub with .long when needed tests/tcg/ppc64le: drop __int128 usage in bcdsub target/ppc: change xs[n]madd[am]sp to use float64r32_muladd tests/tcg/ppc64le: use inline asm instead of __builtin_mtfsf Use long endian options for ppc64 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/ppc: Add missing helper_reset_fpstatus to helper_XVCVSPBF16Víctor Colombo2022-03-051-0/+2
| | | | | | | | | | | | | | | | | | Fixes: 3909ff1fac ("target/ppc: Implement xvcvbf16spn and xvcvspbf16 instructions") Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220304175156.2012315-8-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * target/ppc: Add missing helper_reset_fpstatus to VSX_MAX_MINCVíctor Colombo2022-03-051-0/+2
| | | | | | | | | | | | | | | | | | Fixes: da499405aa ("target/ppc: Refactor VSX_MAX_MINC helper") Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220304175156.2012315-7-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * target/ppc: split XXGENPCV macros for readabilityMatheus Ferst2022-03-052-42/+57
| | | | | | | | | | | | | | | | Fixes: b090f4f1e3c9 ("target/ppc: Implement xxgenpcv[bhwd]m instruction") Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220304175156.2012315-6-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * target/ppc: use andc in vrlqmiMatheus Ferst2022-03-051-4/+2
| | | | | | | | | | | | | | | | Fixes: 7e5947df6e94 ("target/ppc: implement vrlqmi") Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220304175156.2012315-5-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * target/ppc: use extract/extract2 to create vrlqnm maskMatheus Ferst2022-03-051-7/+3
| | | | | | | | | | | | | | | | Fixes: 4e272668406b ("target/ppc: implement vrlqnm") Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220304175156.2012315-4-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * target/ppc: use ext32u and deposit in do_vx_vmulhw_i64Matheus Ferst2022-03-051-7/+3
| | | | | | | | | | | | | | | | Fixes: 29e9dfcf755e ("target/ppc: vmulh* instructions without helpers") Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220304175156.2012315-3-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * target/ppc: Fix vmul[eo]* instructions marked 2.07Lucas Mateus Castro (alqotel)2022-03-051-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Some ISA v2.03 Vector Multiply instructions marked to be ISA v2.07 only. This patch fixes it. Fixes: 80eca687c851 ("target/ppc: moved vector even and odd multiplication to decodetree") Reported-by: Howard Spoelstra <hsp.cat7@gmail.com> Suggested-by: Fabiano Rosas <farosas@linux.ibm.com> Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220304175156.2012315-2-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * tests/tcg/ppc64le: Use Altivec register names in clobber listMatheus Ferst2022-03-051-8/+8
| | | | | | | | | | | | | | | | | | | | | | LLVM/Clang doesn't know the VSX registers when compiling with -mabi=elfv1. Use only registers >= 32 and list them with their Altivec name. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220304165417.1981159-6-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * tests/tcg/ppc64le: emit bcdsub with .long when neededMatheus Ferst2022-03-051-31/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on GCC docs[1], we use the '-mpower8-vector' flag at config-time to detect the toolchain support to the bcdsub instruction. LLVM/Clang supports this flag since version 3.6[2], but the instruction and related builtins were only added in LLVM 14[3]. In the absence of other means to detect this support at config-time, we resort to __has_builtin to identify the presence of __builtin_bcdsub at compile-time. If the builtin is not available, the instruction is emitted with a ".long". [1] https://gcc.gnu.org/onlinedocs/gcc-8.3.0/gcc/PowerPC-AltiVec_002fVSX-Built-in-Functions.html [2] https://github.com/llvm/llvm-project/commit/59eb767e11d4ffefb5f55409524e5c8416b2b0db [3] https://github.com/llvm/llvm-project/commit/c933c2eb334660c131f4afc9d194fafb0cec0423 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220304165417.1981159-5-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * tests/tcg/ppc64le: drop __int128 usage in bcdsubMatheus Ferst2022-03-051-68/+61
| | | | | | | | | | | | | | | | | | | | | | | | Using __int128 with inline asm constraints like "v" generates incorrect code when compiling with LLVM/Clang (e.g., only one doubleword of the VSR is loaded). Instead, use a GPR pair to pass the 128-bits value and load the VSR with mtvsrd/xxmrghd. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220304165417.1981159-4-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * target/ppc: change xs[n]madd[am]sp to use float64r32_muladdMatheus Ferst2022-03-051-38/+20
| | | | | | | | | | | | | | | | | | | | | | | | Change VSX Scalar Multiply-Add/Subtract Type-A/M Single Precision helpers to use float64r32_muladd. This method should correctly handle all rounding modes, so the workaround for float_round_nearest_even can be dropped. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220304165417.1981159-3-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * tests/tcg/ppc64le: use inline asm instead of __builtin_mtfsfMatheus Ferst2022-03-051-10/+9
| | | | | | | | | | | | | | | | | | | | LLVM/Clang does not support __builtin_mtfsf. Acked-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220304165417.1981159-2-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * Use long endian options for ppc64Miroslav Rezanina2022-03-052-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | GCC options pairs -mlittle/-mlittle-endian and -mbig/-mbig-endian are equivalent on ppc64 architecture. However, Clang supports only long version of the options. Use longer form in configure to properly support both GCC and Clang compiler. In addition, fix this issue in tcg test configure. Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Message-Id: <20220131091714.4825-1-mrezanin@redhat.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* | Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20220304' ↵Peter Maydell2022-03-0517-93/+440
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging Reorder do_constant_folding_cond test to satisfy valgrind. Fix value of MAX_OPC_PARAM_IARGS. Add opcodes for vector nand, nor, eqv. Support vector nand, nor, eqv on PPC and S390X hosts. Support AVX512VL, AVX512BW, AVX512DQ, and AVX512VBMI2. # gpg: Signature made Fri 04 Mar 2022 18:59:08 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth-gitlab/tags/pull-tcg-20220304: (21 commits) tcg/i386: Implement bitsel for avx512 tcg/i386: Implement more logical operations for avx512 tcg/i386: Implement avx512 multiply tcg/i386: Implement avx512 min/max/abs tcg/i386: Expand scalar rotate with avx512 insns tcg/i386: Remove rotls_vec from tcg_target_op_def tcg/i386: Expand vector word rotate as avx512vbmi2 shift-double tcg/i386: Support avx512vbmi2 vector shift-double instructions tcg/i386: Implement avx512 variable rotate tcg/i386: Implement avx512 immediate rotate tcg/i386: Implement avx512 immediate sari shift tcg/i386: Implement avx512 scalar shift tcg/i386: Implement avx512 variable shifts tcg/i386: Use tcg_can_emit_vec_op in expand_vec_cmp_noinv tcg/i386: Add tcg_out_evex_opc tcg/i386: Detect AVX512 tcg/s390x: Implement vector NAND, NOR, EQV tcg/ppc: Implement vector NAND, NOR, EQV tcg: Add opcodes for vector nand, nor, eqv tcg: Set MAX_OPC_PARAM_IARGS to 7 ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | tcg/i386: Implement bitsel for avx512Richard Henderson2022-03-042-2/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The general ternary logic operation can implement BITSEL. Funnel the 4-operand operation into three variants of the 3-operand instruction, depending on input operand overlap. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/i386: Implement more logical operations for avx512Richard Henderson2022-03-042-5/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | AVX512VL has a general ternary logic operation, VPTERNLOGQ, which can implement NOT, ORC, NAND, NOR, EQV. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/i386: Implement avx512 multiplyRichard Henderson2022-03-041-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | AVX512DQ has VPMULLQ. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/i386: Implement avx512 min/max/absRichard Henderson2022-03-041-7/+11
| | | | | | | | | | | | | | | | | | | | | | | | AVX512VL has VPABSQ, VPMAXSQ, VPMAXUQ, VPMINSQ, VPMINUQ. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/i386: Expand scalar rotate with avx512 insnsRichard Henderson2022-03-041-20/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | Expand 32-bit and 64-bit scalar rotate with VPRO[LR]V; expand 16-bit scalar rotate with VPSHLDV. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/i386: Remove rotls_vec from tcg_target_op_defRichard Henderson2022-03-041-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | There is no such instruction on x86, so we should not be pretending it has arguments. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/i386: Expand vector word rotate as avx512vbmi2 shift-doubleRichard Henderson2022-03-041-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | While there are no specific 16-bit rotate instructions, there are double-word shifts, which can perform the same operation. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/i386: Support avx512vbmi2 vector shift-double instructionsRichard Henderson2022-03-043-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | We will use VPSHLD, VPSHLDV and VPSHRDV for 16-bit rotates. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/i386: Implement avx512 variable rotateRichard Henderson2022-03-042-2/+25
| | | | | | | | | | | | | | | | | | | | | | | | AVX512VL has VPROLVD and VPRORVQ. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/i386: Implement avx512 immediate rotateRichard Henderson2022-03-042-3/+14
| | | | | | | | | | | | | | | | | | | | | AVX512VL has VPROLD and VPROLQ, layered onto the same opcode as PSHIFTD, but requires EVEX encoding and W1. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/i386: Implement avx512 immediate sari shiftRichard Henderson2022-03-041-9/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | AVX512 has VPSRAQ with immediate operand, in the same form as with AVX, but requires EVEX encoding and W1. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/i386: Implement avx512 scalar shiftRichard Henderson2022-03-041-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | AVX512VL has VPSRAQ. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/i386: Implement avx512 variable shiftsRichard Henderson2022-03-041-8/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | AVX512VL has VPSRAVQ, and AVX512BW has VPSLLVW, VPSRAVW, VPSRLVW. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/i386: Use tcg_can_emit_vec_op in expand_vec_cmp_noinvRichard Henderson2022-03-041-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | The condition for UMIN/UMAX availability is about to change; use the canonical version. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/i386: Add tcg_out_evex_opcRichard Henderson2022-03-041-1/+50
| | | | | | | | | | | | | | | | | | | | | | | | The evex encoding is added here, for use in a subsequent patch. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/i386: Detect AVX512Richard Henderson2022-03-043-5/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | There are some operation sizes in some subsets of AVX512 that are missing from previous iterations of AVX. Detect them. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/s390x: Implement vector NAND, NOR, EQVRichard Henderson2022-03-042-3/+20
| | | | | | | | | | | | | | | | | | | | | Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/ppc: Implement vector NAND, NOR, EQVRichard Henderson2022-03-042-3/+18
| | | | | | | | | | | | | | | | | | | | | Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg: Add opcodes for vector nand, nor, eqvRichard Henderson2022-03-0410-15/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We've had placeholders for these opcodes for a while, and should have support on ppc, s390x and avx512 hosts. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>