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| * target/riscv: Set VS* bits to one in mideleg when H-Ext is enabledRajnesh Kanwal2023-11-071-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | With H-Ext supported, VS bits are all hardwired to one in MIDELEG denoting always delegated interrupts. This is being done in rmw_mideleg but given mideleg is used in other places when routing interrupts this change initializes it in riscv_cpu_realize to be on the safe side. Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20231016111736.28721-4-rkanwal@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST.Rajnesh Kanwal2023-11-071-6/+4
| | | | | | | | | | | | | | | | | | | | | | RISCV_EXCP_SEMIHOST is set to 0x10, which can be a local interrupt id as well. This change moves RISCV_EXCP_SEMIHOST to switch case so that async flag check is performed before invoking semihosting logic. Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20231016111736.28721-3-rkanwal@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: Without H-mode mask all HS mode inturrupts in mie.Rajnesh Kanwal2023-11-071-1/+1
| | | | | | | | | | | | | | Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20231016111736.28721-2-rkanwal@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: rename ext_icboz to ext_zicbozDaniel Henrique Barboza2023-11-075-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | Add a leading 'z' to improve grepping. When one wants to search for uses of zicboz they're more likely to do 'grep -i zicboz' than 'grep -i icboz'. Suggested-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20231012164604.398496-5-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: rename ext_icbom to ext_zicbomDaniel Henrique Barboza2023-11-075-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | Add a leading 'z' to improve grepping. When one wants to search for uses of zicbom they're more likely to do 'grep -i zicbom' than 'grep -i icbom'. Suggested-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20231012164604.398496-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: rename ext_icsr to ext_zicsrDaniel Henrique Barboza2023-11-076-22/+22
| | | | | | | | | | | | | | | | | | | | | | | | Add a leading 'z' to improve grepping. When one wants to search for uses of zicsr they're more likely to do 'grep -i zicsr' than 'grep -i icsr'. Suggested-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20231012164604.398496-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * target/riscv: rename ext_ifencei to ext_zifenceiDaniel Henrique Barboza2023-11-074-17/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | Add a leading 'z' to improve grepping. When one wants to search for uses of zifencei they're more likely to do 'grep -i zifencei' than 'grep -i ifencei'. Suggested-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20231012164604.398496-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* | Merge tag 'pull-tcg-20231106' of https://gitlab.com/rth7680/qemu into stagingStefan Hajnoczi2023-11-0736-1304/+1529
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | util: Add cpuinfo for loongarch64 tcg/loongarch64: Use cpuinfo.h tcg/loongarch64: Improve register allocation for INDEX_op_qemu_ld_a*_i128 host/include/loongarch64: Add atomic16 load and store tcg: Move expanders out of line tcg/mips: Always implement movcond tcg/mips: Implement neg opcodes tcg/loongarch64: Implement neg opcodes tcg: Make movcond and neg required opcodes tcg: Optimize env memory operations tcg: Canonicalize sub of immediate to add tcg/sparc64: Implement tcg_out_extrl_i64_i32 # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmVJpT0dHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV9i7QgAtjxUB3y/caCPp0Me # 3cXYtpL1vNxx+cTESGMlmIRSji+cEOxYSpnY0itxXcKpcwP8Au8eoTe85NxyIllg # 2R/SA2jlmrmiipI+bwb0UBCy+BzUfMgmegA88K2W22J0fetwIy19PN9ORmYdLiYE # /pWNFOSPzhYEJgOw7V2MwciUv3llolMOfxU7VT4oVaCknZRsyaGUwl4uTT4GdPuK # p29O9nziyKDmNTqJ9SKKll5bzwCMAgkn2lUcMGf+rpl7ZxjgvysUYrGXKmOnj4Uu # eCU2d3ZHoSspcYEjbFASlyPd7z5apGI8Iq2K35FUhURFPv06Su/bIGOOD4ujP2Qp # vc/bFQ== # =Mvaf # -----END PGP SIGNATURE----- # gpg: Signature made Tue 07 Nov 2023 10:47:25 HKT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20231106' of https://gitlab.com/rth7680/qemu: (35 commits) tcg/sparc64: Implement tcg_out_extrl_i64_i32 tcg/optimize: Canonicalize sub2 with constants to add2 tcg/optimize: Canonicalize subi to addi during optimization tcg: Canonicalize subi to addi during opcode generation tcg/optimize: Split out arg_new_constant tcg: Eliminate duplicate env store operations tcg/optimize: Optimize env memory operations tcg/optimize: Split out cmp_better_copy tcg/optimize: Pipe OptContext into reset_ts tcg: Don't free vector results tcg: Remove TCG_TARGET_HAS_neg_{i32,i64} tcg/loongarch64: Implement neg opcodes tcg/mips: Implement neg opcodes tcg: Remove TCG_TARGET_HAS_movcond_{i32,i64} tcg/mips: Always implement movcond tcg/mips: Split out tcg_out_setcond_int tcg: Move tcg_temp_free_* out of line tcg: Move tcg_temp_new_*, tcg_global_mem_new_* out of line tcg: Move tcg_constant_* out of line tcg: Unexport tcg_gen_op*_{i32,i64} ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * | tcg/sparc64: Implement tcg_out_extrl_i64_i32Richard Henderson2023-11-061-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Build fix for missing symbol. Cc: qemu-stable@nongnu.org Fixes: dad2f2f5af ("tcg/sparc64: Disable TCG_TARGET_HAS_extr_i64_i32") Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/optimize: Canonicalize sub2 with constants to add2Richard Henderson2023-11-061-2/+19
| | | | | | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20231026013945.1152174-4-richard.henderson@linaro.org>
| * | tcg/optimize: Canonicalize subi to addi during optimizationRichard Henderson2023-11-061-1/+13
| | | | | | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20231026013945.1152174-3-richard.henderson@linaro.org>
| * | tcg: Canonicalize subi to addi during opcode generationRichard Henderson2023-11-061-16/+2
| | | | | | | | | | | | | | | | | | | | | Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20231026013945.1152174-2-richard.henderson@linaro.org>
| * | tcg/optimize: Split out arg_new_constantRichard Henderson2023-11-061-11/+18
| | | | | | | | | | | | | | | | | | | | | | | | Fixes a bug wherein raw uses of tcg_constant_internal do not have their TempOptInfo initialized. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg: Eliminate duplicate env store operationsRichard Henderson2023-11-061-0/+13
| | | | | | | | | | | | | | | | | | | | | Notice when a constant is stored to the same location twice. Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/optimize: Optimize env memory operationsRichard Henderson2023-11-061-21/+243
| | | | | | | | | | | | | | | | | | | | | Propagate stores to loads, loads to loads. Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/optimize: Split out cmp_better_copyRichard Henderson2023-11-061-18/+11
| | | | | | | | | | | | | | | | | | | | | | | | Compare two temps for "better", split out from finding the best from a whole list. Use TCGKind, which already gives the proper priority. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/optimize: Pipe OptContext into reset_tsRichard Henderson2023-11-061-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | Will be needed in the next patch. Reviewed-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg: Don't free vector resultsRichard Henderson2023-11-061-74/+38
| | | | | | | | | | | | | | | | | | | | | | | | Avoid reusing vector temporaries so that we may re-use them when propagating stores to loads. Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg: Remove TCG_TARGET_HAS_neg_{i32,i64}Richard Henderson2023-11-0616-43/+15
| | | | | | | | | | | | | | | | | | | | | The movcond opcode is now mandatory for backends to implement. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231026041404.1229328-7-richard.henderson@linaro.org>
| * | tcg/loongarch64: Implement neg opcodesRichard Henderson2023-11-062-2/+11
| | | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231026041404.1229328-6-richard.henderson@linaro.org>
| * | tcg/mips: Implement neg opcodesRichard Henderson2023-11-062-2/+10
| | | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231026041404.1229328-5-richard.henderson@linaro.org>
| * | tcg: Remove TCG_TARGET_HAS_movcond_{i32,i64}Richard Henderson2023-11-0614-66/+14
| | | | | | | | | | | | | | | | | | | | | The movcond opcode is now mandatory for backends to implement. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231026041404.1229328-4-richard.henderson@linaro.org>
| * | tcg/mips: Always implement movcondRichard Henderson2023-11-062-7/+16
| | | | | | | | | | | | | | | | | | | | | Expand as branch over move if not supported in the ISA. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231026041404.1229328-3-richard.henderson@linaro.org>
| * | tcg/mips: Split out tcg_out_setcond_intRichard Henderson2023-11-061-172/+106
| | | | | | | | | | | | | | | | | | | | | | | | Return the temp and a set of flags, to be used as a primitive for setcond, brcond, movcond. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231026041404.1229328-2-richard.henderson@linaro.org>
| * | tcg: Move tcg_temp_free_* out of lineRichard Henderson2023-11-062-24/+30
| | | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231029210848.78234-12-richard.henderson@linaro.org>
| * | tcg: Move tcg_temp_new_*, tcg_global_mem_new_* out of lineRichard Henderson2023-11-064-77/+76
| | | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231029210848.78234-11-richard.henderson@linaro.org>
| * | tcg: Move tcg_constant_* out of lineRichard Henderson2023-11-064-26/+30
| | | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231029210848.78234-10-richard.henderson@linaro.org>
| * | tcg: Unexport tcg_gen_op*_{i32,i64}Richard Henderson2023-11-062-126/+52
| | | | | | | | | | | | | | | | | | | | | | | | These functions are no longer used outside tcg-op.c. There are several that are completely unused, so remove them. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231029210848.78234-9-richard.henderson@linaro.org>
| * | tcg: Move tcg_gen_opN declarations to tcg-internal.hRichard Henderson2023-11-062-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | These are used within tcg-op.c and tcg-op-ldst.c. There are no uses outside tcg/. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231029210848.78234-8-richard.henderson@linaro.org>
| * | tcg: Move vec_gen_* declarations to tcg-internal.hRichard Henderson2023-11-062-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | These are used within tcg-op-vec.c and tcg/host/tcg-target.c.inc. There are no uses outside tcg/. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231029210848.78234-7-richard.henderson@linaro.org>
| * | tcg: Move 64-bit expanders out of lineRichard Henderson2023-11-062-206/+169
| | | | | | | | | | | | | | | | | | | | | | | | This one is more complicated, combining 32-bit and 64-bit expansion with C if instead of preprocessor #if. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231029210848.78234-6-richard.henderson@linaro.org>
| * | tcg: Move 32-bit expanders out of lineRichard Henderson2023-11-062-122/+140
| | | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231029210848.78234-5-richard.henderson@linaro.org>
| * | tcg: Move generic expanders out of lineRichard Henderson2023-11-062-16/+19
| | | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231029210848.78234-4-richard.henderson@linaro.org>
| * | tcg: Move tcg_gen_op* out of lineRichard Henderson2023-11-062-208/+252
| | | | | | | | | | | | | | | | | | | | | | | | In addition to moving out of line, with CONFIG_DEBUG_TCG mark them all noinline. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231029210848.78234-3-richard.henderson@linaro.org>
| * | tcg: Mark tcg_gen_op* as noinlineRichard Henderson2023-11-061-8/+14
| | | | | | | | | | | | | | | | | | | | | | | | Encourage the compiler to tail-call rather than inline across the dozens of opcode expanders. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231029210848.78234-2-richard.henderson@linaro.org>
| * | accel/tcg: Fix condition for store_atom_insert_al16Richard Henderson2023-11-062-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | Store bytes under a mask is fundamentally a cmpxchg, not a straight store. Use HAVE_CMPXCHG128 instead of HAVE_ATOMIC128_RW. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230916220151.526140-8-richard.henderson@linaro.org>
| * | accel/tcg: Remove redundant case in store_atom_16Richard Henderson2023-11-061-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | We handled the HAVE_ATOMIC128_RW case with atomic16_set at the top of the function; the only thing left for a host without that support is to fall through to cpu_loop_exit_atomic. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230916220151.526140-7-richard.henderson@linaro.org>
| * | host/include/loongarch64: Add atomic16 load and storeRichard Henderson2023-11-063-0/+103
| | | | | | | | | | | | | | | | | | | | | | | | While loongarch64 does not have a 128-bit cmpxchg, it does have 128-bit atomic load and store via the vector unit. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230916220151.526140-6-richard.henderson@linaro.org>
| * | tcg/loongarch64: Use cpuinfo.hRichard Henderson2023-11-062-11/+5
| | | | | | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiajie Chen <c@jia.je> Message-Id: <20230916220151.526140-5-richard.henderson@linaro.org>
| * | util: Add cpuinfo for loongarch64Richard Henderson2023-11-063-0/+58
| | | | | | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiajie Chen <c@jia.je> Message-Id: <20230916220151.526140-4-richard.henderson@linaro.org>
| * | tcg/loongarch64: Use C_N2_I1 for INDEX_op_qemu_ld_a*_i128Richard Henderson2023-11-062-7/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use new registers for the output, so that we never overlap the input address, which could happen for user-only. This avoids a "tmp = addr + 0" in that case. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiajie Chen <c@jia.je> Message-Id: <20230916220151.526140-3-richard.henderson@linaro.org>
| * | tcg: Add C_N2_I1Richard Henderson2023-11-061-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | Constraint with two outputs, both in new registers. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiajie Chen <c@jia.je> Message-Id: <20230916220151.526140-2-richard.henderson@linaro.org>
| * | accel/tcg: Move HMP info jit and info opcount codeRichard Henderson2023-11-067-158/+154
| |/ | | | | | | | | | | | | | | | | | | Move all of it into accel/tcg/monitor.c. This puts everything about tcg that is only used by the monitor in the same place. Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | Merge tag 'pull-block-2023-11-06' of https://gitlab.com/hreitz/qemu into stagingStefan Hajnoczi2023-11-074-28/+51
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Block patches: - One patch to make qcow2's discard-no-unref option do better what it is supposed to do (i.e. prevent fragmentation) - Two fixes for zoned requests # -----BEGIN PGP SIGNATURE----- # # iQJGBAABCAAwFiEEy2LXoO44KeRfAE00ofpA0JgBnN8FAmVJHbgSHGhyZWl0ekBy # ZWRoYXQuY29tAAoJEKH6QNCYAZzfLn4QAKxuUYZaXirv6K4U2tW4aAJtc5uESdwv # WYhG7YU7MleBGCY0fRoih5thrPrzRLC8o1QhbRcA36+/PAZf4BYrJEfqLUdzuN5x # 6Vb1n3NRUzPD1+VfL/B9hVZhFbtTOUZuxPGEqCoHAmqBaeKuYRT1bLZbtRtPVLSk # 5eTMiyrpRMlBWc7O71eGKLqU4k0vAznwHBGf2Z93qWAsKcRZCwbAWYa7Q6rJ9jJ8 # 1jNsQuAk0p74/uGEpFhoEVrFEcV6pMbI4+jB9i0t9YYxT0tLIdIX1VUx+AHJfItk # IF2stB6SFOaAy2W3Fn+0oJvz40aMLzg9VjEeTpGmdlKC67ZTYa6Obwzy5WNLPIap # k7VUheUEe8qoKUtxQNxGLR/HKEJSFXyhU0lgAGxE1gl2xc1QFFFsrimpwFd3d37j # 3PwfhjARHonf4ZXgsvtIjb7nG9seMZYO7Vht0OztJyW8c2XN5OFVPir9xLbd9VUg # wZNGB8jAsHgj77+S/mRIwpP+laKL8wB7zYZ1mgFI98QJIYqL8tGdV/IiUhLljHzc # XAmwekOhBMMbgHhliBy9zDuTy59+zZ0FoxZPn/JvBjqBAkEnz9EbhHxi2imQg+1d # XSoLbx1X1yEbepWz8mCGiveLIPkt+3qMJuuQF76nURaA+nm3tCl/nKca6QLnVKzU # 2QtPWS0qRmwd # =5w7S # -----END PGP SIGNATURE----- # gpg: Signature made Tue 07 Nov 2023 01:09:12 HKT # gpg: using RSA key CB62D7A0EE3829E45F004D34A1FA40D098019CDF # gpg: issuer "hreitz@redhat.com" # gpg: Good signature from "Hanna Reitz <hreitz@redhat.com>" [unknown] # gpg: WARNING: The key's User ID is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: CB62 D7A0 EE38 29E4 5F00 4D34 A1FA 40D0 9801 9CDF * tag 'pull-block-2023-11-06' of https://gitlab.com/hreitz/qemu: file-posix: fix over-writing of returning zone_append offset block/file-posix: fix update_zones_wp() caller qcow2: keep reference on zeroize with discard-no-unref enabled Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * | file-posix: fix over-writing of returning zone_append offsetNaohiro Aota2023-11-061-9/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | raw_co_zone_append() sets "s->offset" where "BDRVRawState *s". This pointer is used later at raw_co_prw() to save the block address where the data is written. When multiple IOs are on-going at the same time, a later IO's raw_co_zone_append() call over-writes a former IO's offset address before raw_co_prw() completes. As a result, the former zone append IO returns the initial value (= the start address of the writing zone), instead of the proper address. Fix the issue by passing the offset pointer to raw_co_prw() instead of passing it through s->offset. Also, remove "offset" from BDRVRawState as there is no usage anymore. Fixes: 4751d09adcc3 ("block: introduce zone append write for zoned devices") Signed-off-by: Naohiro Aota <naohiro.aota@wdc.com> Message-Id: <20231030073853.2601162-1-naohiro.aota@wdc.com> Reviewed-by: Sam Li <faithilikerun@gmail.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Hanna Czenczek <hreitz@redhat.com>
| * | block/file-posix: fix update_zones_wp() callerSam Li2023-11-061-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the zoned request fail, it needs to update only the wp of the target zones for not disrupting the in-flight writes on these other zones. The wp is updated successfully after the request completes. Fixed the callers with right offset and nr_zones. Signed-off-by: Sam Li <faithilikerun@gmail.com> Message-Id: <20230825040556.4217-1-faithilikerun@gmail.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> [hreitz: Rebased and fixed comment spelling] Signed-off-by: Hanna Czenczek <hreitz@redhat.com>
| * | qcow2: keep reference on zeroize with discard-no-unref enabledJean-Louis Dupond2023-11-063-17/+39
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the discard-no-unref flag is enabled, we keep the reference for normal discard requests. But when a discard is executed on a snapshot/qcow2 image with backing, the discards are saved as zero clusters in the snapshot image. When committing the snapshot to the backing file, not discard_in_l2_slice is called but zero_in_l2_slice. Which did not had any logic to keep the reference when discard-no-unref is enabled. Therefor we add logic in the zero_in_l2_slice call to keep the reference on commit. Fixes: https://gitlab.com/qemu-project/qemu/-/issues/1621 Signed-off-by: Jean-Louis Dupond <jean-louis@dupond.be> Message-Id: <20231003125236.216473-2-jean-louis@dupond.be> [hreitz: Made the documentation change more verbose, as discussed on-list] Signed-off-by: Hanna Czenczek <hreitz@redhat.com>
* | Merge tag 'pull-target-arm-20231106' of ↵Stefan Hajnoczi2023-11-0714-31/+64
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * hw/arm/virt: fix PMU IRQ registration * hw/arm/virt: Report correct register sizes in ACPI DBG2/SPCR tables * hw/i386/intel_iommu: vtd_slpte_nonzero_rsvd(): assert no overflow * util/filemonitor-inotify: qemu_file_monitor_watch(): assert no overflow * mc146818rtc: rtc_set_time(): initialize tm to zeroes * block/nvme: nvme_process_completion() fix bound for cid * hw/core/loader: gunzip(): initialize z_stream * io/channel-socket: qio_channel_socket_flush(): improve msg validation * hw/arm/vexpress-a9: Remove useless mapping of RAM at address 0 * target/arm: Fix A64 LDRA immediate decode # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmVJBtUZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3qYTEACYqLV57JezgRFXzMEwKX3l # 9IYbFje+lGemobdJOEHhRvXjCNb+5TwhEfQasri0FBzokw16S3WOOF7roGb6YOU1 # od1SGiS2AbrmiazlBpamVO8z0WAEgbnXIoQa/3xKAGPJXszD2zK+06KnXS5xuCuD # nHojzIx7Gv4HEIs4huY39/YL2HMaxrqvXC8IAu51eqY+TPnETT+WI3HxlZ2OMIsn # 1Jnn+FeZfA1bhKx4JsD9MyHM1ovbjOwYkHOlzjU6fmTFFPGKRy0nxnjMNCBcXHQ+ # unemc/9BhEFup76tkX+JIlSBrPre5Mnh93DsGKSapwKPKq+fQhUDmzXY2r3OvQZX # ryxO4PJkCNTM1wZU6GeEDPWVfhgBKHUMv+tr9Mf9iBlyXRsmXLSEl7AFUUaFlgAL # dSMyiAaUlfvGa7Gtta9eFAJ/GeaiuJu2CYq6lvtRrNIHflLm3gVCef8gmwM5Eqxm # 3PNzEoabKyQQfz69j9RCLpoutMBq1sg2IzxW8UjAFupugcIABjLf0Sl11qA0/B89 # YX67B0ynQD9ajI2GS8ULid/tvEiJVgdZ2Ua3U3xpG54vKG1/54EUiCP8TtoIuoMy # bKg8AU9EIPN962PxoAwS+bSSdCu7/zBjVpg4T/zIzWRdgSjRsE21Swu5Ca934ng5 # VpVUuiwtI/zvHgqaiORu+w== # =UbqJ # -----END PGP SIGNATURE----- # gpg: Signature made Mon 06 Nov 2023 23:31:33 HKT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20231106' of https://git.linaro.org/people/pmaydell/qemu-arm: target/arm: Fix A64 LDRA immediate decode hw/arm/vexpress-a9: Remove useless mapping of RAM at address 0 io/channel-socket: qio_channel_socket_flush(): improve msg validation hw/core/loader: gunzip(): initialize z_stream block/nvme: nvme_process_completion() fix bound for cid mc146818rtc: rtc_set_time(): initialize tm to zeroes util/filemonitor-inotify: qemu_file_monitor_watch(): assert no overflow hw/i386/intel_iommu: vtd_slpte_nonzero_rsvd(): assert no overflow tests/qtest/bios-tables-test: Update virt SPCR and DBG2 golden references hw/arm/virt: Report correct register sizes in ACPI DBG2/SPCR tables. tests/qtest/bios-tables-test: Allow changes to virt SPCR and DBG2 hw/arm/virt: fix PMU IRQ registration Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * | target/arm: Fix A64 LDRA immediate decodePeter Maydell2023-11-062-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In commit be23a049 in the conversion to decodetree we broke the decoding of the immediate value in the LDRA instruction. This should be a 10 bit signed value that is scaled by 8, but in the conversion we incorrectly ended up scaling it only by 2. Fix the scaling factor. Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1970 Fixes: be23a049 ("target/arm: Convert load (pointer auth) insns to decodetree") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20231106113445.1163063-1-peter.maydell@linaro.org
| * | hw/arm/vexpress-a9: Remove useless mapping of RAM at address 0Peter Maydell2023-11-062-11/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the vexpress-a9 board we try to map both RAM and flash to address 0, as seen in "info mtree": address-space: memory 0000000000000000-ffffffffffffffff (prio 0, i/o): system 0000000000000000-0000000003ffffff (prio 0, romd): alias vexpress.flashalias @vexpress.flash0 0000000000000000-0000000003ffffff 0000000000000000-0000000003ffffff (prio 0, ram): alias vexpress.lowmem @vexpress.highmem 0000000000000000-0000000003ffffff 0000000010000000-0000000010000fff (prio 0, i/o): arm-sysctl 0000000010004000-0000000010004fff (prio 0, i/o): pl041 (etc) The flash "wins" and the RAM mapping is useless (but also harmless). This happened as a result of commit 6ec1588e in 2014, which changed "we always map the RAM to the low addresses for vexpress-a9" to "we always map flash in the low addresses", but forgot to stop mapping the RAM. In real hardware, this low part of memory is remappable, both at runtime by the guest writing to a control register, and configurably as to what you get out of reset -- you can have the first flash device, or the second, or the DDR2 RAM, or the external AXI bus (which for QEMU means "nothing there"). In an ideal world we would support that remapping both at runtime and via a machine property to select the out-of-reset behaviour. Pending anybody caring enough to implement the full remapping behaviour: * remove the useless mapped-but-inaccessible lowram MR * document that QEMU doesn't support remapping of low memory Fixes: 6ec1588e ("hw/arm/vexpress: Alias NOR flash at 0 for vexpress-a9") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1761 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231103185602.875849-1-peter.maydell@linaro.org