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* Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into stagingPeter Maydell2024-10-2921-139/+245
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCAAdFiEEIV1G9IJGaJ7HfzVi7wSWWzmNYhEFAmcglKYACgkQ7wSWWzmN # YhEm/wf/cYA7i3asKMUoYqlff5mBiY3aFCWzTR5qHLBcWfnB33f9FYpAW6RgDwMa # 3aFAJm1VZAynmUWgz+f537+e+7900M+P54zbD7kHCthAy7l/E7t9SkKNpe6jZHEA # P4hB09CSKm/TY1XtsFMvO5tkF9IgY51VEO+mZJesO1H2X2+3ulJYusx9fh/P6yST # bG8sbXr55v23R3z4UOovqfkuskPETwRh3qoiOLPPBy8CWkBVze8J+siC7HC+eFIo # KrQ+jhUYpIK8CAgHV09ZnlurLo6UZ0+vlo9IcJN+GQp/gsmg8OErjvzPdKKbynC/ # 1zjvkgyW27aHsei+baTMXGCE0P8dIw== # =6+yo # -----END PGP SIGNATURE----- # gpg: Signature made Tue 29 Oct 2024 07:54:14 GMT # gpg: using RSA key 215D46F48246689EC77F3562EF04965B398D6211 # gpg: Good signature from "Jason Wang (Jason Wang on RedHat) <jasowang@redhat.com>" [marginal] # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 215D 46F4 8246 689E C77F 3562 EF04 965B 398D 6211 * tag 'net-pull-request' of https://github.com/jasowang/qemu: virtio-net: Avoid indirection_table_mask overflow Fix calculation of minimum in colo_compare_tcp net: Check if nc is NULL in qemu_get_vnet_hdr_len() net/tap-win32: Fix gcc 14 format truncation errors chardev: finalize 'reconnect' deprecation net/stream: deprecate 'reconnect' in favor of 'reconnect-ms' hw/net: improve tracing of eBPF RSS setup ebpf: improve trace event coverage to all key operations hw/net: report errors from failing to use eBPF RSS FDs ebpf: add formal error reporting to all APIs ebpf: improve error trace events ebpf: drop redundant parameter checks in static methods hw/net: fix typo s/epbf/ebpf/ in virtio-net net: fix build when libbpf is disabled, but libxdp is enabled Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * virtio-net: Avoid indirection_table_mask overflowAkihiko Odaki2024-10-291-6/+6
| | | | | | | | | | | | | | | | | | | | We computes indirections_len by adding 1 to indirection_table_mask, but it may overflow indirection_table_mask is UINT16_MAX. Check if indirection_table_mask is small enough before adding 1. Fixes: 590790297c0d ("virtio-net: implement RSS configuration command") Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
| * Fix calculation of minimum in colo_compare_tcpStefan Weil2024-10-291-2/+1
| | | | | | | | | | | | | | | | | | | | | | GitHub's CodeQL reports a critical error which is fixed by using the MIN macro: Unsigned difference expression compared to zero Signed-off-by: Stefan Weil <sw@weilnetz.de> Cc: qemu-stable@nongnu.org Reviewed-by: Zhang Chen <chen.zhang@intel.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
| * net: Check if nc is NULL in qemu_get_vnet_hdr_len()Akihiko Odaki2024-10-281-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | A netdev may not have a peer specified, resulting in NULL. We should make it behave like /dev/null in such a case instead of letting it cause segmentatin fault. Fixes: 4b52d63249a5 ("tap: Remove qemu_using_vnet_hdr()") Cc: qemu-stable@nongnu.org Reported-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Tested-by; Jonathan Cameron <Jonathan.Cameron@huawei.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
| * net/tap-win32: Fix gcc 14 format truncation errorsBernhard Beschow2024-10-281-9/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch fixes the following errors generated by GCC 14.2: ../src/net/tap-win32.c:343:19: error: '%s' directive output may be truncated writing up to 255 bytes into a region of size 176 [-Werror=format-truncation=] 343 | "%s\\%s\\Connection", | ^~ 344 | NETWORK_CONNECTIONS_KEY, enum_name); | ~~~~~~~~~ ../src/net/tap-win32.c:341:9: note: 'snprintf' output between 92 and 347 bytes into a destination of size 256 341 | snprintf(connection_string, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ 342 | sizeof(connection_string), | ~~~~~~~~~~~~~~~~~~~~~~~~~~ 343 | "%s\\%s\\Connection", | ~~~~~~~~~~~~~~~~~~~~~ 344 | NETWORK_CONNECTIONS_KEY, enum_name); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../src/net/tap-win32.c:242:58: error: '%s' directive output may be truncated writing up to 255 bytes into a region of size 178 [-Werror=format-truncation=] 242 | snprintf (unit_string, sizeof(unit_string), "%s\\%s", | ^~ 243 | ADAPTER_KEY, enum_name); | ~~~~~~~~~ ../src/net/tap-win32.c:242:9: note: 'snprintf' output between 79 and 334 bytes into a destination of size 256 242 | snprintf (unit_string, sizeof(unit_string), "%s\\%s", | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 243 | ADAPTER_KEY, enum_name); | ~~~~~~~~~~~~~~~~~~~~~~~ ../src/net/tap-win32.c:620:52: error: '%s' directive output may be truncated writing up to 255 bytes into a region of size 245 [-Werror=format-truncation=] 620 | snprintf (device_path, sizeof(device_path), "%s%s%s", | ^~ 621 | USERMODEDEVICEDIR, 622 | device_guid, | ~~~~~~~~~~~ ../src/net/tap-win32.c:620:5: note: 'snprintf' output between 16 and 271 bytes into a destination of size 256 620 | snprintf (device_path, sizeof(device_path), "%s%s%s", | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 621 | USERMODEDEVICEDIR, | ~~~~~~~~~~~~~~~~~~ 622 | device_guid, | ~~~~~~~~~~~~ 623 | TAPSUFFIX); | ~~~~~~~~~~ Signed-off-by: Bernhard Beschow <shentey@gmail.com> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2607 Cc: qemu-stable@nongnu.org Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Jason Wang <jasowang@redhat.com>
| * chardev: finalize 'reconnect' deprecationDaniil Tatianin2024-10-286-20/+20
| | | | | | | | | | | | | | | | | | Change all related docs and tests to use the new 'reconnect-ms' option instead of the now deprecated 'reconnect'. Signed-off-by: Daniil Tatianin <d-tatianin@yandex-team.ru> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
| * net/stream: deprecate 'reconnect' in favor of 'reconnect-ms'Daniil Tatianin2024-10-285-26/+57
| | | | | | | | | | | | | | | | | | | | | | Do the same thing we already did for chardev in c8e2b6b4d7e, and introduce a new 'reconnect-ms' option to make it possible to specify sub-second timeouts. This also changes the related documentaion and tests to use reconnect-ms as well. Signed-off-by: Daniil Tatianin <d-tatianin@yandex-team.ru> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
| * hw/net: improve tracing of eBPF RSS setupDaniel P. Berrangé2024-10-282-6/+11
| | | | | | | | | | | | | | | | This adds more trace events to key eBPF RSS setup operations, and also distinguishes events from multiple NIC instances. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
| * ebpf: improve trace event coverage to all key operationsDaniel P. Berrangé2024-10-282-0/+23
| | | | | | | | | | | | | | | | | | The existing error trace event is renamed to have a name prefix matching its source file & to remove the redundant first arg that adds no useful information. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
| * hw/net: report errors from failing to use eBPF RSS FDsDaniel P. Berrangé2024-10-281-12/+29
| | | | | | | | | | | | | | | | | | | | | | | | If the user/mgmt app passed in a set of pre-opened FDs for eBPF RSS, then it is expecting QEMU to use them. Any failure to do so must be considered a fatal error and propagated back up the stack, otherwise deployment mistakes will not be detectable in a prompt manner. When not using pre-opened FDs, then eBPF RSS is tried on a "best effort" basis only and thus fallback to software RSS is valid. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
| * ebpf: add formal error reporting to all APIsDaniel P. Berrangé2024-10-284-20/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | The eBPF code is currently reporting error messages through trace events. Trace events are fine for debugging, but they are not to be considered the primary error reporting mechanism, as their output is inaccessible to callers. This adds an "Error **errp" parameter to all methods which have important error scenarios to report to the caller. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
| * ebpf: improve error trace eventsDaniel P. Berrangé2024-10-282-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | A design pattern of trace_foo_error("descriptive string") is undesirable because it does not allow for filtering trace events based on the error scenario. Split eBPF error trace event into three separate events to address this filtering need. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
| * ebpf: drop redundant parameter checks in static methodsDaniel P. Berrangé2024-10-281-27/+5
| | | | | | | | | | | | | | | | | | | | Various static methods have checks on their parameters which were already checked immediately before the method was invoked. Drop these redundat checks to simplify the following commit which adds formal error reporting. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
| * hw/net: fix typo s/epbf/ebpf/ in virtio-netDaniel P. Berrangé2024-10-281-5/+5
| | | | | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
| * net: fix build when libbpf is disabled, but libxdp is enabledDaniel P. Berrangé2024-10-282-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The net/af-xdp.c code is enabled when the libxdp library is present, however, it also has direct API calls to bpf_xdp_query_id & bpf_xdp_detach which are provided by the libbpf library. As a result if building with --disable-libbpf, but libxdp gets auto-detected, we'll fail to link QEMU /usr/bin/ld: libcommon.a.p/net_af-xdp.c.o: undefined reference to symbol 'bpf_xdp_query_id@@LIBBPF_0.7.0' There are two bugs here * Since we have direct libbpf API calls, when building net/af-xdp.c, we must tell meson that libbpf is a dependancy, so that we directly link to it, rather than relying on indirect linkage. * When must skip probing for libxdp at all, when libbpf is not found, raising an error if --enable-libxdp was given explicitly. Fixes: cb039ef3d9e3112da01e1ecd9b136ac9809ef733 Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
* | Merge tag 'pull-maintainer-oct-misc-241024-1' of ↵Peter Maydell2024-10-2523-58/+273
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.com/stsquad/qemu into staging testing, gdbstub and plugin updates - update MAINTAINERS with pointers to foo/next - add NOFETCH to help test custom docker builds - update microblaze toolchain with atomic fixes - update tsan build and documentation - don't restrict build-environment by arch unless needed - add cross-modifying code test - add tracepoints for cpu_step_atomic fallbacks - fix defaults for loongarch cross build - make check-[dco|patch] a little more verbose - fix gdbstub bug preventing aarch64_be-linux-user starting - add basic test for aarch64_be - clean up some gdbstub test scripts - fix qemu_plugin_reset # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEEZoWumedRZ7yvyN81+9DbCVqeKkQFAmcaDeQACgkQ+9DbCVqe # KkRTlQgAlFaP1Nxa8y6pRZSL0WY9J3Znf5e2GDnVN3nJbfx1wZg7oZ4/dWieDF/Y # /9jLfMi8nDJ51tzH24PSASbHQ1xnblhuUfhRMwqAFhSwsZUb0VzdeGdq+FIyXQ5w # Cy2Ubz7g81qP/x9JRCCUGFfXaM1LSizsY1lNioRsDd533WJLkvxWucmpSN3XhxHJ # rEa3xI/qAcUah4G3yww47L+DmlKnJQcsihShRBC6Am2tWqxbz+1kBUaVfaVVo1if # IPN+bBk4eI1EHdRRyWJSsq3nELzqW4FJ3+9V0ifsOFW2KGsnkhbl0qUxqDmW5aBb # P9flEdpTfSiCbqp+IKG9vxJKuf/BGw== # =5Wui # -----END PGP SIGNATURE----- # gpg: Signature made Thu 24 Oct 2024 10:05:40 BST # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * tag 'pull-maintainer-oct-misc-241024-1' of https://gitlab.com/stsquad/qemu: plugins: fix qemu_plugin_reset MAINTAINERS: mention my plugins/next tree testing: Enhance gdb probe script tests/tcg/aarch64: Use raw strings for regexes in test-mte.py tests/tcg: enable basic testing for aarch64_be-linux-user config/targets: update aarch64_be-linux-user gdb XML list MAINTAINERS: mention my gdbstub/next tree gitlab: make check-[dco|patch] a little more verbose dockerfiles: fix default targets for debian-loongarch-cross accel/tcg: add tracepoints for cpu_loop_exit_atomic tests/tcg/x86_64: Add cross-modifying code test scripts/ci: remove architecture checks for build-environment updates docs/devel: update tsan build documentation meson: hide tsan related warnings MAINTAINERS: mention my testing/next tree tests/docker: add NOFETCH env variable for testing tests/docker: Fix microblaze atomics Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * plugins: fix qemu_plugin_resetPierrick Bouvier2024-10-241-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 34e5e1 refactored the plugin context initialization. After this change, tcg_ctx->plugin_insn is not reset inconditionnally anymore, but only if one plugin at least is active. When uninstalling the last plugin active, we stopped reinitializing tcg_ctx->plugin_insn, which leads to memory callbacks being emitted. This results in an error as they don't appear in a plugin op sequence as expected. The correct fix is to make sure we reset plugin translation variables after current block translation ends. This way, we can catch any potential misuse of those after a given block, in more than fixing the current bug. Fixes: https://gitlab.com/qemu-project/qemu/-/issues/2570 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Tested-by: Robbin Ehn <rehn@rivosinc.com> Message-Id: <20241015003819.984601-1-pierrick.bouvier@linaro.org> [AJB: trim patch version details from commit msg] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20241023113406.1284676-19-alex.bennee@linaro.org>
| * MAINTAINERS: mention my plugins/next treeAlex Bennée2024-10-241-0/+1
| | | | | | | | | | | | | | | | Make it easier to find where plugin patches are being staged. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20241023113406.1284676-17-alex.bennee@linaro.org>
| * testing: Enhance gdb probe scriptGustavo Romero2024-10-241-36/+39
| | | | | | | | | | | | | | | | | | | | | | Use list and set comprehension to simplify code. Also, gently handle invalid gdb filenames. Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-Id: <20241015145848.387281-1-gustavo.romero@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20241023113406.1284676-16-alex.bennee@linaro.org>
| * tests/tcg/aarch64: Use raw strings for regexes in test-mte.pyGustavo Romero2024-10-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Use Python's raw string notation instead of string literals for regex so it's not necessary to double backslashes when regex special forms are used. Raw notation is preferred for regex and easier to read. Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20241015140806.385449-1-gustavo.romero@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20241023113406.1284676-15-alex.bennee@linaro.org>
| * tests/tcg: enable basic testing for aarch64_be-linux-userAlex Bennée2024-10-244-1/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We didn't notice breakage of aarch64_be because we don't have any TCG tests for it. However while the existing aarch64 compiler can target big-endian builds no one packages a BE libc. Instead we bang some rocks together to do the most basic of hello world with a nostdlib syscall test. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20241023113406.1284676-14-alex.bennee@linaro.org>
| * config/targets: update aarch64_be-linux-user gdb XML listAlex Bennée2024-10-241-1/+1
| | | | | | | | | | | | | | | | | | | | Attempting to run the binary asserts when it can't find the XML entry. We can fix it so we don't although I suspect other stuff is broken. Fixes: https://gitlab.com/qemu-project/qemu/-/issues/2580 Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20241023113406.1284676-13-alex.bennee@linaro.org>
| * MAINTAINERS: mention my gdbstub/next treeAlex Bennée2024-10-241-0/+1
| | | | | | | | | | | | | | | | | | Make it easy for people to see what is already queued. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20241023113406.1284676-12-alex.bennee@linaro.org>
| * gitlab: make check-[dco|patch] a little more verboseAlex Bennée2024-10-242-6/+4
| | | | | | | | | | | | | | | | | | | | When git fails the rather terse backtrace only indicates it failed without some useful context. Add some to make the log a little more useful. Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20241023113406.1284676-11-alex.bennee@linaro.org>
| * dockerfiles: fix default targets for debian-loongarch-crossPierrick Bouvier2024-10-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | fix system target name, and remove --disable-system (which deactivates system target). Found using: make docker-test-build@debian-loongarch-cross V=1 Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20241020213759.2168248-1-pierrick.bouvier@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20241023113406.1284676-10-alex.bennee@linaro.org>
| * accel/tcg: add tracepoints for cpu_loop_exit_atomicAlex Bennée2024-10-243-1/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We try to avoid using cpu_loop_exit_atomic as it brings in an all-core sync point. However on some cpu/kernel/benchmark combinations it is starting to show up in the performance profile. To make it easier to see whats going on add tracepoints for the slow path so we can see what is triggering the wait. It seems for a modern CPU it can be quite a bit, for example: ./qemu-system-aarch64 \ -machine type=virt,virtualization=on,pflash0=rom,pflash1=efivars,gic-version=max \ -smp 4 \ -accel tcg \ -device virtio-net-pci,netdev=unet \ -device virtio-scsi-pci \ -device scsi-hd,drive=hd \ -netdev user,id=unet,hostfwd=tcp::2222-:22 \ -blockdev driver=raw,node-name=hd,file.driver=host_device,file.filename=/dev/zen-ssd2/trixie-arm64,discard=unmap \ -serial mon:stdio \ -blockdev node-name=rom,driver=file,filename=(pwd)/pc-bios/edk2-aarch64-code.fd,read-only=true \ -blockdev node-name=efivars,driver=file,filename=$HOME/images/qemu-arm64-efivars \ -m 8192 \ -object memory-backend-memfd,id=mem,size=8G,share=on \ -kernel /home/alex/lsrc/linux.git/builds/arm64/arch/arm64/boot/Image -append "root=/dev/sda2 console=ttyAMA0 systemd.unit=benchmark-stress-ng.service" \ -display none -d trace:load_atom\*_fallback,trace:store_atom\*_fallback With: -cpu neoverse-v1,pauth-impdef=on => 2203343 With: -cpu cortex-a76 => 0 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20241023113406.1284676-9-alex.bennee@linaro.org>
| * tests/tcg/x86_64: Add cross-modifying code testIlya Leoshkevich2024-10-242-0/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit f025692c992c ("accel/tcg: Clear PAGE_WRITE before translation") fixed cross-modifying code handling, but did not add a test. The changed code was further improved recently [1], and I was not sure whether these modifications were safe (spoiler: they were fine). Add a test to make sure there are no regressions. [1] https://lists.gnu.org/archive/html/qemu-devel/2022-09/msg00034.html Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-Id: <20241001150617.9977-1-iii@linux.ibm.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20241023113406.1284676-8-alex.bennee@linaro.org>
| * scripts/ci: remove architecture checks for build-environment updatesAlex Bennée2024-10-241-2/+0
| | | | | | | | | | | | | | | | | | | | We were missing s390x here. There isn't much point testing for the architecture here as we will fail anyway if the appropriate package list is missing. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20241023113406.1284676-7-alex.bennee@linaro.org>
| * docs/devel: update tsan build documentationPierrick Bouvier2024-10-241-4/+22
| | | | | | | | | | | | | | | | | | | | | | Mention it's now possible to build with gcc, instead of clang, and explain how to build a sanitized glib version. Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20240910174013.1433331-4-pierrick.bouvier@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20241023113406.1284676-6-alex.bennee@linaro.org>
| * meson: hide tsan related warningsPierrick Bouvier2024-10-241-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When building with gcc-12 -fsanitize=thread, gcc reports some constructions not supported with tsan. Found on debian stable. qemu/include/qemu/atomic.h:36:52: error: ‘atomic_thread_fence’ is not supported with ‘-fsanitize=thread’ [-Werror=tsan] 36 | #define smp_mb() ({ barrier(); __atomic_thread_fence(__ATOMIC_SEQ_CST); }) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20240910174013.1433331-2-pierrick.bouvier@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20241023113406.1284676-5-alex.bennee@linaro.org>
| * MAINTAINERS: mention my testing/next treeAlex Bennée2024-10-241-0/+1
| | | | | | | | | | | | | | | | | | I put it under my name as there may be other maintainer testing trees as well. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20241023113406.1284676-4-alex.bennee@linaro.org>
| * tests/docker: add NOFETCH env variable for testingAlex Bennée2024-10-241-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | Testing non-auto built docker containers (i.e. custom built compilers) is a bit fiddly as you couldn't continue a build with a previously locally built container. While you can play games with REGISTRY its simpler to allow a NOFETCH that will go through the cached build process when you run the tests. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20241023113406.1284676-3-alex.bennee@linaro.org>
| * tests/docker: Fix microblaze atomicsIlya Leoshkevich2024-10-242-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | GCC produces invalid code for microblaze atomics. The fix is unfortunately not upstream, so fetch it from an external location and apply it locally. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-Id: <20240919152308.10440-1-iii@linux.ibm.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20241023113406.1284676-2-alex.bennee@linaro.org>
* | Merge tag 'pull-aspeed-20241024' of https://github.com/legoater/qemu into ↵Peter Maydell2024-10-2518-382/+1002
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging aspeed queue: * Fixed GPIO interrupt status when in index mode * Added GPIO support for the AST2700 SoC and specific test cases * Fixed crypto controller (HACE) Accumulative hash function * Converted Aspeed machine avocado tests to the new functional framework. SDK tests still to be addressed. * Fixed issue in the SSI controller when doing writes in user mode * Added support for the WRSR2 register of Winbond flash devices * Added SFDP table for the Windbond w25q80bl flash device * Changed flash device models for the ast1030-a1 EVB # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmcZ6MIACgkQUaNDx8/7 # 7KFQPA//RTxi1PmCDlzd1ffzMWEadD3CpGLJ4RgEeZpNtkx6IF2uFFBdlNgjTSmD # B8FdIOVb8qo2omXahKIVIgoKbGgn3U3jciH67D/x4Jyp8IhW6n5XwZzKNJ7kLVHX # IluGmlvqNumSKl3vxsLvprC0ojRiO/SfWkzS6VOwoFPM7uNDTybQicWBBoy3Jh3e # VVlMwIeKHMQVJGpI8PQbtnFZO4HaMqWwlo0EoIJji59fdyWULLvrXzH9YhzwFVjQ # oCNvJUBLfxLse7c13cm/LuNmw+IQtLC5OztsOOtv1XZ1MruhJ7t316eGsQEpeWcD # Yy5RK4mIBJMExu9oxcKOqgSznQSgenvNGWg6Z9FyyKGciylafnE8GeT35WObumyD # v9gzgeLcw5DgvDgQXaYi4IkKyezaHoE3HPbFdBEZHBt8tn5pPGmXM0lEWL5xQ5B8 # h6HphjxIlFxeHIxYenLJowLBMOt8aFXzGboF2XCLrx19OC2zvoo7klCbFeAfZpvQ # JMXP+GsQIe7fnBMbyXGrJh9q+/7tKR4ivtTV/vnSF0FPtyzxdoSrYsUA4SZqSWvI # ONz62p+zlE/oXBUIaFnC2Ea41YwJ7mDbmcSU1dFxmE0xRVmoYlUocoeS2VOUmTH0 # CMgEcmMXQG0vx8nipQbScbuWRCBlf0YwJ7Y7stgI8HabmsMMbIg= # =DqCH # -----END PGP SIGNATURE----- # gpg: Signature made Thu 24 Oct 2024 07:27:14 BST # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@redhat.com>" [full] # gpg: aka "Cédric Le Goater <clg@kaod.org>" [full] # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-aspeed-20241024' of https://github.com/legoater/qemu: test/qtest/aspeed_smc-test: Fix coding style hw/arm/aspeed: Correct fmc_model w25q80bl for ast1030-a1 EVB hw/arm/aspeed: Correct spi_model w25q256 for ast1030-a1 EVB. hw/block/m25p80: Add SFDP table for w25q80bl flash hw/block:m25p80: Support write status register 2 command (0x31) for w25q01jvq hw/block:m25p80: Fix coding style aspeed/smc: Fix write incorrect data into flash in user mode tests/functional: Convert most Aspeed machine tests hw/misc/aspeed_hace: Fix SG Accumulative hashing tests/qtest:ast2700-gpio-test: Add GPIO test case for AST2700 aspeed/soc: Support GPIO for AST2700 aspeed/soc: Correct GPIO irq 130 for AST2700 hw/gpio/aspeed: Add AST2700 support hw/gpio/aspeed: Fix clear incorrect interrupt status for GPIO index mode hw/gpio/aspeed: Support different memory region ops hw/gpio/aspeed: Support to set the different memory size hw/gpio/aspeed: Fix coding style Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | test/qtest/aspeed_smc-test: Fix coding styleJamin Lin2024-10-241-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | Fix coding style issues from checkpatch.pl Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
| * | hw/arm/aspeed: Correct fmc_model w25q80bl for ast1030-a1 EVBJamin Lin2024-10-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the default fmc_model was "sst25vf032b" whose size was 4MB for ast1030-a1 EVB. However, according to the schematic of ast1030-a1 EVB, ASPEED shipped default flash of fmc_cs0 and fmc_cs1 were "w25q80bl" and "w25q256", respectively. The size of w25q80bl is 1MB and the size of w25q256 is 32MB. The fmc_cs0 was connected to AST1030 A1 internal flash and the fmc_cs1 was connected to external flash. The internal flash could not be changed because it was placed into AST1030 A1 chip. Users only can change fmc_cs1 external flash. So far, only supports to set the default fmc_model for all chip select pins. In other words, users cannot set the different default flash model for fmc_cs0 and fmc_cs1, respectively. Correct fmc_model default flash to w25q80bl the same as AST1030 A1 internal flash for ast1030-a1 EVB. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
| * | hw/arm/aspeed: Correct spi_model w25q256 for ast1030-a1 EVB.Jamin Lin2024-10-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the default spi_model was "sst25vf032b" whose size was 4MB for ast1030-a1 EVB. However, according to the schematic of ast1030-a1 EVB, ASPEED shipped default flash of spi1 and spi2 were w25q256 whose size was 32MB. Correct spi_model default flash to w25q256 for ast1030-a1 EVB. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
| * | hw/block/m25p80: Add SFDP table for w25q80bl flashJamin Lin2024-10-243-2/+39
| | | | | | | | | | | | | | | | | | | | | Add the SFDP table for the Windbond w25q80bl flash. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
| * | hw/block:m25p80: Support write status register 2 command (0x31) for w25q01jvqJamin Lin2024-10-241-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the w25q01jv datasheet at page 16, it is required to set QE bit in "Status Register 2" to enable quad mode. Currently, m25p80 support users utilize "Write Status Register 1(0x01)" command to set QE bit in "Status Register 2" and utilize "Read Status Register 2(0x35)" command to get the QE bit status. However, some firmware directly utilize "Status Register 2(0x31)" command to set QE bit. To fully support quad mode for w25q01jvq, adds WRSR2 command. Update collecting data needed 1 byte for WRSR2 command in decode_new_cmd function and verify QE bit at the first byte of collecting data bit 2 in complete_collecting_data. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
| * | hw/block:m25p80: Fix coding styleJamin Lin2024-10-241-8/+14
| | | | | | | | | | | | | | | | | | | | | Fix coding style issues from checkpatch.pl Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
| * | aspeed/smc: Fix write incorrect data into flash in user modeJamin Lin2024-10-242-12/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the design of ASPEED SPI controllers user mode, users write the data to flash, the SPI drivers set the Control Register(0x10) bit 0 and 1 enter user mode. Then, SPI drivers send flash commands for writing data. Finally, SPI drivers set the Control Register (0x10) bit 2 to stop active control and restore bit 0 and 1. According to the design of ASPEED SMC model, firmware writes the Control Register and the "aspeed_smc_flash_update_ctrl" function is called. Then, this function verify Control Register(0x10) bit 0 and 1. If it set user mode, the value of s->snoop_index is SNOOP_START else SNOOP_OFF. If s->snoop_index is SNOOP_START, the "aspeed_smc_do_snoop" function verify the first incomming data is a new flash command and writes the corresponding dummy bytes if need. However, it did not check the current unselect status. If current unselect status is "false" and firmware set the IO MODE by Control Register bit 31:28, the value of s->snoop_index will be changed to SNOOP_START again and "aspeed_smc_do_snoop" misunderstand that the incomming data is the new flash command and it causes writing unexpected data into flash. Example: 1. Firmware set user mode by Control Register bit 0 and 1(0x03) 2. SMC model set s->snoop SNOOP_START 3. Firmware set Quad Page Program with 4-Byte Address command (0x34) 4. SMC model verify this flash command and it needs 4 dummy bytes. 5. Firmware send 4 bytes address. 6. SMC model receives 4 bytes address 7. Firmware set QPI IO MODE by Control Register bit 31. (0x80000003) 8. SMC model verify new user mode by Control Register bit 0 and 1. Then, set s->snoop SNOOP_START again. (It is the wrong behavior.) 9. Firmware send 0xebd8c134 data and it should be written into flash. However, SMC model misunderstand that the first incoming data, 0x34, is the new command because the value of s->snoop is changed to SNOOP_START. Finally, SMC sned the incorrect data to flash model. Introduce a new unselect attribute in AspeedSMCState to save the current unselect status for user mode and set it "true" by default. Update "aspeed_smc_flash_update_ctrl" function to check the previous unselect status. If both new unselect status and previous unselect status is different, update s->snoop_index value and call "aspeed_smc_flash_do_select". Increase VMStateDescription version. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> [ clg: - Replaced VMSTATE_BOOL -> VMSTATE_BOOL_V ] Signed-off-by: Cédric Le Goater <clg@redhat.com>
| * | tests/functional: Convert most Aspeed machine testsCédric Le Goater2024-10-243-292/+284
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a simple conversion of the tests with some cleanups and adjustments to match the new test framework. Replace the zephyr image MD5 hashes with SHA256 hashes while at it. The SDK tests depend on a ssh class from avocado.utils which is difficult to replace. To be addressed separately. Signed-off-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com>
| * | hw/misc/aspeed_hace: Fix SG Accumulative hashingAlejandro Zeise2024-10-242-45/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make the Aspeed HACE module use the new qcrypto accumulative hashing functions when in scatter-gather accumulative mode. A hash context will maintain a "running-hash" as each scatter-gather chunk is received. Previously each scatter-gather "chunk" was cached so the hash could be computed once the final chunk was received. However, the cache was a shallow copy, so once the guest overwrote the memory provided to HACE the final hash would not be correct. Possibly related to: https://gitlab.com/qemu-project/qemu/-/issues/1121 Buglink: https://github.com/openbmc/qemu/issues/36 Signed-off-by: Alejandro Zeise <alejandro.zeise@seagate.com> [ clg: - Checkpatch fixes - Reworked qcrypto_hash*() error reports in do_hash_operation() ] Signed-off-by: Cédric Le Goater <clg@redhat.com> Acked-by: Andrew Jeffery <andrew@codeconstruct.com.au> Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au>
| * | tests/qtest:ast2700-gpio-test: Add GPIO test case for AST2700Jamin Lin2024-10-243-0/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add GPIO test cases to test output and input pins from A0 to D7 for AST2700. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Thomas Huth <thuth@redhat.com> [ clg: - Updated MAINTAINERS ] Signed-off-by: Cédric Le Goater <clg@redhat.com>
| * | aspeed/soc: Support GPIO for AST2700Jamin Lin2024-10-241-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | Add GPIO model for AST2700 GPIO support. The GPIO controller registers base address is start at 0x14C0_B000 and its address space is 0x1000. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
| * | aspeed/soc: Correct GPIO irq 130 for AST2700Jamin Lin2024-10-241-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The register set of GPIO have a significant change since AST2700. Each GPIO pin has their own individual control register and users are able to set one GPIO pin’s direction, interrupt enable, input mask and so on in the same one control register. AST2700 does not have GPIO18_XXX registers for GPIO 1.8v, removes ASPEED_DEV_GPIO_1_8V. It is enough to only have ASPEED_DEV_GPIO device in AST2700. The AST2700 GPIO controller interrupt is connected to GICINT130_INTC at bit 18. Therefore, correct GPIO irq 130. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
| * | hw/gpio/aspeed: Add AST2700 supportJamin Lin2024-10-241-0/+380
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AST2700 integrates two set of Parallel GPIO Controller with maximum 212 control pins, which are 27 groups. (H, exclude pin: H7 H6 H5 H4) In the previous design of ASPEED SOCs, one register is used for setting one function for one set which are 32 pins and 4 groups. ex: GPIO000 is used for setting data value for GPIO A, B, C and D in AST2600. ex: GPIO004 is used for setting direction for GPIO A, B, C and D in AST2600. However, the register set have a significant change since AST2700. Each GPIO pin has their own individual control register. In other words, users are able to set one GPIO pin’s direction, interrupt enable, input mask and so on in the same one register. Currently, aspeed_gpio_read and aspeed_gpio_write callback functions are not compatible AST2700. Introduce new aspeed_gpio_2700_read and aspeed_gpio_2700_write callback functions and aspeed_gpio_2700_ops memory region operation for AST2700. Introduce a new ast2700 class to support AST2700. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
| * | hw/gpio/aspeed: Fix clear incorrect interrupt status for GPIO index modeJamin Lin2024-10-241-10/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The interrupt status field is W1C, where a set bit on read indicates an interrupt is pending. If the bit extracted from data is set it should clear the corresponding bit in reg_value. However, if the extracted bit is clear then the value of the corresponding bit in reg_value should be unchanged. SHARED_FIELD_EX32() extracts the interrupt status bit from the write (data). reg_value is set to the set's interrupt status, which means that for any pin with an interrupt pending, the corresponding bit is set. The deposit32() call updates the bit at pin_idx in the reg_value, using the value extracted from the write (data). The result is that if multiple interrupt status bits were pending and the write was acknowledging specific one bit, then the all interrupt status bits will be cleared. However, it is index mode and should only clear the corresponding bit. For example, say we have an interrupt pending for GPIOA0, where the following statements are true: set->int_status == 0b01 s->pending == 1 Before it is acknowledged, an interrupt becomes pending for GPIOA1: set->int_status == 0b11 s->pending == 2 A write is issued to acknowledge the interrupt for GPIOA0. This causes the following sequence: reg_value == 0b11 pending == 2 s->pending == 0 set->int_status == 0b00 It should only clear bit 0 in index mode and the correct result should be as following. set->int_status == 0b11 s->pending == 2 pending == 1 s->pending == 1 set->int_status == 0b10 Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Suggested-by: Andrew Jeffery <andrew@codeconstruct.com.au> Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
| * | hw/gpio/aspeed: Support different memory region opsJamin Lin2024-10-242-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It set "aspeed_gpio_ops" struct which containing read and write callbacks to be used when I/O is performed on the GPIO region. Besides, in the previous design of ASPEED SOCs, one register is used for setting one function for 32 GPIO pins. ex: GPIO000 is used for setting data value for GPIO A, B, C and D in AST2600. ex: GPIO004 is used for setting direction for GPIO A, B, C and D in AST2600. However, the register set have a significant change in AST2700. Each GPIO pin has their own control register. In other words, users are able to set one GPIO pin’s direction, interrupt enable, input mask and so on in one register. The aspeed_gpio_read/aspeed_gpio_write callback functions are not compatible AST2700. Introduce a new "const MemoryRegionOps *" attribute in AspeedGPIOClass and use it in aspeed_gpio_realize function. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
| * | hw/gpio/aspeed: Support to set the different memory sizeJamin Lin2024-10-242-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the datasheet of ASPEED SOCs, a GPIO controller owns 4KB of register space for AST2700, AST2500, AST2400 and AST1030; owns 2KB of register space for AST2600 1.8v and owns 2KB of register space for AST2600 3.3v. It set the memory region size 2KB by default and it does not compatible register space for AST2700. Introduce a new class attribute to set the GPIO controller memory size for different ASPEED SOCs. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>