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* qapi: Recognize section tags and 'Features:' only after blank lineMarkus Armbruster2024-02-269-12/+32
| | | | | | | | | Putting a blank line before section tags and 'Features:' is good, existing practice. Enforce it. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-ID: <20240216145841.2099240-12-armbru@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
* qapi: Require descriptions and tagged sections to be indentedMarkus Armbruster2024-02-2628-2316/+2318
| | | | | | | | | | | | By convention, we indent the second and subsequent lines of descriptions and tagged sections, except for examples. Turn this into a hard rule, and apply it to examples, too. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-ID: <20240216145841.2099240-11-armbru@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> [Straightforward conflicts in qapi/migration.json resolved]
* qapi: Reject section heading in the middle of a doc commentMarkus Armbruster2024-02-265-4/+13
| | | | | | | | | | | | | | | docs/devel/qapi-code-gen.txt claims "A heading line must be the first line of the documentation comment block" since commit 55ec69f8b16 (docs/devel/qapi-code-gen.txt: Update to new rST backend conventions). Not true, we have code to make it work anywhere in a free-form doc comment: commit dcdc07a97cb (qapi: Make section headings start a new doc comment block). Make it true, for simplicity's sake. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-ID: <20240216145841.2099240-10-armbru@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
* qapi: Rename QAPIDoc.Section.name to .tagMarkus Armbruster2024-02-263-19/+19
| | | | | | | | | | Since the previous commit, QAPIDoc.Section.name is either None (untagged section) or the section's tag string ('Returns', '@name', ...). Rename it to .tag. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-ID: <20240216145841.2099240-9-armbru@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
* qapi: Improve error message for empty doc sectionsMarkus Armbruster2024-02-263-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | Improve the message for an empty tagged section from empty doc section 'Note' to text required after 'Note:' and the message for an empty argument or feature description from empty doc section 'foo' to text required after '@foo:' Improve the error position to refer to the beginning of the empty section instead of its end. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-ID: <20240216145841.2099240-8-armbru@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
* qapi: Improve error position for bogus invalid "Returns" sectionMarkus Armbruster2024-02-262-4/+8
| | | | | | | | | | When something other than a command has a "Returns" section, the error message points to the beginning of the definition comment. Point to the "Returns" section instead. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-ID: <20240216145841.2099240-7-armbru@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
* qapi: Improve error position for bogus argument descriptionsMarkus Armbruster2024-02-268-8/+10
| | | | | | | | | | When documented arguments don't exist, the error message points to the beginning of the definition comment. Point to the first bogus argument description instead. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-ID: <20240216145841.2099240-6-armbru@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
* sphinx/qapidoc: Drop code to generate doc for simple union branchMarkus Armbruster2024-02-261-11/+7
| | | | | | | | | | | | Commit 4e99f4b12c0 (qapi: Drop simple unions) eliminated implicitly defined union branch types, except for the empty object type 'q_empty'. QAPISchemaGenRSTVisitor._nodes_for_members() still has code to generate documentation for implicitly defined union branch types. It does nothing for 'q_empty'. Simplify. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-ID: <20240216145841.2099240-5-armbru@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
* tests/qapi-schema: Cover 'Features:' not followed by descriptionsMarkus Armbruster2024-02-264-0/+30
| | | | | | | | | | A 'Features:' line without any features is useless, but not an error now. However, a later commit will make it one, because that makes rejecting duplicate 'Features:' easier. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-ID: <20240216145841.2099240-4-armbru@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
* tests/qapi-schema: Cover duplicate 'Features:' lineMarkus Armbruster2024-02-264-0/+34
| | | | | | | | | | | | | | We don't actually recognize the second 'Features:' line. Instead, we treat it as an untagged section. If it was followed by feature description, we'd reject that like "description of '@feat2:' follows a section". Less than clear. To be improved shortly. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-ID: <20240216145841.2099240-3-armbru@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
* tests/qapi-schema: Fix test 'QAPI rST doc'Markus Armbruster2024-02-262-16/+15
| | | | | | | | | | | | | | The test compares Sphinx plain-text output against a golden reference. To work on Windows hosts, it filters out carriage returns in both files. Unfortunately, the filter doesn't work: it creates an empty file. Comparing empty files always succeeds. Fix the filter, and update the golden reference to current Sphinx output. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-ID: <20240216145841.2099240-2-armbru@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
* qapi: Misc cleanups to migrate QAPIsHet Gala2024-02-261-6/+7
| | | | | | | | Signed-off-by: Het Gala <het.gala@nutanix.com> Message-ID: <20240216195659.189091-1-het.gala@nutanix.com> Reviewed-by: Peter Xu <peterx@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
* Merge tag 'pull-request-2024-02-23' of https://gitlab.com/thuth/qemu into ↵Peter Maydell2024-02-2416-189/+99
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging * m68k: Fix exception frame format for 68010 * Add cdrom test for LoongArch virt machine * Fix qtests when using --without-default-devices * Enable -Wvla * Windows 32-bit removal * Silence warnings in the test-x86-cpuid-compat qtest # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmXY7MMRHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbWkRg//TCprQ7Gesex/yvMFIZuZk+poEaibxGXU # cWp6hneV8selTzBKzBC3VS1n31shd9astNRE95N2fSIfCV6R22y2tfZF2rSOoeog # bvqX7KoaEnSsrDS054EGAnuvYQpOGLGth/3Mc9Z791r5I1tYZPJocVnAyi/OB+3q # Gr5WzXj6Z/QD7c0f6vZ943wRBO/zc1729KikDUSyfS3Tua+15mAuUIUQdlLNNPct # 6aT5e6c967mAYh93AUevd3hgVYXH2W4fH7s1q2pap2hMBw2a43XvlMKJ9CvXPFPg # eU6knRPES16BSC2TTphNCBQi9n3rQdion01VsoQEetVBfFa4yA1Ys7ofF5vCa2l8 # 5EO5X3VQfZeq0ktmrLM7qAO0OMnolIqbeNS97ggOiyL0Q3YXim6cNWf8+OZbGoFR # OK88ndmzEXrZq+5w4QBDGLHFU3u8ZeWAM6p7Ht/ZN89ndDYT5bGBwkjVRW5hVgck # fmGhgutSqP2/DN5/4nMn8jtmGc65H/rBRilttW8W2JF72rQJYduDnx/A4KUatkHT # tC58NwLarF3kF7cebhWvNQDD74ia/35n+fEAmtIHF42YHE6aifss91QrgT+qGG5+ # GG12JIoFVDCgE1pkNU7GO53Uqo94Ej8TUOxwF9QfftxnqiktMG7Y/KQRcSA5VvHr # laagGgDzHP0= # =1hu9 # -----END PGP SIGNATURE----- # gpg: Signature made Fri 23 Feb 2024 19:06:43 GMT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2024-02-23' of https://gitlab.com/thuth/qemu: target/i386: do not filter processor tracing features except on KVM .gitlab-ci.d/windows.yml: Remove shared-msys2 abstraction .gitlab-ci.d: Drop cross-win32-system job docs: Document that 32-bit Windows is unsupported meson: Enable -Wvla target/ppc/kvm: Replace variable length array in kvmppc_read_hptes() target/ppc/kvm: Replace variable length array in kvmppc_save_htab() tests: skip dbus-display tests that need a console tests/qtest: Fix boot-serial-test when using --without-default-devices tests/cdrom-test: Add cdrom test for LoongArch virt machine target/m68k: Fix exception frame format for 68010 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/i386: do not filter processor tracing features except on KVMPaolo Bonzini2024-02-231-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The processor tracing features in cpu_x86_cpuid() are hardcoded to a set that should be safe on all processor that support PT virtualization. But as an additional check, x86_cpu_filter_features() also checks that the accelerator supports that safe subset, and if not it marks CPUID_7_0_EBX_INTEL_PT as unavailable. This check fails on accelerators other than KVM, but it is actually unnecessary to do it because KVM is the only accelerator that uses the safe subset. Everything else just provides nonzero values for CPUID leaf 0x14 (TCG/HVF because processor tracing is not supported; qtest because nothing is able to read CPUID anyway). Restricting the check to KVM fixes a warning with the qtest accelerator: $ qemu-system-x86_64 -display none -cpu max,mmx=off -accel qtest qemu-system-x86_64: warning: TCG doesn't support requested feature: CPUID.07H:EBX.intel-pt [bit 25] The warning also happens in the test-x86-cpuid-compat qtest. Reported-by: Peter Maydell <peter.maydell@linaro.org> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2096 Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-ID: <20240221162910.101327-1-pbonzini@redhat.com> Fixes: d047402436 ("target/i386: Call accel-agnostic x86_cpu_get_supported_cpuid()") Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * .gitlab-ci.d/windows.yml: Remove shared-msys2 abstractionPeter Maydell2024-02-231-44/+41
| | | | | | | | | | | | | | | | | | | | | | | | Now we don't build msys2-32bit we don't need the abstraction out of the common msys2 handling from the 32-vs-64-bit specifics. Collapse it down into the msys2-64bit job definition. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: "Daniel P. Berrangé" <berrange@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240222130920.362517-4-peter.maydell@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * .gitlab-ci.d: Drop cross-win32-system jobPeter Maydell2024-02-234-135/+0
| | | | | | | | | | | | | | | | | | | | | | | | We don't support 32-bit Windows any more, so we don't need to defend it with this CI job. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: "Daniel P. Berrangé" <berrange@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-ID: <20240222130920.362517-3-peter.maydell@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * docs: Document that 32-bit Windows is unsupportedPeter Maydell2024-02-232-0/+17
| | | | | | | | | | | | | | | | | | Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: "Daniel P. Berrangé" <berrange@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-ID: <20240222130920.362517-2-peter.maydell@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * meson: Enable -WvlaPeter Maydell2024-02-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | QEMU has historically used variable length arrays only very rarely. Variable length arrays are a potential security issue where an on-stack dynamic allocation isn't correctly size-checked, especially when the size comes from the guest. (An example problem of this kind from the past is CVE-2021-3527). Forbidding them entirely is a defensive measure against further bugs of this kind. Enable -Wvla to prevent any new uses from sneaking into the codebase. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-ID: <20240125173211.1786196-3-peter.maydell@linaro.org> [thuth: rebased to current master branch] Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240221162636.173136-4-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * target/ppc/kvm: Replace variable length array in kvmppc_read_hptes()Thomas Huth2024-02-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | HPTES_PER_GROUP is 8 and HASH_PTE_SIZE_64 is 16, so we don't waste too many bytes by always allocating the maximum amount of bytes on the stack here to get rid of the variable length array. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Message-ID: <20240221162636.173136-3-thuth@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * target/ppc/kvm: Replace variable length array in kvmppc_save_htab()Thomas Huth2024-02-231-1/+1
| | | | | | | | | | | | | | | | | | | | To be able to compile QEMU with -Wvla (to prevent potential security issues), we need to get rid of the variable length array in the kvmppc_save_htab() function. Replace it with a heap allocation instead. Message-ID: <20240221162636.173136-2-thuth@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * tests: skip dbus-display tests that need a consoleMarc-André Lureau2024-02-231-2/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When compiling with "configure --without-default-devices", the dbus-display-test fails since it implicitly assumes that the machine comes with a default console. There doesn't seem to be an easy way to figure this during build time, so skip the tests requiring the Console interface at runtime. Reported-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-ID: <20240221073759.171443-1-marcandre.lureau@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * tests/qtest: Fix boot-serial-test when using --without-default-devicesThomas Huth2024-02-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | If "configure" has been run with "--without-default-devices", there is no e1000 device in the binaries, so the boot-serial-test currently fails in that case since it tries to use the e1000 with the sam460ex machine. Since we're testing the serial output here, and not the NIC, let's simply switch to the "pci-bridge" device here instead, which should always be there for PCI-based machines like the sam460ex. Message-ID: <20240219111030.384158-1-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * tests/cdrom-test: Add cdrom test for LoongArch virt machineBibo Mao2024-02-231-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The cdrom test skips to execute on LoongArch system with command "make check", this patch enables cdrom test for LoongArch virt machine platform. With this patch, cdrom test passes to run on LoongArch virt machine type. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Message-ID: <20240217100230.134042-1-maobibo@loongson.cn> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
| * target/m68k: Fix exception frame format for 68010Daniel Palmer2024-02-233-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From the 68010 a word with the frame format and exception vector are placed on the stack before the PC and SR. M68K_FEATURE_QUAD_MULDIV is currently checked to workout if to do this or not for the configured CPU but that flag isn't set for 68010 so currently the exception stack when 68010 is configured is incorrect. It seems like checking M68K_FEATURE_MOVEFROMSR_PRIV would do but adding a new flag that shows exactly what is going on here is maybe clearer. Add a new flag for the behaviour, M68K_FEATURE_EXCEPTION_FORMAT_VEC, and set it for 68010 and above, and then use it to control if the format and vector word are pushed/pop during exception entry/exit. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2164 Signed-off-by: Daniel Palmer <daniel@0x0f.com> Message-ID: <20240115101643.2165387-1-daniel@0x0f.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
* | Merge tag 'pull-ppc-for-9.0-20240224' of https://gitlab.com/npiggin/qemu ↵Peter Maydell2024-02-2354-352/+3318
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging * Avocado tests for ppc64 to boot FreeBSD, run guests with emulated or nested hypervisor facilities, among other things. * Update ppc64 CPU defaults to Power10. * Add a new powernv10-rainier machine to better capture differences between the different Power10 systems. * Implement more device models for powernv. * 4xx TLB flushing performance and correctness improvements. * Correct gdb implementation to access some important SPRs. * Misc cleanups and bug fixes. # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEETkN92lZhb0MpsKeVZ7MCdqhiHK4FAmXYuX0ACgkQZ7MCdqhi # HK6t1Q/9Hxw+MseFUa/6sbWX6mhv/8emrFFOwI9qxapxDoMyic+SjIhR5PPCYh6t # TLE1vJiV54XYB3286hz3eQfDxfHNjkgsF7PYp9SEd6D1rMT9ESxeu5NkifenEfP0 # UoTFXJyfg/OF1h+JQRrVv1m+D4mqGGNCQB4QiU3DYTmRhrhp7H3mKfUX/KvkEwiX # EqZibmrqb9SVSjT66LBQzY328mEH4nipF33QtYKfYjb6kMe8ACSznL2VYP0NmacU # T+3eHJeLtOLeRlHwYfADx2ekRHlsJuE9/fMMHJHb2qxJkHSQ7yGBqSLESAe6kNP8 # TnKJ9x4433K7IjFqaoiDONrMVJbVZDh/DUh1WWdY14iiUOYEy7uLkLtmThmNSyUB # 622Rd5Ch09JWzA/tg1aC9mR2f9boe9/Z1VeHeN8j+sVj1e6MEh8un8SER3X+9TDz # myGLsmPXQnu1yjebycuE+9RAPbR9npOAkQpE5ZfDwjUM7y4s4jzZUKUoIhtCXeEF # eIykVnaGbPlEBGpuf+E+w2ZxhZUIfxRUhuunK8Ib4TE8khJn/Ir4BxoLweSnqtKM # O4xiFvHm72RUVK232Kox5HWbFJ8XSLBUb3ABNGbXXynzAMD+THB4ImFBbysOmIkR # xcF1tWQ+xoMMcCxbx73b0PhO5AR/PgYc2ctug9rAc9fh4ypJLEs= # =LZzb # -----END PGP SIGNATURE----- # gpg: Signature made Fri 23 Feb 2024 15:27:57 GMT # gpg: using RSA key 4E437DDA56616F4329B0A79567B30276A8621CAE # gpg: Good signature from "Nicholas Piggin <npiggin@gmail.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 4E43 7DDA 5661 6F43 29B0 A795 67B3 0276 A862 1CAE * tag 'pull-ppc-for-9.0-20240224' of https://gitlab.com/npiggin/qemu: (47 commits) target/ppc: optimise ppcemb_tlb_t flushing target/ppc: 440 optimise tlbwe TLB flushing target/ppc: 4xx optimise tlbwe_lo TLB flushing target/ppc: 4xx don't flush TLB for a newly written software TLB entry target/ppc: Factor out 4xx ppcemb_tlb_t flushing target/ppc: Fix 440 tlbwe TLB invalidation gaps target/ppc: Add SMT support to time facilities target/ppc: Implement core timebase state machine and TFMR ppc/pnv: Implement the ChipTOD to Core transfer ppc/pnv: Wire ChipTOD model to powernv9 and powernv10 machines ppc/pnv: Add POWER9/10 chiptod model target/ppc: Fix move-to timebase SPR access permissions target/ppc: Improve timebase register defines naming target/ppc: Rename TBL to TB on 64-bit target/ppc: Update gdbstub to read SPR's CFAR, DEC, HDEC, TB-L/U hw/ppc: N1 chiplet wiring hw/ppc: Add N1 chiplet model hw/ppc: Add pnv nest pervasive common chiplet model ppc/pnv: Test pnv i2c master and connected devices ppc/pnv: Add a pca9554 I2C device to powernv10-rainier ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/ppc: optimise ppcemb_tlb_t flushingNicholas Piggin2024-02-231-6/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Filter TLB flushing by PID and mmuidx. Zoltan reports that, together with the previous TLB flush changes, performance of a sam460ex machine running 'lame' to convert a wav to mp3 is improved nearly 10%: CPU time TLB partial flushes TLB elided flushes Before 37s 508238 7680722 After 34s 73 1143 Tested-by: BALATON Zoltan <balaton@eik.bme.hu> Acked-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
| * target/ppc: 440 optimise tlbwe TLB flushingNicholas Piggin2024-02-231-1/+1
| | | | | | | | | | | | | | | | | | | | Have 440 tlbwe flush only the range corresponding to the addresses covered by the software TLB entry being modified rather than the entire TLB. This matches what 4xx does. Tested-by: BALATON Zoltan <balaton@eik.bme.hu> Acked-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
| * target/ppc: 4xx optimise tlbwe_lo TLB flushingNicholas Piggin2024-02-231-2/+8
| | | | | | | | | | | | | | | | | | Rather than tlbwe_lo always flushing all TCG TLBs, have it flush just those corresponding to the old software TLB, and only if it was valid. Tested-by: BALATON Zoltan <balaton@eik.bme.hu> Acked-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
| * target/ppc: 4xx don't flush TLB for a newly written software TLB entryNicholas Piggin2024-02-231-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BookE software TLB is implemented by flushing old translations from the relevant TCG TLB whenever software TLB entries change. This means a new software TLB entry should not have any corresponding cached TCG TLB translations, so there is nothing to flush. The exception is multiple software TLBs that cover the same address and address space, but that is a programming error and results in undefined behaviour, and flushing does not give an obviously better outcome in that case either. Remove the unnecessary flush of a newly written software TLB entry. Tested-by: BALATON Zoltan <balaton@eik.bme.hu> Acked-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
| * target/ppc: Factor out 4xx ppcemb_tlb_t flushingNicholas Piggin2024-02-231-11/+13
| | | | | | | | | | | | | | | | | | Flushing the TCG TLB pages that cache a software TLB is a common operation, factor it into its own function. Tested-by: BALATON Zoltan <balaton@eik.bme.hu> Acked-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
| * target/ppc: Fix 440 tlbwe TLB invalidation gapsNicholas Piggin2024-02-231-25/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 440 tlbwe (write entry) instruction misses several cases that must flush the TCG TLB: - If the new size is smaller than the existing size, the EA no longer covered should be flushed. This looks like an inverted inequality test. - If the TLB PID changes. - If the TLB attr bit 0 (translation address space) changes. - If low prot (access control) bits change. Fix this by removing tricks to avoid TLB flushes, and just invalidate the TLB if any valid entry is being changed, similarly to 4xx. Optimisations will be introduced in subsequent changes. Tested-by: BALATON Zoltan <balaton@eik.bme.hu> Acked-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
| * target/ppc: Add SMT support to time facilitiesNicholas Piggin2024-02-232-11/+136
| | | | | | | | | | | | | | | | | | | | | | | | | | The TB, VTB, PURR, HDEC SPRs are per-LPAR registers, and the TFMR is a per-core register. Add the necessary SMT synchronisation and value sharing. The TFMR can only drive the timebase state machine via thread 0 of the core, which is almost certainly not right, but it is enough for skiboot and certain other proprietary firmware. Acked-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
| * target/ppc: Implement core timebase state machine and TFMRNicholas Piggin2024-02-232-3/+243
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This implements the core timebase state machine, which is the core side of the time-of-day system in POWER processors. This facility is operated by control fields in the TFMR register, which also contains status fields. The core timebase interacts with the chiptod hardware, primarily to receive TOD updates, to synchronise timebase with other cores. This model does not actually update TB values with TOD or updates received from the chiptod, as timebases are always synchronised. It does step through the states required to perform the update. There are several asynchronous state transitions. These are modelled using using mfTFMR to drive state changes, because it is expected that firmware poll the register to wait for those states. This is good enough to test basic firmware behaviour without adding real timers. The values chosen are arbitrary. Acked-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
| * ppc/pnv: Implement the ChipTOD to Core transferNicholas Piggin2024-02-235-0/+166
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | One of the functions of the ChipTOD is to transfer TOD to the Core (aka PC - Pervasive Core) timebase facility. The ChipTOD can be programmed with a target address to send the TOD value to. The hardware implementation seems to perform this by sending the TOD value to a SCOM address. This implementation grabs the core directly and manipulates the timebase facility state in the core. This is a hack, but it works enough for now. A better implementation would implement the transfer to the PnvCore xscom register and drive the timebase state machine from there. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
| * ppc/pnv: Wire ChipTOD model to powernv9 and powernv10 machinesNicholas Piggin2024-02-232-0/+33
| | | | | | | | | | | | | | | | Wire the ChipTOD model to powernv9 and powernv10 machines. Suggested-by-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
| * ppc/pnv: Add POWER9/10 chiptod modelNicholas Piggin2024-02-235-0/+517
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ChipTOD (for Time-Of-Day) is a chip pervasive facility in IBM POWER (powernv) processors that keeps a time of day clock. In particular for this model are facilities that initialise and start the time of day clock, and that synchronise that clock to cores on the chip, and to other chips. In this way, all cores on all chips can synchronise timebase (TB). This model implements functionality sufficient to run the skiboot chiptod synchronisation procedure (with the following core timebase state machine implementation). It does not modify the TB in the cores where the real hardware would, because the QEMU ppc timebase implementation is always synchronised acros all cores. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
| * target/ppc: Fix move-to timebase SPR access permissionsNicholas Piggin2024-02-231-8/+23
| | | | | | | | | | | | | | | | The move-to timebase registers TBU and TBL can not be read, and they can not be written in supervisor mode on hypervisor-capable CPUs. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
| * target/ppc: Improve timebase register defines namingNicholas Piggin2024-02-232-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The timebase in ppc started out with the mftb instruction which is like mfspr but addressed timebase registers (TBRs) rather than SPRs. These instructions could be used to read TB and TBU at 268 and 269. Timebase could be written via the TBL and TBU SPRs at 284 and 285. The ISA changed around v2.03 to bring TB and TBU reads into the SPR space at 268 and 269 (access via mftb TBR-space is still supported but will be phased out). Later, VTB was added which is an entirely different register. The SPR number defines in QEMU are understandably inconsistently named. Change SPR 268, 269, 284, 285 to TBL, TBU, WR_TBL, WR_TBU, respectively. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
| * target/ppc: Rename TBL to TB on 64-bitNicholas Piggin2024-02-232-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | From the earliest PowerPC ISA, TBR (later SPR) 268 has been called TB and accessed with mftb instruction. The problem is that TB is the name of the 64-bit register, and 32-bit implementations can only read the lower half with one instruction, so 268 has also been called TBL and it does only read TBL on 32-bit. Change SPR 268 to be called TB on 64-bit implementations. Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
| * target/ppc: Update gdbstub to read SPR's CFAR, DEC, HDEC, TB-L/USaif Abrar2024-02-231-2/+38
| | | | | | | | | | | | | | | | | | | | SPR's CFAR, DEC, HDEC, TB-L/U are not implemented as part of CPUPPCState. Hence, gdbstub is not able to access them using (CPUPPCState *)env->spr[] array. Update gdb_get_spr_reg() method to handle these SPR's specifically. Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Saif Abrar <saif.abrar@linux.vnet.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
| * hw/ppc: N1 chiplet wiringChalapathi V2024-02-232-0/+17
| | | | | | | | | | | | | | | | This part of the patchset connects the nest1 chiplet model to p10 chip. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
| * hw/ppc: Add N1 chiplet modelChalapathi V2024-02-234-0/+212
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The N1 chiplet handle the high speed i/o traffic over PCIe and others. The N1 chiplet consists of PowerBus Fabric controller, nest Memory Management Unit, chiplet control unit and more. This commit creates a N1 chiplet model and initialize and realize the pervasive chiplet model where chiplet control registers are implemented. This commit also implement the read/write method for the powerbus scom registers Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
| * hw/ppc: Add pnv nest pervasive common chiplet modelChalapathi V2024-02-234-0/+244
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A POWER10 chip is divided into logical units called chiplets. Chiplets are broadly divided into "core chiplets" (with the processor cores) and "nest chiplets" (with everything else). Each chiplet has an attachment to the pervasive bus (PIB) and with chiplet-specific registers. All nest chiplets have a common basic set of registers and This model will provide the registers functionality for common registers of nest chiplet (Pervasive Chiplet, PB Chiplet, PCI Chiplets, MC Chiplet, PAU Chiplets) This commit implement the read/write functions of chiplet control registers. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
| * ppc/pnv: Test pnv i2c master and connected devicesGlenn Miles2024-02-236-190/+717
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tests the following for both P9 and P10: - I2C master POR status - I2C master status after immediate reset Tests the following for powernv10-ranier only: - Config pca9552 hotplug device pins as inputs then Read the INPUT0/1 registers to verify all pins are high - Connected GPIO pin tests of P10 PCA9552 device. Tests output of pins 0-4 affect input of pins 5-9 respectively. - PCA9554 GPIO pins test. Tests input and ouput functionality. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
| * ppc/pnv: Add a pca9554 I2C device to powernv10-rainierGlenn Miles2024-02-234-0/+12
| | | | | | | | | | | | | | | | | | | | | | For powernv10-rainier, the Power Hypervisor code expects to see a pca9554 device connected to the 3rd PNV I2C engine on port 1 at I2C address 0x25 (or left-justified address of 0x4A). This is used by the hypervisor code to detect if a "Cable Card" is present. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
| * misc: Add a pca9554 GPIO device modelGlenn Miles2024-02-234-2/+391
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Specs are available here: https://www.nxp.com/docs/en/data-sheet/PCA9554_9554A.pdf This is a simple model supporting the basic registers for GPIO mode. The device also supports an interrupt output line but the model does not yet support this. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
| * ppc/pnv: Use resettable interface to reset child I2C busesGlenn Miles2024-02-231-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The QEMU I2C buses and devices use the resettable interface for resetting while the PNV I2C controller and parent buses and devices have not yet transitioned to this new interface and use the old reset strategy. This was preventing the I2C buses and devices wired to the PNV I2C controller from being reset. The short term fix for this is to have the PNV I2C Controller's reset function explicitly call the resettable interface function, bus_cold_reset(), on all child I2C buses. The long term fix should be to transition all PNV parent devices and buses to use the resettable interface so that all child buses and devices are automatically reset. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
| * ppc/pnv: Wire up pca9552 GPIO pins for PCIe hotplug power controlGlenn Miles2024-02-231-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For power10-rainier, a pca9552 device is used for PCIe slot hotplug power control by the Power Hypervisor code. The code expects that some time after it enables power to a PCIe slot by asserting one of the pca9552 GPIO pins 0-4, it should see a "power good" signal asserted on one of pca9552 GPIO pins 5-9. To simulate this behavior, we simply connect the GPIO outputs for pins 0-4 to the GPIO inputs for pins 5-9. Each PCIe slot is assigned 3 GPIO pins on the pca9552 device, for control of up to 5 PCIe slots. The per-slot signal names are: SLOTx_EN.......PHYP uses this as an output to enable slot power. We connect this to the SLOTx_PG pin to simulate a PGOOD signal. SLOTx_PG.......PHYP uses this as in input to detect PGOOD for the slot. For our purposes we just connect this to the SLOTx_EN output. SLOTx_Control..PHYP uses this as an output to prevent a race condition in the real hotplug circuitry, but we can ignore this output for simulation. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
| * ppc/pnv: Add pca9552 to powernv10-rainier for PCIe hotplug power controlGlenn Miles2024-02-233-0/+27
| | | | | | | | | | | | | | | | | | | | | | The Power Hypervisor code expects to see a pca9552 device connected to the 3rd PNV I2C engine on port 1 at I2C address 0x63 (or left- justified address of 0xC6). This is used by hypervisor code to control PCIe slot power during hotplug events. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
| * ppc/pnv: New powernv10-rainier machine typeGlenn Miles2024-02-231-2/+22
| | | | | | | | | | | | | | | | | | Create a new powernv machine type, powernv10-rainier, that will contain rainier-specific devices. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>