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* tcg: Convert divu to TCGOutOpBinaryRichard Henderson2025-04-2823-126/+157
| | | | | | | | For TCI, we're losing type information in the interpreter. Introduce a tci-specific opcode to handle the difference. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Merge INDEX_op_div_{i32,i64}Richard Henderson2025-04-287-24/+22
| | | | | | | | | Rename to INDEX_op_divs to emphasize signed inputs, and mirroring INDEX_op_divu_*. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert div to TCGOutOpBinaryRichard Henderson2025-04-2814-77/+156
| | | | | | | | For TCI, we're losing type information in the interpreter. Introduce a tci-specific opcode to handle the difference. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Merge INDEX_op_mulsh_{i32,i64}Richard Henderson2025-04-285-22/+15
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert mulsh to TCGOutOpBinaryRichard Henderson2025-04-2823-72/+95
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Merge INDEX_op_muluh_{i32,i64}Richard Henderson2025-04-285-25/+22
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert muluh to TCGOutOpBinaryRichard Henderson2025-04-2823-82/+123
| | | | | | | | Remove unreachable mul[su]h_i32 leftovers from commit aeb6326ec5e ("tcg/riscv: Require TCG_TARGET_REG_BITS == 64"). Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Merge INDEX_op_mul_{i32,i64}Richard Henderson2025-04-287-23/+19
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert mul to TCGOutOpBinaryRichard Henderson2025-04-2811-148/+210
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Merge INDEX_op_not_{i32,i64}Richard Henderson2025-04-287-29/+24
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert not to TCGOutOpUnaryRichard Henderson2025-04-2825-103/+119
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Merge INDEX_op_neg_{i32,i64}Richard Henderson2025-04-287-40/+18
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert neg to TCGOutOpUnaryRichard Henderson2025-04-2811-67/+125
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Merge INDEX_op_sub_{i32,i64}Richard Henderson2025-04-287-18/+12
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert sub to TCGOutOpSubtractRichard Henderson2025-04-2815-174/+169
| | | | | | | | | | Create a special subclass for sub, because two backends can support "subtract from immediate". Drop all backend support for an immediate as the second operand, as we transform sub to add during optimize. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/arm: Fix constraints for subRichard Henderson2025-04-282-7/+5
| | | | | | | | | | In 7536b82d288 we lost the rI constraint that allowed the use of RSB to perform reg = imm - reg. At the same time, drop support for reg = reg - imm, which is now transformed generically to addition, and need not be handled by the backend. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Merge INDEX_op_nor_{i32,i64}Richard Henderson2025-04-287-17/+15
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert nor to TCGOutOpBinaryRichard Henderson2025-04-2824-65/+86
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/loongarch64: Do not accept constant argument to norRichard Henderson2025-04-281-8/+2
| | | | | | | | The instruction set does not implement nor with immediate. There is no reason to pretend that we do. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Merge INDEX_op_nand_{i32,i64}Richard Henderson2025-04-287-17/+15
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert nand to TCGOutOpBinaryRichard Henderson2025-04-2824-45/+72
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Merge INDEX_op_eqv_{i32,i64}Richard Henderson2025-04-287-17/+15
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert eqv to TCGOutOpBinaryRichard Henderson2025-04-2827-106/+89
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/optimize: Fold eqv with immediate to xorRichard Henderson2025-04-281-2/+23
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Merge INDEX_op_xor_{i32,i64}Richard Henderson2025-04-288-28/+21
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert xor to TCGOutOpBinaryRichard Henderson2025-04-2811-104/+186
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Merge INDEX_op_orc_{i32,i64}Richard Henderson2025-04-289-19/+17
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert orc to TCGOutOpBinaryRichard Henderson2025-04-2826-118/+104
| | | | | | | | At the same time, drop all backend support for immediate operands, as we now transform orc to or during optimize. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/optimize: Fold orc with immediate to orRichard Henderson2025-04-281-2/+23
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Merge INDEX_op_or_{i32,i64}Richard Henderson2025-04-288-19/+16
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert or to TCGOutOpBinaryRichard Henderson2025-04-2811-94/+186
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Merge INDEX_op_andc_{i32,i64}Richard Henderson2025-04-289-19/+17
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert andc to TCGOutOpBinaryRichard Henderson2025-04-2828-130/+135
| | | | | | | | At the same time, drop all backend support for immediate operands, as we now transform andc to and during optimize. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/optimize: Emit add r,r,-1 in fold_setcond_tst_pow2Richard Henderson2025-04-281-5/+3
| | | | | | | | We canonicalize subtract with constant to add with constant. Fix this missed instance. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/optimize: Fold andc with immediate to andRichard Henderson2025-04-281-0/+19
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Merge INDEX_op_and_{i32,i64}Richard Henderson2025-04-288-45/+24
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert and to TCGOutOpBinaryRichard Henderson2025-04-2811-125/+216
| | | | | | | | | Drop all backend support for an immediate as the first operand. This should never happen in any case, as we swap commutative operands to place immediates as the second operand. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Merge INDEX_op_add_{i32,i64}Richard Henderson2025-04-288-33/+22
| | | | | | | Rely on TCGOP_TYPE instead of opcodes specific to each type. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert add to TCGOutOpBinaryRichard Henderson2025-04-2812-195/+302
| | | | | | | | | Drop all backend support for an immediate as the first operand. This should never happen in any case, as we swap commutative operands to place immediates as the second operand. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Merge INDEX_op_mov_{i32,i64}Richard Henderson2025-04-2817-58/+32
| | | | | | | | | Begin to rely on TCGOp.type to discriminate operations, rather than two different opcodes. Convert mov first. Introduce TCG_OPF_INT in order to keep opcode dumps the same. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Remove INDEX_op_ext{8,16,32}*Richard Henderson2025-04-2827-823/+135
| | | | | | | Use the fully general extract opcodes instead. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Use extract2 for cross-word 64-bit extract on 32-bit hostRichard Henderson2025-04-281-4/+12
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Add all_outop[]Richard Henderson2025-04-281-8/+68
| | | | | | | | | | | Add infrastructure for more consolidated output of opcodes. The base structure allows for constraints to be either static or dynamic, and for the existence of those constraints to replace TCG_TARGET_HAS_* and the bulk of tcg_op_supported. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Add TCGType to tcg_op_insert_{after,before}Richard Henderson2025-04-283-11/+14
| | | | | | | | | | We cannot rely on the value copied from TCGOP_TYPE(op), because the relevant op could be typeless, such as INDEX_op_call. Fixes: fb744ece3a78 ("tcg: Copy TCGOP_TYPE in tcg_op_insert_{after,before}") Suggested-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/optimize: Introduce opt_insert_{before,after}Richard Henderson2025-04-281-9/+21
| | | | | | | | Consolidate the places we call tcg_op_insert_{before,after} within the optimization pass. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/loongarch64: Improve constraints for TCG_CT_CONST_VCMPRichard Henderson2025-04-281-17/+21
| | | | | | | | | | Use the TCGCond given to tcg_target_const_match to exactly match the supported constant. Adjust the code generation to assume this has been done -- recall that encode_*_insn contain assertions that the constants are valid. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/loongarch64: Fix vec_val computation in tcg_target_const_matchRichard Henderson2025-04-281-6/+8
| | | | | | | | Only use vece for a vector constant. This avoids an assertion failure in sextract64 when vece contains garbage. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* Merge tag 'for-upstream' of https://repo.or.cz/qemu/kevin into stagingStefan Hajnoczi2025-04-274-29/+79
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Block layer patches - Discard alignment fixes - Remove unused callback .bdrv_aio_pdiscard() - qemu-img bench: Input validation fix # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEE3D3rFZqa+V09dFb+fwmycsiPL9YFAmgLy7QRHGt3b2xmQHJl # ZGhhdC5jb20ACgkQfwmycsiPL9YB4A//Zsbb+tVsyLBKeffwPpHF/cAzHVH7Q2dV # GC2JJvfrwq0gykfjj+u4akVQnPh49QiQM623PX7O15IikwdLy45ddQcYL1qflYCs # ZGmBOuz/deI74qjl67bZVqIm8WeRhwHkdutfXOL7GRe2IHbceLbwwGUcbCgOVavt # LHu3E2MIbvkLJoHEgg8UbJhZZY9DTLGDaMt00Yhy3UvNHU8UDeIr8o4dxMVv3gOf # +8kIjGQkYNqpWp7aCxy8vofdSFjbBp4lSCK4G83xikUw49qkwWcgZ6jyTzXALg0G # V+nMjH+DnfIRqhi1skFTHQNmFc6upxr7FIOgC+G5amkKLHCPnX9j5/2pBwrk63R7 # kXqzIPfRmfOTnJX+m7a9K/pE6RU9aPfr8mQdokEcQtlJkEjc6QN9HKfy/CLnJ5Id # Le8jQODSZ1zRsP6Z8jyG4unj0AuOucUoXjAKQ5EWK5RoRoLMirxqDEDd9tBjcPYB # JQmB/j7aTrF3aDWBs5ragCQYdcoXJbAbqLAwhaofyVRmVyjYJmWEIkPGGo946GPd # /BFgaUaea4qW5+iIpWFTD9TCQEY/A7RRpT4teu7anZ/hDzLUyXLJU28xYC6LxiDZ # Yoy5M/U6MLvgkBVTNuss4T3CIutBrUI7a/DLuGB+cSM6KkigQvNwLuBqPzTDfEQP # sQJOP4UsX6k= # =8amc # -----END PGP SIGNATURE----- # gpg: Signature made Fri 25 Apr 2025 13:51:48 EDT # gpg: using RSA key DC3DEB159A9AF95D3D7456FE7F09B272C88F2FD6 # gpg: issuer "kwolf@redhat.com" # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" [full] # Primary key fingerprint: DC3D EB15 9A9A F95D 3D74 56FE 7F09 B272 C88F 2FD6 * tag 'for-upstream' of https://repo.or.cz/qemu/kevin: qemu-img: improve queue depth validation in img_bench block: Remove unused callback function *bdrv_aio_pdiscard block/io: skip head/tail requests on EINVAL file-posix: probe discard alignment on Linux block devices Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * qemu-img: improve queue depth validation in img_benchDenis Rastyogin2025-04-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This error was discovered by fuzzing qemu-img. Currently, running `qemu-img bench -d 0` in img_bench is allowed, which is a pointless operation and causes qemu-img to hang. Signed-off-by: Denis Rastyogin <gerben@altlinux.org> Message-ID: <20250327162423.25154-5-gerben@altlinux.org> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
| * block: Remove unused callback function *bdrv_aio_pdiscardSunny Zhu2025-04-252-23/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The bytes type in *bdrv_aio_pdiscard should be int64_t rather than int. There are no drivers implementing the *bdrv_aio_pdiscard() callback, it appears to be an unused function. Therefore, we'll simply remove it instead of fixing it. Additionally, coroutine-based callbacks are preferred. If someone needs to implement bdrv_aio_pdiscard, a coroutine-based version would be straightforward to implement. Signed-off-by: Sunny Zhu <sunnyzhyy@qq.com> Message-ID: <tencent_7140D2E54157D98CF3D9E64B1A007A1A7906@qq.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>