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* hw/xen: Fix errp handling in xen_consoleDavid Woodhouse2025-01-151-13/+21
| | | | | | | | | | | | When attempting to read the 'output' node, interpret any error *other* than ENOENT as a fatal error. For ENOENT, fall back to serial_hd() to find a character device, or create a null device. Do not attempt to prepend to errp when serial_hd() fails; the error isn't relevant (and prior to this change, wasn't set anyway). Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Anthony PERARD <anthony.perard@vates.tech>
* hw/xen: Use xs_node_read() from xenstore_read_str() instead of open-coding itDavid Woodhouse2025-01-151-4/+2
| | | | | | Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Anthony PERARD <anthony.perard@vates.tech> Acked-by: Roger Pau Monné <roger.pau@citrix.com>
* hw/xen: Use xs_node_read() from xen_netdev_get_name()David Woodhouse2025-01-151-7/+6
| | | | | | | | Now that xs_node_read() can construct a node path, no need to open-code it. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Anthony PERARD <anthony.perard@vates.tech> Acked-by: Roger Pau Monné <roger.pau@citrix.com>
* hw/xen: Use xs_node_read() from xen_console_get_name()David Woodhouse2025-01-151-9/+9
| | | | | | | | Now that xs_node_read() can construct a node path, no need to open-code it. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Anthony PERARD <anthony.perard@vates.tech> Acked-by: Roger Pau Monné <roger.pau@citrix.com>
* hw/xen: Use xs_node_read() from xs_node_vscanf()David Woodhouse2025-01-152-10/+6
| | | | | | | | Reduce some duplication. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Anthony PERARD <anthony.perard@vates.tech> Acked-by: Roger Pau Monné <roger.pau@citrix.com>
* xen: do not use '%ms' scanf specifierRoger Pau Monne2025-01-154-5/+19
| | | | | | | | | | | | | | | The 'm' parameter used to request auto-allocation of the destination variable is not supported on FreeBSD, and as such leads to failures to parse. What's more, the current usage of '%ms' with xs_node_scanf() is pointless, as it just leads to a double allocation of the same string. Instead use xs_node_read() to read the whole xenstore node. Fixes: a783f8ad4ec9 ('xen: add a mechanism to automatically create XenDevice-s...') Fixes: 9b7737469080 ('hw/xen: update Xen console to XenDevice model') Signed-off-by: Roger Pau Monné <roger.pau@citrix.com> Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Anthony PERARD <anthony.perard@vates.tech>
* hw/xen: Add xs_node_read() helper functionDavid Woodhouse2025-01-153-0/+32
| | | | | | | | | | | | | This returns the full contents of the node, having created the node path from the printf-style format string provided in its arguments. This will save various callers from having to do so for themselves (and from using xs_node_scanf() with the non-portable %ms format string. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> [remove double newline and constify trace parameters] Signed-off-by: Roger Pau Monné <roger.pau@citrix.com> Reviewed-by: Anthony PERARD <anthony.perard@vates.tech>
* Merge tag 'hw-misc-20250113' of https://github.com/philmd/qemu into stagingStefan Hajnoczi2025-01-1452-311/+559
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Misc HW patches queue - Silent unuseful DTC warnings (Philippe) - Unify QDev hotplug decision logic (Akihiko) - Rework XilinX EthLite RAM buffers (Philippe) - Convert vmcoreinfo to 3-phase reset (Philippe) - Convert HPPA CPUs to 3-phase reset (Helge) - Fix UFS endianness issue (Keoseong) - Introduce pci_set_enabled (Akihiko) - Clarify Enclave and Firecracker relationship (Alexander) - Set SDHCI DMA interrupt status bit in correct place (Bernhard) - Fix leak in cryptodev-vhost-user backend (Gabriel) - Fixes on PCI USB XHCI (Phil) - Convert DPRINTF to trace events (Nikita, Bernhard) - Remove &first_cpu in TriCore machine (Philippe) - Checkpatch style cleanups (Bibo) - MAINTAINERS updates (Marcin, Gustavo, Akihiko) - Add default configuration for b4 tool (Jiaxun) # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmeFTq0ACgkQ4+MsLN6t # wN6F2RAA0hhgXYf1BAn0DQI5O/oOzt6WzkwL/yQhKff1piWMcCZbHCOn8JHETE4R # QTqg+OMGuw4Q55YSwqwHW98JIQI/lRbSUX9Vc3km4QxED5owHiqu9wk//KSLv3TY # y86CRbibb0Uy6vEM4J1WK6ATiLePWZ6qzePQX59f9YEagTLM2XO2DasRu+wGDbt+ # 96fPnT7Tx2Bu5jU8+sZ36mw3wWSJo/pLQBE9siH4N33v2I5ntmMs1Lbe7QscDDsw # 1+OOti3lB4q5chNMYNQyPxvz75QIi9et7wREJM9Vt03OpEpj+vWMGzwZFNLfOmeu # eApgcQP/k6z1+pAGjEo5mwNOZcZtR9I/3Uf/sONvO0N5FlJq9CSOTs7L2EddcFzM # lVDZjwEHIoU1xCohqNy2A0Q1s20dNfBEjPEUCuh+tIvFk9cy1L8uZtBVFNUCb33J # Jq8KAkqXAaVj2tHGa27DwFjSTo4olU/G0WO4AQZNwdxvMQwX88gHOGMJkRmJPRVi # ErKD0/bBfVa6orEAorWYwQSnTP1H/2fGfF6rLtI5GvQtPc/jBG3+KpEOS+vc2nzG # 1fq+Kty8kWsU4Fpw3EUHvflnzG4Ujhuc/nJ+FyQhn89Erb49jxBlu25lQOLVRVa4 # gP+jsgi46+4goYzj1vrpTpBgFPFWKGCl1gGz17ij5WyvVXroRzA= # =+uup # -----END PGP SIGNATURE----- # gpg: Signature made Mon 13 Jan 2025 12:34:37 EST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'hw-misc-20250113' of https://github.com/philmd/qemu: (55 commits) Add a b4 configuration file MAINTAINERS: Update path to coreaudio.m MAINTAINERS: Add me as the maintainer for ivshmem-flat MAINTAINERS: remove myself from sbsa-ref hw/tricore/triboard: Remove unnecessary use of &first_cpu hw/usb/hcd-xhci-pci: Use event ring 0 if mapping unsupported hw/usb/hcd-xhci-pci: Use modulo to select MSI vector as per spec backends/cryptodev-vhost-user: Fix local_error leaks hw/loongarch/virt: Checkpatch cleanup target/hppa: Speed up hppa_is_pa20() target/hppa: Set PC on vCPU reset target/hppa: Only set PSW 'M' bit on reset hw/hppa: Reset vCPUs calling resettable_reset() target/hppa: Convert hppa_cpu_init() to ResetHold handler tests: Add functional tests for HPPA machines tests/qtest/boot-serial-test: Correct HPPA machine name hw/gpio/imx_gpio: Turn DPRINTF() into trace events hw/i2c/imx_i2c: Convert DPRINTF() to trace events hw/char/imx_serial: Turn some DPRINTF() statements into trace events hw/misc/imx6_src: Convert DPRINTF() to trace events ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * Add a b4 configuration fileJiaxun Yang2025-01-131-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | b4 [1] is a convenient tool to manage patch series with mailing list working flow. Add a project default config file to match QEMU's mailing list conventions as well as adopting differences on scripting. Examples of b4: ``` $ b4 prep --check Checking patches using: scripts/checkpatch.pl -q --terse --no-summary --mailback - --- Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> --- Changes in v2: - Add lore masks (philmd) from: https://lore.kernel.org/qemu-devel/20241224135054.10243-1-philmd@linaro.org/ - Link to v1: https://lore.kernel.org/r/20241222-b4-config-v1-1-b3667beb30a4@flygoat.com --- ● cc5a4c890fed: Add a b4 configuration file ● checkpatch.pl: 27: WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? --- Success: 0, Warning: 1, Error: 0 ``` ``` $ b4 prep -c Will collect To: addresses using echo Will collect Cc: addresses using get_maintainer.pl Collecting To/Cc addresses + To: qemu-devel@nongnu.org --- You can trim/expand this list with: b4 prep --edit-cover Invoking git-filter-repo to update the cover letter. New history written in 0.02 seconds... Completely finished after 0.06 seconds ``` [1]: https://b4.docs.kernel.org/ Co-developed-by: Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-ID: <20250102-b4-config-v2-1-cc7299e399bb@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * MAINTAINERS: Update path to coreaudio.mAkihiko Odaki2025-01-131-2/+2
| | | | | | | | | | | | | | | | | | | | | | Commit 8b46d7e2dc8e ("audio: Rename coreaudio extension to use Objective-C compiler") renamed coreaudio.c to coreaudio.m. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250111-maintainers-v1-1-faebe6ef0fec@daynix.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * MAINTAINERS: Add me as the maintainer for ivshmem-flatGustavo Romero2025-01-131-0/+7
| | | | | | | | | | | | | | | | | | Add me as the maintainer for the ivshmem-flat device. Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250107015639.27648-1-gustavo.romero@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * MAINTAINERS: remove myself from sbsa-refMarcin Juszkiewicz2025-01-131-1/+0
| | | | | | | | | | | | | | | | | | | | | | I am ending my time with Linaro and do not have plans to continue working on SBSA Reference Platform anymore. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@oss.qualcomm.com> Message-ID: <20241218123055.11220-1-marcin.juszkiewicz@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * hw/tricore/triboard: Remove unnecessary use of &first_cpuPhilippe Mathieu-Daudé2025-01-131-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | triboard_machine_init() has access to the single CPU via: TriBoardMachineState { TC27XSoCState { TriCoreCPU cpu; ... } tc27x_soc; } ms; Pass it as argument to tricore_load_kernel() so we can remove the &first_cpu global use. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20250110180909.83165-1-philmd@linaro.org>
| * hw/usb/hcd-xhci-pci: Use event ring 0 if mapping unsupportedPhil Dennis-Jordan2025-01-131-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The XHCI specification, section 4.17.1 specifies that "If the Number of Interrupters (MaxIntrs) field is greater than 1, then Interrupter Mapping shall be supported." and "If Interrupter Mapping is not supported, the Interrupter Target field shall be ignored by the xHC and all Events targeted at Interrupter 0." QEMU's XHCI device has so far not specially addressed this case, so we add a check to xhci_event() to redirect to event ring and interrupt 0 if mapping is disabled. Signed-off-by: Phil Dennis-Jordan <phil@philjordan.eu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20241227121336.25838-4-phil@philjordan.eu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * hw/usb/hcd-xhci-pci: Use modulo to select MSI vector as per specPhil Dennis-Jordan2025-01-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | QEMU would crash with a failed assertion if the XHCI controller attempted to raise the interrupt on an interrupter corresponding to a MSI vector with a higher index than the highest configured for the device by the guest driver. This behaviour is correct on the MSI/PCI side: per PCI 3.0 spec, devices must ensure they do not send MSI notifications for vectors beyond the range of those allocated by the system/driver software. Unlike MSI-X, there is no generic way for handling aliasing in the case of fewer allocated vectors than requested, so the specifics are up to device implementors. (Section 6.8.3.4. "Sending Messages") It turns out the XHCI spec (Implementation Note in section 4.17, "Interrupters") requires that the host controller signal the MSI vector with the number computed by taking the interrupter number modulo the number of enabled MSI vectors. This change introduces that modulo calculation, fixing the failed assertion. This makes the device work correctly in MSI mode with macOS's XHCI driver, which only allocates a single vector. Signed-off-by: Phil Dennis-Jordan <phil@philjordan.eu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250112210056.16658-2-phil@philjordan.eu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * backends/cryptodev-vhost-user: Fix local_error leaksGabriel Barrantes2025-01-131-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | Do not propagate error to the upper, directly output the error to avoid leaks. Fixes: 2fda101de07 ("virtio-crypto: Support asynchronous mode") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2714 Signed-off-by: Gabriel Barrantes <gabriel.barrantes.dev@outlook.com> Reviewed-by: zhenwei pi <pizhenwei@bytedance.com> Message-Id: <DM8PR13MB50781054A4FDACE6F4FB6469B30F2@DM8PR13MB5078.namprd13.prod.outlook.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * hw/loongarch/virt: Checkpatch cleanupBibo Mao2025-01-133-6/+9
| | | | | | | | | | | | | | | | | | | | Code cleanup with directory hw/loongarch/, removing errors from command "scripts/checkpatch.pl hw/loongarch/*" Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250103064514.2660438-1-maobibo@loongson.cn> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * target/hppa: Speed up hppa_is_pa20()Helge Deller2025-01-132-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | Although the hppa_is_pa20() helper is costly due to string comparisons in object_dynamic_cast(), it is called quite often during memory lookups and at each start of a block of instruction translations. Speed hppa_is_pa20() up by calling object_dynamic_cast() only once at CPU creation and store the result in the is_pa20 of struct CPUArchState. Signed-off-by: Helge Deller <deller@gmx.de> Co-developed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20241231190620.24442-7-philmd@linaro.org>
| * target/hppa: Set PC on vCPU resetHelge Deller2025-01-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On reset: "The CPU begins fetching instructions from address 0xf0000004. This address is in PDC space." Switch vCPUs to 32-bit mode (PSW_W bit is not set) and start execution at address 0xf0000004. Signed-off-by: Helge Deller <deller@gmx.de> Co-developed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20241231190620.24442-6-philmd@linaro.org>
| * target/hppa: Only set PSW 'M' bit on resetPhilippe Mathieu-Daudé2025-01-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On reset: "All PSW bits except the M bit is reset. The M bit is set." Commit 1a19da0da44 ("target/hppa: Fill in hppa_cpu_do_interrupt / hppa_cpu_exec_interrupt") inadvertently set the W bit at RESET, remove it and set the M bit. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Helge Deller <deller@gmx.de> Message-Id: <20241231190620.24442-5-philmd@linaro.org>
| * hw/hppa: Reset vCPUs calling resettable_reset()Helge Deller2025-01-132-3/+4
| | | | | | | | | | | | | | | | | | | | | | Rather than manually (and incompletely) resetting vCPUs, call resettable_reset() which will fully reset the vCPUs. Remove redundant assignations. Signed-off-by: Helge Deller <deller@gmx.de> Co-developed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20241231190620.24442-4-philmd@linaro.org>
| * target/hppa: Convert hppa_cpu_init() to ResetHold handlerHelge Deller2025-01-132-2/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | hppa_cpu_initfn() is called once when a HPPA CPU instance is initialized, but it sets fields which should be set each time a CPU resets. Rename it as a reset handler, having it matching the ResettablePhases::hold() signature, and register it as ResettableClass handler. Since on reset the CPU registers and TLB entries are expected to be zero, add a memset() call clearing CPUHPPAState up to the &end_reset_fields marker. Signed-off-by: Helge Deller <deller@gmx.de> Co-developed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20241231190620.24442-3-philmd@linaro.org>
| * tests: Add functional tests for HPPA machinesPhilippe Mathieu-Daudé2025-01-135-3/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add quick firmware boot tests (less than 1sec) for the B160L (32-bit) and C3700 (64-bit) HPPA machines: $ make check-functional-hppa ... 4/4 qemu:func-quick+func-hppa / func-hppa-hppa_seabios OK 0.22s 2 subtests passed Remove the duplicated B160L test in qtest/boot-serial-test.c. Suggested-by: Helge Deller <deller@gmx.de> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Helge Deller <deller@gmx.de> Tested-by: Helge Deller <deller@gmx.de> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250102100340.43014-3-philmd@linaro.org>
| * tests/qtest/boot-serial-test: Correct HPPA machine namePhilippe Mathieu-Daudé2025-01-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 7df6f751176 ("hw/hppa: Split out machine creation") renamed the 'hppa' machine as 'B160L', but forgot to update the boot serial test, which ended being skipped. Cc: qemu-stable@nongnu.org Fixes: 7df6f751176 ("hw/hppa: Split out machine creation") Reported-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20250102100340.43014-2-philmd@linaro.org>
| * hw/gpio/imx_gpio: Turn DPRINTF() into trace eventsBernhard Beschow2025-01-132-11/+12
| | | | | | | | | | | | | | | | | | | | While at it add a trace event for input GPIO events. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-ID: <20250111183711.2338-14-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * hw/i2c/imx_i2c: Convert DPRINTF() to trace eventsBernhard Beschow2025-01-132-16/+10
| | | | | | | | | | | | | | | | | | | | | | Also print the QOM canonical path when tracing which allows for distinguishing the many instances a typical i.MX SoC has. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-ID: <20250111183711.2338-12-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * hw/char/imx_serial: Turn some DPRINTF() statements into trace eventsBernhard Beschow2025-01-132-19/+44
| | | | | | | | | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-ID: <20250111183711.2338-9-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * hw/misc/imx6_src: Convert DPRINTF() to trace eventsBernhard Beschow2025-01-132-18/+11
| | | | | | | | | | | | | | | | Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250108092538.11474-14-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * tests/qtest/libqos: Reuse TYPE_IMX_I2C defineBernhard Beschow2025-01-132-4/+5
| | | | | | | | | | | | | | | | | | Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Fabiano Rosas <farosas@suse.de> Message-ID: <20250108092538.11474-12-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * hw/timer/imx_gpt: Remove unused defineBernhard Beschow2025-01-131-4/+0
| | | | | | | | | | | | | | Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250108092538.11474-11-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * hw/char/stm32f2xx_usart: replace print with traceNikita Shubin2025-01-132-26/+29
| | | | | | | | | | | | | | | | | | | | Drop debug printing macros and replace them with according trace functions. Signed-off-by: Nikita Shubin <n.shubin@yadro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241220111756.16511-1-nikita.shubin@maquefel.me> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * hw/sd/sdhci: Factor sdhci_sdma_transfer() outPhilippe Mathieu-Daudé2025-01-131-11/+11
| | | | | | | | | | | | | | | | | | | | Factor sdhci_sdma_transfer() out of sdhci_data_transfer(). Re-use it in sdhci_write(), so we don't try to run multi block transfer for a single block. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Bernhard Beschow <shentey@gmail.com> Message-Id: <20250109122029.22780-1-philmd@linaro.org>
| * hw/sd/sdhci: Set SDHC_NIS_DMA bit when appropriateBernhard Beschow2025-01-131-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | In U-Boot, the fsl_esdhc[_imx] driver waits for both "transmit completed" and "DMA" bits in esdhc_send_cmd_common() by means of DATA_COMPLETE constant. QEMU currently misses to set the DMA bit which causes the driver to loop forever. Fix that by setting the DMA bit if enabled when doing DMA block transfers. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250108092538.11474-2-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * hw/ufs: Adjust value to match CPU's endian formatKeoseong Park2025-01-132-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In ufs_write_attr_value(), the value parameter is handled in the CPU's endian format but provided in big-endian format by the caller. Thus, it is converted to the CPU's endian format. The related test code is also fixed to reflect this change. Fixes: 7c85332a2b3e ("hw/ufs: minor bug fixes related to ufs-test") Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Keoseong Park <keosung.park@samsung.com> Reviewed-by: Jeuk Kim <jeuk20.kim@samsung.com> Message-ID: <20250107084356epcms2p2af4d86432174d76ea57336933e46b4c3@epcms2p2> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * hw/pci: Rename has_power to enabledAkihiko Odaki2025-01-134-9/+15
| | | | | | | | | | | | | | | | | | | | The renamed state will not only represent powering state of PFs, but also represent SR-IOV VF enablement in the future. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250109-reuse-v19-1-f541e82ca5f7@daynix.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * hw/misc/vmcoreinfo: Convert to three-phase reset interfacePhilippe Mathieu-Daudé2025-01-131-3/+5
| | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20241219153857.57450-6-philmd@linaro.org>
| * hw/misc/vmcoreinfo: Rename VMCOREINFO_DEVICE -> TYPE_VMCOREINFOPhilippe Mathieu-Daudé2025-01-132-7/+6
| | | | | | | | | | | | | | | | | | | | Follow the assumed QOM type definition style, prefixing with 'TYPE_', and dropping the '_DEVICE' suffix which doesn't add any value. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20250102132624.53443-1-philmd@linaro.org>
| * docs/nitro-enclave: Clarify Enclave and Firecracker relationshipAlexander Graf2025-01-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The documentation says that Nitro Enclaves are based on Firecracker. AWS has never made that statement. This patch nudges the wording to instead say it "looks like a Firecracker microvm". Signed-off-by: Alexander Graf <graf@amazon.com> Reviewed-by: Dorjoy Chowdhury <dorjoychy111@gmail.com> Message-ID: <20241211222512.95660-1-graf@amazon.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * hw/net/xilinx_ethlite: Map RESERVED I/O as unimplementedPhilippe Mathieu-Daudé2025-01-131-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to track access to reserved I/O space, use yet another UnimplementedDevice covering the whole device memory range. Mapped with lower priority (-1). The memory flat view becomes: (qemu) info mtree -f FlatView #0 Root memory region: system 0000000081000000-00000000810007e3 (prio 0, ram): ethlite.tx[0]buf 00000000810007e4-00000000810007f3 (prio 0, i/o): ethlite.mdio 00000000810007f4-00000000810007ff (prio 0, i/o): ethlite.tx[0]io 0000000081000800-0000000081000fe3 (prio 0, ram): ethlite.tx[1]buf 0000000081000fe4-0000000081000ff3 (prio -1, i/o): ethlite.reserved @0000000000000fe4 0000000081000ff4-0000000081000fff (prio 0, i/o): ethlite.tx[1]io 0000000081001000-00000000810017e3 (prio 0, ram): ethlite.rx[0]buf 00000000810017e4-00000000810017fb (prio -1, i/o): ethlite.reserved @00000000000017e4 00000000810017fc-00000000810017ff (prio 0, i/o): ethlite.rx[0]io 0000000081001800-0000000081001fe3 (prio 0, ram): ethlite.rx[1]buf 0000000081001fe4-0000000081001ffb (prio -1, i/o): ethlite.reserved @0000000000001fe4 0000000081001ffc-0000000081001fff (prio 0, i/o): ethlite.rx[1]io Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20241114210010.34502-20-philmd@linaro.org>
| * hw/net/xilinx_ethlite: Rename 'mmio' MR as 'container'Philippe Mathieu-Daudé2025-01-131-8/+8
| | | | | | | | | | | | | | | | | | | | Having all its address range mapped by subregions, s->mmio MemoryRegion effectively became a container. Rename it as 'container' for clarity. Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20241112181044.92193-21-philmd@linaro.org>
| * hw/net/xilinx_ethlite: Map the RAM buffer as RAM memory regionPhilippe Mathieu-Daudé2025-01-131-64/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than using I/O registers for RAM buffer, having to swap endianness back and forth (because the core memory layer automatically swaps endiannes for us), declare the buffers as RAM regions. The "xlnx.xps-ethernetlite" MR doesn't have any more I/O regions. Remove the now unused s->regs[] array. The memory flat view becomes: FlatView #0 Root memory region: system 0000000081000000-00000000810007e3 (prio 0, ram): ethlite.tx[0]buf 00000000810007e4-00000000810007f3 (prio 0, i/o): ethlite.mdio 00000000810007f4-00000000810007ff (prio 0, i/o): ethlite.tx[0]io 0000000081000800-0000000081000fe3 (prio 0, ram): ethlite.tx[1]buf 0000000081000ff4-0000000081000fff (prio 0, i/o): ethlite.tx[1]io 0000000081001000-00000000810017e3 (prio 0, ram): ethlite.rx[0]buf 00000000810017fc-00000000810017ff (prio 0, i/o): ethlite.rx[0]io 0000000081001800-0000000081001fe3 (prio 0, ram): ethlite.rx[1]buf 0000000081001ffc-0000000081001fff (prio 0, i/o): ethlite.rx[1]io Reported-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20241114210010.34502-18-philmd@linaro.org>
| * hw/net/xilinx_ethlite: Map TX_CTRL as MMIOPhilippe Mathieu-Daudé2025-01-131-30/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add TX_CTRL to the TX registers MMIO region. The memory flat view becomes: (qemu) info mtree -f FlatView #0 Root memory region: system 0000000081000000-00000000810007e3 (prio 0, i/o): xlnx.xps-ethernetlite 00000000810007e4-00000000810007f3 (prio 0, i/o): ethlite.mdio 00000000810007f4-00000000810007ff (prio 0, i/o): ethlite.tx[0]io 0000000081000800-0000000081000ff3 (prio 0, i/o): xlnx.xps-ethernetlite @0000000000000800 0000000081000ff4-0000000081000fff (prio 0, i/o): ethlite.tx[1]io 0000000081001000-00000000810017fb (prio 0, i/o): xlnx.xps-ethernetlite @0000000000001000 00000000810017fc-00000000810017ff (prio 0, i/o): ethlite.rx[0]io 0000000081001800-0000000081001ffb (prio 0, i/o): xlnx.xps-ethernetlite @0000000000001800 0000000081001ffc-0000000081001fff (prio 0, i/o): ethlite.rx[1]io Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-Id: <20241112181044.92193-19-philmd@linaro.org>
| * hw/net/xilinx_ethlite: Map TX_GIE as MMIOPhilippe Mathieu-Daudé2025-01-131-10/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add TX_GIE to the TX registers MMIO region. Before TX_GIE1 was accessed as RAM, with no effect. Now it is accessed as MMIO, also without any effect. The memory flat view becomes: (qemu) info mtree -f FlatView #0 Root memory region: system 0000000081000000-00000000810007e3 (prio 0, i/o): xlnx.xps-ethernetlite 00000000810007e4-00000000810007f3 (prio 0, i/o): ethlite.mdio 00000000810007f4-00000000810007fb (prio 0, i/o): ethlite.tx[0]io 00000000810007fc-0000000081000ff3 (prio 0, i/o): xlnx.xps-ethernetlite @00000000000007fc 0000000081000ff4-0000000081000ffb (prio 0, i/o): ethlite.tx[1]io 0000000081000ffc-00000000810017fb (prio 0, i/o): xlnx.xps-ethernetlite @0000000000000ffc 00000000810017fc-00000000810017ff (prio 0, i/o): ethlite.rx[0]io 0000000081001800-0000000081001ffb (prio 0, i/o): xlnx.xps-ethernetlite @0000000000001800 0000000081001ffc-0000000081001fff (prio 0, i/o): ethlite.rx[1]io Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-Id: <20241112181044.92193-18-philmd@linaro.org>
| * hw/net/xilinx_ethlite: Map TX_LEN as MMIOPhilippe Mathieu-Daudé2025-01-131-12/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Declare TX registers as MMIO region, split it out of the current mixed RAM/MMIO region. The memory flat view becomes: (qemu) info mtree -f FlatView #0 Root memory region: system 0000000081000000-00000000810007e3 (prio 0, i/o): xlnx.xps-ethernetlite 00000000810007e4-00000000810007f3 (prio 0, i/o): ethlite.mdio 00000000810007f4-00000000810007f7 (prio 0, i/o): ethlite.tx[0]io 00000000810007f8-0000000081000ff3 (prio 0, i/o): xlnx.xps-ethernetlite @00000000000007f8 0000000081000ff4-0000000081000ff7 (prio 0, i/o): ethlite.tx[1]io 0000000081000ff8-00000000810017fb (prio 0, i/o): xlnx.xps-ethernetlite @0000000000000ff8 00000000810017fc-00000000810017ff (prio 0, i/o): ethlite.rx[0]io 0000000081001800-0000000081001ffb (prio 0, i/o): xlnx.xps-ethernetlite @0000000000001800 0000000081001ffc-0000000081001fff (prio 0, i/o): ethlite.rx[1]io Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-Id: <20241112181044.92193-17-philmd@linaro.org>
| * hw/net/xilinx_ethlite: Map RX_CTRL as MMIOPhilippe Mathieu-Daudé2025-01-131-15/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Declare RX registers as MMIO region, split it out of the current mixed RAM/MMIO region. The memory flat view becomes: (qemu) info mtree -f FlatView #0 Root memory region: system 0000000081000000-00000000810007e3 (prio 0, i/o): xlnx.xps-ethernetlite 00000000810007e4-00000000810007f3 (prio 0, i/o): ethlite.mdio 00000000810007f4-00000000810017fb (prio 0, i/o): xlnx.xps-ethernetlite @00000000000007f4 00000000810017fc-00000000810017ff (prio 0, i/o): ethlite.rx[0]io 0000000081001800-0000000081001ffb (prio 0, i/o): xlnx.xps-ethernetlite @0000000000001800 0000000081001ffc-0000000081001fff (prio 0, i/o): ethlite.rx[1]io Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20241112181044.92193-16-philmd@linaro.org>
| * hw/net/xilinx_ethlite: Access TX_CTRL register for each portPhilippe Mathieu-Daudé2025-01-131-8/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than accessing the registers within the mixed RAM/MMIO region as indexed register, declare a per-port TX_CTRL. This will help to map the RAM as RAM (keeping MMIO as MMIO) in few commits. Previous s->regs[R_TX_CTRL0] and s->regs[R_TX_CTRL1] are now unused. Not a concern, this array will soon disappear. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-Id: <20241112181044.92193-15-philmd@linaro.org>
| * hw/net/xilinx_ethlite: Access TX_LEN register for each portPhilippe Mathieu-Daudé2025-01-131-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than accessing the registers within the mixed RAM/MMIO region as indexed register, declare a per-port TX_LEN. This will help to map the RAM as RAM (keeping MMIO as MMIO) in few commits. Previous s->regs[R_TX_LEN0] and s->regs[R_TX_LEN1] are now unused. Not a concern, this array will soon disappear. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-Id: <20241112181044.92193-14-philmd@linaro.org>
| * hw/net/xilinx_ethlite: Access TX_GIE register for each portPhilippe Mathieu-Daudé2025-01-131-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than accessing the registers within the mixed RAM/MMIO region as indexed register, declare a per-port TX_GIE. This will help to map the RAM as RAM (keeping MMIO as MMIO) in few commits. Previous s->regs[R_TX_GIE0] and s->regs[R_TX_GIE1] are now unused. Not a concern, this array will soon disappear. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-Id: <20241112181044.92193-13-philmd@linaro.org>
| * hw/net/xilinx_ethlite: Introduce rxbuf_ptr() helperPhilippe Mathieu-Daudé2025-01-131-10/+29
| | | | | | | | | | | | | | | | | | rxbuf_ptr() points to the beginning of a (RAM) RX buffer within the device state. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-Id: <20241112181044.92193-11-philmd@linaro.org>
| * hw/net/xilinx_ethlite: Introduce txbuf_ptr() helperPhilippe Mathieu-Daudé2025-01-131-2/+16
| | | | | | | | | | | | | | | | | | | | | | | | For a particular physical address within the EthLite MMIO range, addr_to_port_index() returns which port is accessed. txbuf_ptr() points to the beginning of a (RAM) TX buffer within the device state. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-Id: <20241112181044.92193-10-philmd@linaro.org>