summary refs log tree commit diff stats
Commit message (Collapse)AuthorAgeFilesLines
* Merge remote-tracking branch ↵Peter Maydell2022-01-2852-74/+4300
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/pmaydell/tags/pull-target-arm-20220128' into staging target-arm queue: * Update copyright dates to 2022 * hw/armv7m: Fix broken VMStateDescription * hw/char/exynos4210_uart: Fix crash on trying to load VM state * rtc: Move RTC function prototypes to their own header * xlnx-versal-virt: Support PMC SLCR * xlnx-versal-virt: Support OSPI flash memory controller * scripts: Explain the difference between linux-headers and standard-headers * target/arm: Log CPU index in 'Taking exception' log * arm_gicv3_its: Various bugfixes and cleanups * arm_gicv3_its: Implement the missing MOVI and MOVALL commands * ast2600: Fix address mapping of second SPI controller * target/arm: Use correct entrypoint for SVC taken from Hyp to Hyp # gpg: Signature made Fri 28 Jan 2022 15:29:36 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20220128: (32 commits) target/arm: Use correct entrypoint for SVC taken from Hyp to Hyp hw/arm: ast2600: Fix address mapping of second SPI controller hw/intc/arm_gicv3_its: Implement MOVI hw/intc/arm_gicv3_its: Implement MOVALL hw/intc/arm_gicv3_its: Check table bounds against correct limit hw/intc/arm_gicv3_its: Make GITS_BASER<n> RAZ/WI for unimplemented registers hw/intc/arm_gicv3_its: Provide read accessor for translation_ops hw/intc/arm_gicv3: Set GICR_CTLR.CES if LPIs are supported hw/intc/arm_gicv3_redist: Remove unnecessary zero checks hw/intc/arm_gicv3_its: Sort ITS command list into numeric order hw/intc/arm_gicv3: Honour GICD_CTLR.EnableGrp1NS for LPIs hw/intc/arm_gicv3_its: Don't clear GITS_CWRITER on writes to GITS_CBASER hw/intc/arm_gicv3_its: Don't clear GITS_CREADR when GITS_CTLR.ENABLED is set hw/intc/arm_gicv3: Initialise dma_as in GIC, not ITS hw/intc/arm_gicv3_its: Add tracepoints target/arm: Log CPU index in 'Taking exception' log scripts: Explain the difference between linux-headers and standard-headers MAINTAINERS: Remove myself (for raspi). MAINTAINERS: Add an entry for Xilinx Versal OSPI hw/arm/xlnx-versal-virt: Connect mt35xu01g flashes to the OSPI ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Use correct entrypoint for SVC taken from Hyp to HypPeter Maydell2022-01-281-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The exception caused by an SVC instruction may be taken to AArch32 Hyp mode for two reasons: * HCR.TGE indicates that exceptions from EL0 should trap to EL2 * we were already in Hyp mode The entrypoint in the vector table to be used differs in these two cases: for an exception routed to Hyp mode from EL0, we enter at the common 0x14 "hyp trap" entrypoint. For SVC from Hyp mode to Hyp mode, we enter at the 0x08 (svc/hvc trap) entrypoint. In the v8A Arm ARM pseudocode this is done in AArch32.TakeSVCException. QEMU incorrectly routed both of these exceptions to the 0x14 entrypoint. Correct the entrypoint for SVC from Hyp to Hyp by making use of the existing logic which handles "normal entrypoint for Hyp-to-Hyp, otherwise 0x14" for traps like UNDEF and data/prefetch aborts (reproduced here since it's outside the visible context in the diff for this commit): if (arm_current_el(env) != 2 && addr < 0x14) { addr = 0x14; } Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220117131953.3936137-1-peter.maydell@linaro.org
| * hw/arm: ast2600: Fix address mapping of second SPI controllerCédric Le Goater2022-01-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Address should be 0x1E631000 and not 0x1E641000 as initially introduced. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/838 Fixes: f25c0ae1079d ("aspeed/soc: Add AST2600 support") Suggested-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20220126083520.4135713-1-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/intc/arm_gicv3_its: Implement MOVIPeter Maydell2022-01-283-0/+215
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement the ITS MOVI command. This command specifies a (physical) LPI by DeviceID and EventID and provides a new ICID for it. The ITS must find the interrupt translation table entry for the LPI, which will tell it the old ICID. It then moves the pending state of the LPI from the old redistributor to the new one and updates the ICID field in the translation table entry. This is another GICv3 ITS command that we forgot to implement. Linux does use this one, but only if the guest powers off one of its CPUs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220122182444.724087-15-peter.maydell@linaro.org
| * hw/intc/arm_gicv3_its: Implement MOVALLPeter Maydell2022-01-283-0/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | Implement the ITS MOVALL command, which takes all the pending interrupts on a source redistributor and makes the not-pending on that source redistributor and pending on a destination redistributor. This is a GICv3 ITS command which we forgot to implement. (It is not used by Linux guests.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220122182444.724087-14-peter.maydell@linaro.org
| * hw/intc/arm_gicv3_its: Check table bounds against correct limitPeter Maydell2022-01-282-10/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently when we fill in a TableDesc based on the value the guest has written to the GITS_BASER<n> register, we calculate both: * num_entries : the number of entries in the table, constrained by the amount of memory the guest has given it * num_ids : the number of IDs we support for this table, constrained by the implementation choices and the architecture (eg DeviceIDs are 16 bits, so num_ids is 1 << 16) When validating ITS commands, however, we check only num_ids, thus allowing a broken guest to specify table entries that index off the end of it. This will only corrupt guest memory, but the ITS is supposed to reject such commands as invalid. Instead of calculating both num_entries and num_ids, set num_entries to the minimum of the two limits, and check that. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220122182444.724087-13-peter.maydell@linaro.org
| * hw/intc/arm_gicv3_its: Make GITS_BASER<n> RAZ/WI for unimplemented registersPeter Maydell2022-01-281-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ITS has a bank of 8 GITS_BASER<n> registers, which allow the guest to specify the base address of various data tables. Each register has a read-only type field indicating which table it is for and a read-write field where the guest can write in the base address (among other things). We currently allow the guest to write the writeable fields for all eight registers, even if the type field is 0 indicating "Unimplemented". This means the guest can provoke QEMU into asserting by writing an address into one of these unimplemented base registers, which bypasses the "if (!value) continue" check in extract_table_params() and lets us hit the assertion that the type field is one of the permitted table types. Prevent the assertion by not allowing the guest to write to the unimplemented base registers. This means their value will remain 0 and extract_table_params() will ignore them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220122182444.724087-12-peter.maydell@linaro.org
| * hw/intc/arm_gicv3_its: Provide read accessor for translation_opsPeter Maydell2022-01-281-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MemoryRegionOps gicv3_its_translation_ops currently provides only a .write_with_attrs function, because the only register in this region is the write-only GITS_TRANSLATER. However, if you don't provide a read function and the guest tries reading from this memory region, QEMU will crash because memory_region_read_with_attrs_accessor() calls a NULL pointer. Add a read function which always returns 0, to cover both bogus attempts to read GITS_TRANSLATER and also reads from the rest of the region, which is documented to be reserved, RES0. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220122182444.724087-11-peter.maydell@linaro.org
| * hw/intc/arm_gicv3: Set GICR_CTLR.CES if LPIs are supportedPeter Maydell2022-01-282-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | The GICR_CTLR.CES bit is a read-only bit which is set to 1 to indicate that the GICR_CTLR.EnableLPIs bit can be written to 0 to disable LPIs (as opposed to allowing LPIs to be enabled but not subsequently disabled). Our implementation permits this, so advertise it by setting CES to 1. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220122182444.724087-10-peter.maydell@linaro.org
| * hw/intc/arm_gicv3_redist: Remove unnecessary zero checksPeter Maydell2022-01-281-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ITS-related parts of the redistributor code make some checks for whether registers like GICR_PROPBASER and GICR_PENDBASER are zero. There is no requirement in the specification for treating zeroes in these address registers specially -- they contain guest physical addresses and it is entirely valid (if unusual) for the guest to choose to put the tables they address at guest physical address zero. We use these values only to calculate guest addresses, and attempts by the guest to use a bad address will be handled by the address_space_* functions which we use to do the loads and stores. Remove the unnecessary checks. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220122182444.724087-9-peter.maydell@linaro.org
| * hw/intc/arm_gicv3_its: Sort ITS command list into numeric orderPeter Maydell2022-01-281-5/+5
| | | | | | | | | | | | | | | | | | | | The list of #defines for the ITS command packet numbers is neither in alphabetical nor numeric order. Sort it into numeric order. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220122182444.724087-8-peter.maydell@linaro.org
| * hw/intc/arm_gicv3: Honour GICD_CTLR.EnableGrp1NS for LPIsPeter Maydell2022-01-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The GICD_CTLR distributor register has enable bits which control whether the different interrupt groups (Group 0, Non-secure Group 1 and Secure Group 1) are forwarded to the CPU. We get this right for traditional interrupts, but forgot to account for it when adding LPIs. LPIs are always Group 1 NS and if the EnableGrp1NS bit is not set we must not forward them to the CPU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220122182444.724087-7-peter.maydell@linaro.org
| * hw/intc/arm_gicv3_its: Don't clear GITS_CWRITER on writes to GITS_CBASERPeter Maydell2022-01-281-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | The ITS specification says that when the guest writes to GITS_CBASER this causes GITS_CREADR to be cleared. However it does not have an equivalent clause for GITS_CWRITER. (This is because GITS_CREADR is read-only, but GITS_CWRITER is writable and the guest can initialize it.) Remove the code that clears GITS_CWRITER on GITS_CBASER writes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220122182444.724087-6-peter.maydell@linaro.org
| * hw/intc/arm_gicv3_its: Don't clear GITS_CREADR when GITS_CTLR.ENABLED is setPeter Maydell2022-01-281-1/+0
| | | | | | | | | | | | | | | | | | | | | | The current ITS code clears GITS_CREADR when GITS_CTLR.ENABLED is set. This is not correct -- guest code can validly clear ENABLED and then set it again and expect the ITS to continue processing where it left off. Remove the erroneous assignment. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220122182444.724087-5-peter.maydell@linaro.org
| * hw/intc/arm_gicv3: Initialise dma_as in GIC, not ITSPeter Maydell2022-01-282-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In our implementation, all ITSes connected to a GIC share a single AddressSpace, which we keep in the GICv3State::dma_as field and initialized based on the GIC's 'sysmem' property. The right place to set it up by calling address_space_init() is therefore in the GIC's realize method, not the ITS's realize. This fixes a theoretical bug where QEMU hangs on startup if the board model creates two ITSes connected to the same GIC -- we would call address_space_init() twice on the same AddressSpace*, which creates an infinite loop in the QTAILQ that softmmu/memory.c uses to store its list of AddressSpaces and causes any subsequent attempt to iterate through that list to loop forever. There aren't any board models like that in the tree at the moment, though. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220122182444.724087-4-peter.maydell@linaro.org
| * hw/intc/arm_gicv3_its: Add tracepointsPeter Maydell2022-01-282-0/+19
| | | | | | | | | | | | | | | | | | | | | | The ITS currently has no tracepoints; add a minimal set that allows basic monitoring of guest register accesses and reading of commands from the command queue. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220122182444.724087-3-peter.maydell@linaro.org
| * target/arm: Log CPU index in 'Taking exception' logPeter Maydell2022-01-283-5/+8
| | | | | | | | | | | | | | | | | | | | | | In an SMP system it can be unclear which CPU is taking an exception; add the CPU index (which is the same value used in the TCG 'Trace %d:' logging) to the "Taking exception" log line to clarify it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220122182444.724087-2-peter.maydell@linaro.org
| * scripts: Explain the difference between linux-headers and standard-headersPeter Maydell2022-01-281-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | If you don't know it, it's hard to figure out the difference between the linux-headers folder and the include/standard-headers folder. So let's add a short explanation to clarify the difference. Suggested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com>
| * MAINTAINERS: Remove myself (for raspi).Andrew Baumann2022-01-281-1/+0
| | | | | | | | | | | | Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Message-id: MW4PR21MB1940E8BB52F4053C943B1FCD9E219@MW4PR21MB1940.namprd21.prod.outlook.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * MAINTAINERS: Add an entry for Xilinx Versal OSPIFrancisco Iglesias2022-01-281-0/+6
| | | | | | | | | | | | | | | | | | | | List myself as maintainer for the Xilinx Versal OSPI controller. Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220121161141.14389-11-francisco.iglesias@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/xlnx-versal-virt: Connect mt35xu01g flashes to the OSPIFrancisco Iglesias2022-01-281-0/+23
| | | | | | | | | | | | | | | | | | | | | | Connect Micron Xccela mt35xu01g flashes to the OSPI flash memory controller. Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220121161141.14389-10-francisco.iglesias@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/block/m25p80: Add support for Micron Xccela flash mt35xu01gFrancisco Iglesias2022-01-281-0/+2
| | | | | | | | | | | | | | | | | | Add support for Micron Xccela flash mt35xu01g. Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20220121161141.14389-9-francisco.iglesias@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/xlnx-versal: Connect the OSPI flash memory controller modelFrancisco Iglesias2022-01-282-0/+113
| | | | | | | | | | | | | | | | | | | | Connect the OSPI flash memory controller model (including the source and destination DMA). Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220121161141.14389-8-francisco.iglesias@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/ssi: Add a model of Xilinx Versal's OSPI flash memory controllerFrancisco Iglesias2022-01-283-0/+1965
| | | | | | | | | | | | | | | | | | | | Add a model of Xilinx Versal's OSPI flash memory controller. Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20220121161141.14389-7-francisco.iglesias@xilinx.com [PMM: fixed indent] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/dma/xlnx_csu_dma: Support starting a read transfer through a class methodFrancisco Iglesias2022-01-282-2/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | An option on real hardware when embedding a DMA engine into a peripheral is to make the peripheral control the engine through a custom DMA control (hardware) interface between the two. Software drivers in this scenario configure and trigger DMA operations through the controlling peripheral's register API (for example, writing a specific bit in a register could propagate down to a transfer start signal on the DMA control interface). At the same time the status, results and interrupts for the transfer might still be intended to be read and caught through the DMA engine's register API (and signals). This patch adds a class 'read' method for allowing to start read transfers from peripherals embedding and controlling the Xilinx CSU DMA engine as in above scenario. Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20220121161141.14389-6-francisco.iglesias@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * include/hw/dma/xlnx_csu_dma: Add in missing includes in the headerFrancisco Iglesias2022-01-281-0/+5
| | | | | | | | | | | | | | | | | | | | | | Add in the missing includes in the header for being able to build the DMA model when reusing it. Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20220121161141.14389-5-francisco.iglesias@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/xlnx-versal: Connect Versal's PMC SLCRFrancisco Iglesias2022-01-282-1/+75
| | | | | | | | | | | | | | | | | | Connect Versal's PMC SLCR (system-level control registers) model. Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20220121161141.14389-4-francisco.iglesias@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/xlnx-versal: 'Or' the interrupts from the BBRAM and RTC modelsFrancisco Iglesias2022-01-283-5/+30
| | | | | | | | | | | | | | | | | | | | Add an orgate and 'or' the interrupts from the BBRAM and RTC models. Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20220121161141.14389-3-francisco.iglesias@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/misc: Add a model of Versal's PMC SLCRFrancisco Iglesias2022-01-283-1/+1528
| | | | | | | | | | | | | | | | | | | | | | Add a model of Versal's PMC SLCR (system-level control registers). Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20220121161141.14389-2-francisco.iglesias@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * rtc: Move RTC function prototypes to their own headerPeter Maydell2022-01-2824-25/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | softmmu/rtc.c defines two public functions: qemu_get_timedate() and qemu_timedate_diff(). Currently we keep the prototypes for these in qemu-common.h, but most files don't need them. Move them to their own header, a new include/sysemu/rtc.h. Since the C files using these two functions did not need to include qemu-common.h for any other reason, we can remove those include lines when we add the include of the new rtc.h. The license for the .h file follows that of the softmmu/rtc.c where both the functions are defined. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
| * hw/char/exynos4210_uart: Fix crash on trying to load VM statePeter Maydell2022-01-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The exynos4210_uart_post_load() function assumes that it is passed the Exynos4210UartState, but it has been attached to the VMStateDescription for the Exynos4210UartFIFO type. The result is a SIGSEGV when attempting to load VM state for any machine type including this device. Fix the bug by attaching the post-load function to the VMSD for the Exynos4210UartState. This is the logical place for it, because the actions it does relate to the entire UART state, not just the FIFO. Thanks to the bug reporter @TrungNguyen1909 for the clear bug description and the suggested fix. Fixes: c9d3396d80fe7ece9b ("hw/char/exynos4210_uart: Implement post_load function") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/638 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20220120151648.433736-1-peter.maydell@linaro.org
| * hw/armv7m: Fix broken VMStateDescriptionPeter Maydell2022-01-281-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In commit d5093d961585f02 we added a VMStateDescription to the TYPE_ARMV7M object, to handle migration of its Clocks. However a cut-and-paste error meant we used the wrong struct name in the VMSTATE_CLOCK() macro arguments. The result was that attempting a 'savevm' might result in an assertion failure. Cc: qemu-stable@nongnu.org Buglink: https://gitlab.com/qemu-project/qemu/-/issues/803 Fixes: d5093d961585f02 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Ani Sinha <ani@anisinha.ca> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20220120151609.433555-1-peter.maydell@linaro.org
| * Update copyright dates to 2022Peter Maydell2022-01-282-2/+2
| | | | | | | | | | | | | | | | | | | | It's a new year; update the copyright strings for our help/version/about information and for our documentation. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20220120124713.288303-1-peter.maydell@linaro.org
* | Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ↵Peter Maydell2022-01-2825-123/+189
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging * configure and meson fixes * "meson test" switch for iotests * deprecation of old SGX QAPI * unexport InterruptStatsProviderClass-related functions # gpg: Signature made Fri 28 Jan 2022 10:13:36 GMT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini-gitlab/tags/for-upstream: configure: fix parameter expansion of --cross-cc-cflags options qapi: Cleanup SGX related comments and restore @section-size check-block: replace -makecheck with TAP output qemu-iotests: require at least an argument to check-block.sh build: make check-block a meson test scripts/mtest2make: add support for SPEED=thorough check-block.sh: passthrough -jN flag of make to -j N flag of check meson: Use find_program() to resolve the entitlement.sh script exec/cpu: Make host pages variables / macros 'target agnostic' meson.build: Use a function from libfdt 1.5.1 for the library check intc: Unexport InterruptStatsProviderClass-related functions docker: add msitools to Fedora/mingw cross build-sys: fix undefined ARCH error build-sys: fix a meson deprecation warning Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * configure: fix parameter expansion of --cross-cc-cflags optionsMatheus Ferst2022-01-282-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Without this fix, any use of --cross-cc-cflags-* causes a message like: $ ../configure --cross-cc-ppc64le=clang --cross-cc-cflags-ppc64le="-target powerpc64le-unknown-linux-gnu -sysroot ..." ../configure: 1: eval: cross_cc_cflags_--cross-cc-cflags-ppc64le=-target: not found ../configure: 3816: export: cross_cc_cflags_--cross-cc-cflags-ppc64le: bad variable name Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220120173142.2755077-1-matheus.ferst@eldorado.org.br> [Fix other occurrences too, noted by Philippe Mathieu-Daudé. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * qapi: Cleanup SGX related comments and restore @section-sizeYang Zhong2022-01-284-9/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SGX NUMA patches were merged into Qemu 7.0 release, we need clarify detailed version history information and also change some related comments, which make SGX related comments clearer. The QMP command schema promises backwards compatibility as standard. We temporarily restore "@section-size", which can avoid incompatible API breakage. The "@section-size" will be deprecated in 7.2 version. Suggested-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Yang Zhong <yang.zhong@intel.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220120223104.437161-1-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * check-block: replace -makecheck with TAP outputPaolo Bonzini2022-01-285-44/+48
| | | | | | | | | | | | | | Let "meson test" take care of showing the results of the individual tests, consistently with other output from "make check V=1". Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * qemu-iotests: require at least an argument to check-block.shPaolo Bonzini2022-01-281-10/+7
| | | | | | | | | | | | | | | | This is anyway how check-block.sh is used in practice, and by removing the list of formats in the script we avoid duplication between meson.build and check-block.sh. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * build: make check-block a meson testPaolo Bonzini2022-01-286-32/+58
| | | | | | | | | | | | | | | | | | | | | | | | "meson test" can be asked to run tests verbosely; this makes it usable also for qemu-iotests's own harness, and it lets "make check-block" reuse mtest2make.py's infrastructure to find and build test dependencies. Adjust check-block.sh to use the standard exit code that reports a test as skipped. Alternatively, in the future we could make it produce TAP output, which is consistent with all other "make check" tests. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * scripts/mtest2make: add support for SPEED=thoroughPaolo Bonzini2022-01-282-5/+10
| | | | | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * check-block.sh: passthrough -jN flag of make to -j N flag of checkVladimir Sementsov-Ogievskiy2022-01-281-1/+8
| | | | | | | | | | | | | | | | This improves performance of running iotests during "make -jN check". Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-Id: <20211223183933.1497037-1-vsementsov@virtuozzo.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * meson: Use find_program() to resolve the entitlement.sh scriptPhilippe Mathieu-Daudé2022-01-281-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using ../configure without any particular option generates 31 targets on Darwin, and meson search for the entitlement.sh script 31 times: Program nm found: YES Program scripts/undefsym.py found: YES (/opt/homebrew/opt/python@3.9/bin/python3.9 /Code/qemu/scripts/undefsym.py) Program scripts/feature_to_c.sh found: YES (/bin/sh /Code/qemu/scripts/feature_to_c.sh) Program scripts/entitlement.sh found: YES (/Code/qemu/scripts/entitlement.sh) Program scripts/entitlement.sh found: YES (/Code/qemu/scripts/entitlement.sh) Program scripts/entitlement.sh found: YES (/Code/qemu/scripts/entitlement.sh) Program scripts/entitlement.sh found: YES (/Code/qemu/scripts/entitlement.sh) Program scripts/entitlement.sh found: YES (/Code/qemu/scripts/entitlement.sh) Program scripts/entitlement.sh found: YES (/Code/qemu/scripts/entitlement.sh) Program scripts/entitlement.sh found: YES (/Code/qemu/scripts/entitlement.sh) Program scripts/entitlement.sh found: YES (/Code/qemu/scripts/entitlement.sh) Program scripts/entitlement.sh found: YES (/Code/qemu/scripts/entitlement.sh) Program scripts/entitlement.sh found: YES (/Code/qemu/scripts/entitlement.sh) Program scripts/entitlement.sh found: YES (/Code/qemu/scripts/entitlement.sh) Program scripts/entitlement.sh found: YES (/Code/qemu/scripts/entitlement.sh) Program scripts/entitlement.sh found: YES (/Code/qemu/scripts/entitlement.sh) Program scripts/entitlement.sh found: YES (/Code/qemu/scripts/entitlement.sh) Program scripts/entitlement.sh found: YES (/Code/qemu/scripts/entitlement.sh) Program scripts/entitlement.sh found: YES (/Code/qemu/scripts/entitlement.sh) Program scripts/entitlement.sh found: YES (/Code/qemu/scripts/entitlement.sh) Program scripts/entitlement.sh found: YES (/Code/qemu/scripts/entitlement.sh) Program scripts/entitlement.sh found: YES (/Code/qemu/scripts/entitlement.sh) Program scripts/entitlement.sh found: YES (/Code/qemu/scripts/entitlement.sh) Program scripts/entitlement.sh found: YES (/Code/qemu/scripts/entitlement.sh) Program scripts/entitlement.sh found: YES (/Code/qemu/scripts/entitlement.sh) Program scripts/entitlement.sh found: YES (/Code/qemu/scripts/entitlement.sh) Program scripts/entitlement.sh found: YES (/Code/qemu/scripts/entitlement.sh) Program scripts/entitlement.sh found: YES (/Code/qemu/scripts/entitlement.sh) Program scripts/entitlement.sh found: YES (/Code/qemu/scripts/entitlement.sh) Program scripts/entitlement.sh found: YES (/Code/qemu/scripts/entitlement.sh) Program scripts/entitlement.sh found: YES (/Code/qemu/scripts/entitlement.sh) Program scripts/entitlement.sh found: YES (/Code/qemu/scripts/entitlement.sh) Program scripts/entitlement.sh found: YES (/Code/qemu/scripts/entitlement.sh) Program scripts/entitlement.sh found: YES (/Code/qemu/scripts/entitlement.sh) Configuring 50-edk2-i386-secure.json using configuration Configuring 50-edk2-x86_64-secure.json using configuration Use find_program() which seems to cache the script path once found. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220122002052.83745-1-f4bug@amsat.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * exec/cpu: Make host pages variables / macros 'target agnostic'Philippe Mathieu-Daudé2022-01-272-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | "host" pages are related to the *host* not the *target*, thus the qemu_host_page_size / qemu_host_page_mask variables and the HOST_PAGE_ALIGN() / REAL_HOST_PAGE_ALIGN() macros can be moved to "exec/cpu-common.h" which is target agnostic. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20220120000836.229419-1-f4bug@amsat.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * meson.build: Use a function from libfdt 1.5.1 for the library checkThomas Huth2022-01-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The fdt version test in meson.build uses a function from libfdt v1.4.7, but we require version 1.5.1 nowadays. Thus use a function that has been introduced in that version instead. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/822 Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220118170548.97288-1-thuth@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * intc: Unexport InterruptStatsProviderClass-related functionsBernhard Beschow2022-01-274-8/+4
| | | | | | | | | | | | | | | | | | The functions are only used within their respective source files, so no need for exporting. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-Id: <20220116122327.73048-1-shentey@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * docker: add msitools to Fedora/mingw crossMarc-André Lureau2022-01-272-0/+2
| | | | | | | | | | | | | | | | That should help catch build issues/regressions with wixl. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20220114084312.3725242-2-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * build-sys: fix undefined ARCH errorMarc-André Lureau2022-01-271-1/+1
| | | | | | | | | | | | | | | | | | | | ../qga/meson.build:76:4: ERROR: Key ARCH is not in the dictionary. Fixes commit 823eb013 ("configure, meson: move ARCH to meson.build") Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20220114084312.3725242-1-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * build-sys: fix a meson deprecation warningMarc-André Lureau2022-01-271-1/+1
| | | | | | | | | | | | | | | | | | | | WARNING: Deprecated features used: * 0.56.0: {'meson.source_root'} Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reported-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220113162148.3621818-1-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | Merge remote-tracking branch 'remotes/aperard/tags/pull-xen-20220127' into ↵Peter Maydell2022-01-282-3/+11
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging Xen patches - bug fixes for mapcache and ioreq handling # gpg: Signature made Thu 27 Jan 2022 15:17:22 GMT # gpg: using RSA key F80C006308E22CFD8A92E7980CF5572FD7FB55AF # gpg: Good signature from "Anthony PERARD <anthony.perard@gmail.com>" [unknown] # gpg: aka "Anthony PERARD <anthony.perard@citrix.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 5379 2F71 024C 600F 778A 7161 D8D5 7199 DF83 42C8 # Subkey fingerprint: F80C 0063 08E2 2CFD 8A92 E798 0CF5 572F D7FB 55AF * remotes/aperard/tags/pull-xen-20220127: xen-mapcache: Avoid entry->lock overflow xen-hvm: Allow disabling buffer_io_timer Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | xen-mapcache: Avoid entry->lock overflowRoss Lagerwall2022-01-271-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some cases, a particular mapcache entry may be mapped 256 times causing the lock field to wrap to 0. For example, this may happen when using emulated NVME and the guest submits a large scatter-gather write. At this point, the entry map be remapped causing QEMU to write the wrong data or crash (since remap is not atomic). Avoid this overflow by increasing the lock field to a uint32_t and also detect it and abort rather than continuing regardless. Signed-off-by: Ross Lagerwall <ross.lagerwall@citrix.com> Reviewed-by: Paul Durrant <paul@xen.org> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Message-Id: <20220124104450.152481-1-ross.lagerwall@citrix.com> Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>