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| * | hw/arm/exynos4210: Delete unused macro definitionsPeter Maydell2022-04-211-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | Delete a couple of #defines which are never used. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220404154658.565020-12-peter.maydell@linaro.org
| * | hw/arm/exynos4210: Move exynos4210_combiner_get_gpioin() into exynos4210.cPeter Maydell2022-04-213-88/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The function exynos4210_combiner_get_gpioin() currently lives in exynos4210_combiner.c, but it isn't really part of the combiner device itself -- it is a function that implements the wiring up of some interrupt sources to multiple combiner inputs. Move it to live with the other SoC-level code in exynos4210.c, along with a few macros previously defined in exynos4210.h which are now used only in exynos4210.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220404154658.565020-11-peter.maydell@linaro.org
| * | hw/arm/exynos4210: Drop ext_gic_irq[] from Exynos4210Irq structPeter Maydell2022-04-212-7/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The only time we use the ext_gic_irq[] array in the Exynos4210Irq struct is during realize of the SoC -- we initialize it with the input IRQs of the external GIC device, and then connect those to outputs of other devices further on in realize (including in the exynos4210_init_board_irqs() function). Now that the ext_gic object is easily accessible as s->ext_gic we can make the connections directly from one device to the other without going via this array. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220404154658.565020-10-peter.maydell@linaro.org
| * | hw/arm/exynos4210: Put external GIC into state structPeter Maydell2022-04-215-21/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switch the creation of the external GIC to the new-style "embedded in state struct" approach, so we can easily refer to the object elsewhere during realize. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220404154658.565020-9-peter.maydell@linaro.org
| * | hw/arm/exynos4210: Move exynos4210_init_board_irqs() into exynos4210.cPeter Maydell2022-04-213-208/+202
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The function exynos4210_init_board_irqs() currently lives in exynos4210_gic.c, but it isn't really part of the exynos4210.gic device -- it is a function that implements (some of) the wiring up of interrupts between the SoC's GIC and combiner components. This means it fits better in exynos4210.c, which is the SoC-level code. Move it there. Similarly, exynos4210_git_irq() is used almost only in the SoC-level code, so move it too. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220404154658.565020-8-peter.maydell@linaro.org
| * | hw/arm/exynos4210: Fix code style nit in combiner_grp_to_gic_id[]Peter Maydell2022-04-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix a missing set of spaces around '-' in the definition of combiner_grp_to_gic_id[]. We're about to move this code, so fix the style issue first to keep checkpatch happy with the code-motion patch. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220404154658.565020-7-peter.maydell@linaro.org
| * | hw/arm/exynos4210: Coalesce board_irqs and irq_tablePeter Maydell2022-04-213-35/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The exynos4210 code currently has two very similar arrays of IRQs: * board_irqs is a field of the Exynos4210Irq struct which is filled in by exynos4210_init_board_irqs() with the appropriate qemu_irqs for each IRQ the board/SoC can assert * irq_table is a set of qemu_irqs pointed to from the Exynos4210State struct. It's allocated in exynos4210_init_irq, and the only behaviour these irqs have is that they pass on the level to the equivalent board_irqs[] irq The extra indirection through irq_table is unnecessary, so coalesce these into a single irq_table[] array as a direct field in Exynos4210State which exynos4210_init_board_irqs() fills in. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220404154658.565020-6-peter.maydell@linaro.org
| * | hw/arm/exynos4210: Drop int_gic_irq[] from Exynos4210Irq structPeter Maydell2022-04-212-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The only time we use the int_gic_irq[] array in the Exynos4210Irq struct is in the exynos4210_realize() function: we initialize it with the GPIO inputs of the a9mpcore device, and then a bit later on we connect those to the outputs of the internal combiner. Now that the a9mpcore object is easily accessible as s->a9mpcore we can make the connection directly from one device to the other without going via this array. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220404154658.565020-5-peter.maydell@linaro.org
| * | hw/arm/exynos4210: Put a9mpcore device into state structPeter Maydell2022-04-212-5/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The exynos4210 SoC mostly creates its child devices as if it were board code. This includes the a9mpcore object. Switch that to a new-style "embedded in the state struct" creation, because in the next commit we're going to want to refer to the object again further down in the exynos4210_realize() function. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220404154658.565020-4-peter.maydell@linaro.org
| * | hw/intc/exynos4210_gic: Remove unused TYPE_EXYNOS4210_IRQ_GATEPeter Maydell2022-04-211-107/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Now we have removed the only use of TYPE_EXYNOS4210_IRQ_GATE we can delete the device entirely. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Message-id: 20220404154658.565020-3-peter.maydell@linaro.org
| * | hw/arm/exynos4210: Use TYPE_OR_IRQ instead of custom OR-gate devicePeter Maydell2022-04-212-15/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Exynos4210 SoC device currently uses a custom device "exynos4210.irq_gate" to model the OR gate that feeds each CPU's IRQ line. We have a standard TYPE_OR_IRQ device for this now, so use that instead. (This is a migration compatibility break, but that is OK for this machine type.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220404154658.565020-2-peter.maydell@linaro.org
| * | hw/arm: versal: Connect the CRLEdgar E. Iglesias2022-04-212-2/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Connect the CRL (Clock Reset LPD) to the Versal SoC. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Frederic Konrad <fkonrad@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Message-id: 20220406174303.2022038-5-edgar.iglesias@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hw/misc: Add a model of the Xilinx Versal CRLEdgar E. Iglesias2022-04-213-0/+657
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a model of the Xilinx Versal CRL. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Frederic Konrad <fkonrad@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Message-id: 20220406174303.2022038-4-edgar.iglesias@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hw/arm: versal: Add the Cortex-R5FsEdgar E. Iglesias2022-04-213-3/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the Cortex-R5Fs of the Versal RPU (Real-time Processing Unit) subsystem. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Message-id: 20220406174303.2022038-3-edgar.iglesias@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hw/arm: versal: Create an APU CPU ClusterEdgar E. Iglesias2022-04-212-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Create an APU CPU Cluster. This is in preparation to add the RPU. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Message-id: 20220406174303.2022038-2-edgar.iglesias@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hw/arm/xlnx-zynqmp: Connect 4 TTC timersEdgar E. Iglesias2022-04-212-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Connect the 4 TTC timers on the ZynqMP. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Message-id: 20220331222017.2914409-3-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | timer: cadence_ttc: Break out header file to allow embeddingEdgar E. Iglesias2022-04-212-30/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Break out header file to allow embedding of the the TTC. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Message-id: 20220331222017.2914409-2-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hw/arm/virt: Check for attempt to use TrustZone with KVM or HVFPeter Maydell2022-04-211-0/+7
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's not possible to provide the guest with the Security extensions (TrustZone) when using KVM or HVF, because the hardware virtualization extensions don't permit running EL3 guest code. However, we weren't checking for this combination, with the result that QEMU would assert if you tried it: $ qemu-system-aarch64 -enable-kvm -machine virt,secure=on -cpu host -display none Unexpected error in object_property_find_err() at ../../qom/object.c:1304: qemu-system-aarch64: Property 'host-arm-cpu.secure-memory' not found Aborted Check for this combination of options and report an error, in the same way we already do for attempts to give a KVM or HVF guest the Virtualization or MTE extensions. Now we will report: qemu-system-aarch64: mach-virt: KVM does not support providing Security extensions (TrustZone) to the guest CPU Resolves: https://gitlab.com/qemu-project/qemu/-/issues/961 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220404155301.566542-1-peter.maydell@linaro.org
* | Merge tag 'pull-ppc-20220420-2' of https://gitlab.com/danielhb/qemu into stagingRichard Henderson2022-04-2032-136/+445
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ppc patch queue for 2022-04-20 First batch of ppc patches for QEMU 7.1: - skiboot firmware version bump - pseries: add 2M DDW pagesize - pseries: make virtual hypervisor code TCG only - powernv: introduce GPIO lines for PSIHB device - powernv: remove PCIE root bridge LSI - target/ppc: alternative softfloat 128 bit integer support - assorted fixes # -----BEGIN PGP SIGNATURE----- # # iHUEABYKAB0WIQQX6/+ZI9AYAK8oOBk82cqW3gMxZAUCYmB/ngAKCRA82cqW3gMx # ZE10AP4wPeJQ3fxXb5ylVtL4qkJaLWy6VrJBQSKSb5YEA0fhegEA9ZufpnENQePU # gZF0eFAQK/DbSnDyvRQVpGcJM0K1UgI= # =nVRw # -----END PGP SIGNATURE----- # gpg: Signature made Wed 20 Apr 2022 02:48:14 PM PDT # gpg: using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164 # gpg: Can't check signature: No public key * tag 'pull-ppc-20220420-2' of https://gitlab.com/danielhb/qemu: (23 commits) hw/ppc: change indentation to spaces from TABs target/ppc: Add two missing register callbacks on POWER10 ppc/pnv: Remove LSI on the PCIE host bridge pcie: Don't try triggering a LSI when not defined ppc/vof: Fix uninitialized string tracing hw/ppc/ppc405_boards: Initialize g_autofree pointer target/ppc: implement xscvqp[su]qz target/ppc: implement xscv[su]qqp softfloat: add float128_to_int128 softfloat: add float128_to_uint128 softfloat: add int128_to_float128 softfloat: add uint128_to_float128 qemu/int128: add int128_urshift target/ppc: Improve KVM hypercall trace spapr: Move nested KVM hypercalls under a TCG only config. spapr: Move hypercall_register_softmmu ppc/pnv: Remove useless checks in set_irq handlers ppc/pnv: Remove PnvPsiClas::irq_set ppc/pnv: Remove PnvOCC::psi link ppc/pnv: Remove PnvLpcController::psi link ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * hw/ppc: change indentation to spaces from TABsGuo Zhi2022-04-203-17/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | There are still some files in the QEMU PPC code base that use TABs for indentation instead of using spaces. The TABs should be replaced so that we have a consistent coding style. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/374 Signed-off-by: Guo Zhi <qtxuning1999@sjtu.edu.cn> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220412021240.2080218-1-qtxuning1999@sjtu.edu.cn> [danielhb: trimmed commit msg to 72 chars per line] Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * target/ppc: Add two missing register callbacks on POWER10Frederic Barrat2022-04-201-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds tcg accessors for 2 SPRs which were missing on P10: - the TBU40 register is used to write the upper 40 bits of the timebase register. It is used by kvm to update the timebase when entering/exiting the guest on P9 and above. The missing definition was causing erratic decrementer interrupts in a pseries/kvm guest running in a powernv10/tcg host, typically resulting in hangs. - the missing DPDES SPR was found through code inspection. It exists unchanged on P10. Both existed on previous versions of the processor and a bit of git archaeology hints that they were added while the P10 model was already being worked on so they may have simply fallen through the cracks. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220411125900.352028-1-fbarrat@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * ppc/pnv: Remove LSI on the PCIE host bridgeFrederic Barrat2022-04-202-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The phb3/phb4/phb5 root ports inherit from the default PCIE root port implementation, which requests a LSI interrupt (#INTA). On real hardware (POWER8/POWER9/POWER10), there is no such LSI. This patch corrects it so that it matches the hardware. As a consequence, the device tree previously generated was bogus, as the root bridge LSI was not properly mapped. On some implementation (powernv9), it was leading to inconsistent interrupt controller (xive) data. With this patch, it is now clean. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220408131303.147840-3-fbarrat@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * pcie: Don't try triggering a LSI when not definedFrederic Barrat2022-04-202-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch skips [de]asserting a LSI interrupt if the device doesn't have any LSI defined. Doing so would trigger an assert in pci_irq_handler(). The PCIE root port implementation in qemu requests a LSI (INTA), but a subclass may want to change that behavior since it's a valid configuration. For example on the POWER8/POWER9/POWER10 systems, the root bridge doesn't request any LSI. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20220408131303.147840-2-fbarrat@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * ppc/vof: Fix uninitialized string tracingAlexey Kardashevskiy2022-04-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | There are error paths which do not initialize propname but the trace_exit label prints it anyway. This initializes the problem string. Spotted by Coverity CID 1487241. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220406045013.3610172-1-aik@ozlabs.ru> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * hw/ppc/ppc405_boards: Initialize g_autofree pointerBernhard Beschow2022-04-201-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Resolves the only compiler warning when building a full QEMU under Arch Linux: Compiling C object libqemu-ppc-softmmu.fa.p/hw_ppc_ppc405_boards.c.o In file included from /usr/include/glib-2.0/glib.h:114, from qemu/include/glib-compat.h:32, from qemu/include/qemu/osdep.h:132, from ../src/hw/ppc/ppc405_boards.c:25: ../src/hw/ppc/ppc405_boards.c: In function ‘ref405ep_init’: /usr/include/glib-2.0/glib/glib-autocleanups.h:28:3: warning: ‘filename’ may be used uninitialized in this function [-Wmaybe-uninitialized] 28 | g_free (*pp); | ^~~~~~~~~~~~ ../src/hw/ppc/ppc405_boards.c:265:26: note: ‘filename’ was declared here 265 | g_autofree char *filename; | ^~~~~~~~ Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220405123534.3395-1-shentey@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * target/ppc: implement xscvqp[su]qzMatheus Ferst2022-04-204-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | Implement the following PowerISA v3.1 instructions: xscvqpsqz: VSX Scalar Convert with round to zero Quad-Precision to Signed Quadword xscvqpuqz: VSX Scalar Convert with round to zero Quad-Precision to Unsigned Quadword Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220330175932.6995-9-matheus.ferst@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * target/ppc: implement xscv[su]qqpMatheus Ferst2022-04-204-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | Implement the following PowerISA v3.1 instructions: xscvsqqp: VSX Scalar Convert with round Signed Quadword to Quad-Precision xscvuqqp: VSX Scalar Convert with round Unsigned Quadword to Quad-Precision format Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220330175932.6995-8-matheus.ferst@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * softfloat: add float128_to_int128Matheus Ferst2022-04-203-0/+68
| | | | | | | | | | | | | | | | | | Implements float128_to_int128 based on parts_float_to_int logic. Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220330175932.6995-7-matheus.ferst@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * softfloat: add float128_to_uint128Matheus Ferst2022-04-202-0/+67
| | | | | | | | | | | | | | | | | | Implements float128_to_uint128 based on parts_float_to_uint logic. Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220330175932.6995-6-matheus.ferst@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * softfloat: add int128_to_float128Matheus Ferst2022-04-202-0/+30
| | | | | | | | | | | | | | | | | | Based on parts_sint_to_float, implements int128_to_float128 to convert a signed 128-bit value received through an Int128 argument. Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220330175932.6995-5-matheus.ferst@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * softfloat: add uint128_to_float128Matheus Ferst2022-04-202-0/+27
| | | | | | | | | | | | | | | | | | | | Based on parts_uint_to_float, implements uint128_to_float128 to convert an unsigned 128-bit value received through an Int128 argument. Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220330175932.6995-4-matheus.ferst@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * qemu/int128: add int128_urshiftMatheus Ferst2022-04-202-0/+69
| | | | | | | | | | | | | | | | | | | | | | Implement an unsigned right shift for Int128 values and add the same tests cases of int128_rshift in the unit test. Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220330175932.6995-3-matheus.ferst@eldorado.org.br> [danielhb: fixed long lines in test_urshift()] Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * target/ppc: Improve KVM hypercall traceFabiano Rosas2022-04-202-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before: kvm_handle_papr_hcall handle PAPR hypercall kvm_handle_papr_hcall handle PAPR hypercall kvm_handle_papr_hcall handle PAPR hypercall kvm_handle_papr_hcall handle PAPR hypercall kvm_handle_papr_hcall handle PAPR hypercall kvm_handle_papr_hcall handle PAPR hypercall After: kvm_handle_papr_hcall 0x3a8 kvm_handle_papr_hcall 0x3ac kvm_handle_papr_hcall 0x108 kvm_handle_papr_hcall 0x104 kvm_handle_papr_hcall 0x104 kvm_handle_papr_hcall 0x108 Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220325223316.276494-1-farosas@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * spapr: Move nested KVM hypercalls under a TCG only config.Fabiano Rosas2022-04-201-6/+20
| | | | | | | | | | | | | | | | | | | | These are the spapr virtual hypervisor implementation of the nested KVM API. They only make sense when running with TCG. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Message-Id: <20220325221113.255834-3-farosas@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * spapr: Move hypercall_register_softmmuFabiano Rosas2022-04-201-25/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | I'm moving this because next patch will add more code under the ifdef and it will be cleaner if we keep them together. Also switch the ifdef branches to make it more convenient to add code under CONFIG_TCG in the next patch. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Message-Id: <20220325221113.255834-2-farosas@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * ppc/pnv: Remove useless checks in set_irq handlersCédric Le Goater2022-04-201-10/+0
| | | | | | | | | | | | | | Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220323072846.1780212-6-clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * ppc/pnv: Remove PnvPsiClas::irq_setCédric Le Goater2022-04-202-21/+6
| | | | | | | | | | | | | | | | | | | | All devices raising PSI interrupts are now converted to use GPIO lines and the pnv_psi_irq_set() routines have become useless. Drop them. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220323072846.1780212-5-clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * ppc/pnv: Remove PnvOCC::psi linkCédric Le Goater2022-04-203-23/+12
| | | | | | | | | | | | | | | | | | | | | | Use an anonymous output GPIO line to connect the OCC device with the PSIHB device and raise the appropriate PSI IRQ line depending on the processor model. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220323072846.1780212-4-clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * ppc/pnv: Remove PnvLpcController::psi linkCédric Le Goater2022-04-204-27/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create an anonymous output GPIO line to connect the LPC device with the PSIHB device and raise the appropriate PSI IRQ line depending on the processor model. A temporary __pnv_psi_irq_set() routine is introduced to handle the transition. It will be removed when all devices raising PSI interrupts are converted to use GPIOs. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220323072846.1780212-3-clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * ppc/pnv: Fix PSI IRQ definitionCédric Le Goater2022-04-202-8/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On HW, the PSI and FSP interrupt levels are muxed under the same interrupt number. For coding reasons, an extra IRQ number was introduced to index register values in an array. It increased the count of IRQs which do not fit in the PSI IRQ range anymore. The PSI and FSP interrupts should be modeled with an extra level of GPIO lines but since QEMU does not support them, simply drop the extra number to stay within the IRQ range. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220323072846.1780212-2-clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * ppc/spapr/ddw: Add 2M pagesizeAlexey Kardashevskiy2022-04-202-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Recently the LoPAPR spec got a new 2MB pagesize to support in Dynamic DMA Windows API (DDW), this adds the new flag. Linux supports it since https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=38727311871 Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Message-Id: <20220321071945.918669-1-aik@ozlabs.ru> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| * ppc/pnv: Update skiboot to v7.0Joel Stanley2022-04-202-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is skiboot 7.0 (commit 76b349cf7b40). Built using gcc 11.2.0 and binutils 2.38. Changes since the previous version: Christophe Lombard (15): npu2: move opal api pau: introduce support rainier: detect pau devices pau: assign bars pau: create phb pau: enabling opencapi pau: translation layer configuration pau: enable interrupt on error pau: complete phb ops pau: hmi scom dump pau: phy init pau: link training pau: update current opal call functions pau: mmio invalidates pau: Add support for OpenCAPI Persistent Memory devices. Cédric Le Goater (4): xive/p10: Fix xive_special_cache_check when DEBUG=1 xive/p10: Fix mismatch errors when DEBUG=1 interrupts: Do not advertise XICS support on P10 skiboot v6.6.6 release notes Frederic Barrat (6): phb4/5: Escalate page-level TCE kills npu3: Remove GPU support on Swift phb5: Remove obsolete capp-related properties xive/p10:: Declare xive2 DT node as an interrupt-controller skiboot v6.0.24 release notes opal-api: Drop diagnostics data type symbol for PHB5 Michael Ellerman (3): external/mambo: Print more info when the kernel is too big doc: Make it clear all existing platforms use Power9N docs: Add Swift, Mowgli & Rainier Nicholas Piggin (12): external/mambo: Updates for POWER10 configuration for DD2.0 external/mambo: Updates POWER9 SIM_CTRL1 to remove hardware atomic RC external/mambo: Add POWER10 small-core mode HBRT: fix clobbered r16 when host services handlers are called interrupts: add_opal_interrupts avoid NULL dereference on P10 mambo cpu: cpu_idle_job SMT priority fix cpu: add debug check in cpu_relax asm/head: Fix P10 HILE for little endian build phb4: annotate tbl_pest with endian types Remove support for POWER8 DD1 phb3: make endian-clean flash: AST BMC endian fixes Nick Child (1): secvar: Free md context on hash error Ryan Grimm (1): AWAN simulator support for P10 Vasant Hegde (5): ci: Bump qemu version hello_world: Add p10 mambo tests skiboot v6.7.3 release notes skiboot v6.8.1 release notes skiboot v7.0 release notes Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
* | Merge tag 'pull-tcg-20220420' of https://gitlab.com/rth7680/qemu into stagingRichard Henderson2022-04-2013-18/+31
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cleanup sysemu/tcg.h usage. Fix indirect lowering vs cond branches Remove ATOMIC_MMU_IDX Add tcg_constant_ptr # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmJgW38dHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV8tpggApfg2CDI0bRMDBh0g # 04/xwNnzHuSa84/ocMOMUfD5pvBblUmeTH8fAwqcAPDM/EEZwWZl2V1bYzuIrbmR # 8zV+r1cOenDF5Tz8PWfy8XssinTVtTWh/TE0XNV9R/SbEM9eMsjHNu5osKVuLuq1 # rnHWZf8LuY7xGsy4GYqPN0dLE6HtQOfpj/eLGRAj9mZ7re0jKeWg3GdxYoiYDmks # NKmNHYcWD+SjjFvXlOafniQsHbBZmQc/qp7AShG/+VcYY9o1VfncWD6I2dV13RdB # N7++ZhGyQR4NOVo6CN1zLKhfuJqzH2q+qJ7vQ3xtXNAk53LGQ91zjoE+3KaJTrcy # dmnLUw== # =aKdS # -----END PGP SIGNATURE----- # gpg: Signature made Wed 20 Apr 2022 12:14:07 PM PDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate] * tag 'pull-tcg-20220420' of https://gitlab.com/rth7680/qemu: tcg: Add tcg_constant_ptr accel/tcg: Remove ATOMIC_MMU_IDX tcg: Fix indirect lowering vs TCG_OPF_COND_BRANCH Don't include sysemu/tcg.h if it is not necessary Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg: Add tcg_constant_ptrRichard Henderson2022-04-201-0/+2
| | | | | | | | | | | | | | | | | | | | | Similar to tcg_const_ptr, defer to tcg_constant_{i32,i64}. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | accel/tcg: Remove ATOMIC_MMU_IDXRichard Henderson2022-04-202-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | The last use of this macro was removed in f3e182b10013 ("accel/tcg: Push trace info building into atomic_common.c.inc") Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg: Fix indirect lowering vs TCG_OPF_COND_BRANCHRichard Henderson2022-04-202-7/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With TCG_OPF_COND_BRANCH, we extended the lifetimes of globals across extended basic blocks. This means that the liveness computed in pass 1 does not kill globals in the same way as normal temps. Introduce TYPE_EBB to match this lifetime, so that we get correct register allocation for the temps that we introduce during the indirect lowering pass. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Fixes: b4cb76e6208 ("tcg: Do not kill globals at conditional branches") Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | Don't include sysemu/tcg.h if it is not necessaryThomas Huth2022-04-209-9/+0
| |/ | | | | | | | | | | | | | | | | | | | | This header only defines the tcg_allowed variable and the tcg_enabled() function - which are not required in many files that include this header. Drop the #include statement there. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20220315144107.1012530-1-thuth@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | Merge tag 'pull-log-20220420' of https://gitlab.com/rth7680/qemu into stagingRichard Henderson2022-04-2049-660/+725
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clean up log locking. Use the FILE* from qemu_log_trylock more often. Support per-thread log files with -d tid. # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmJgStUdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV+c9Af/ZXnKe6bz5yjXy1mS # mNIBJUPKrz1RXFfJxuCfEDWrtNc/gvQyvc3weZG5X0cXpiczeWA5V/9xbE9hu5gV # 4rePiIHWmOrais6GZlqEu2F8P3/XyqdPHtcdBfa1hDneixtpqMHCqnh36nQjHyiU # ogFxEJ/M9tTwhuWZrXe/JSYAiALEDYMK9bk4RUMOP1c4v37rXqUNOAM1IPhfxLL/ # bK9DQMpz5oUNsWWaqBQ2wQWHkNTOpUEkKGQv0xcQF5SdpYwaxakW9B7/h4QSeOUn # oY6MFTmkJ4BPrLnkcubn+3PICc9LW0OFuzNnUdMCbeqVbjAUQrdMDalKpy4uNFv9 # U1VqHg== # =Mt5s # -----END PGP SIGNATURE----- # gpg: Signature made Wed 20 Apr 2022 11:03:01 AM PDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate] * tag 'pull-log-20220420' of https://gitlab.com/rth7680/qemu: (39 commits) util/log: Support per-thread log files util/log: Limit RCUCloseFILE to file closing util/log: Rename QemuLogFile to RCUCloseFILE util/log: Combine two logfile closes util/log: Hoist the eval of is_daemonized in qemu_set_log_internal util/log: Rename qemu_logfile_mutex to global_mutex util/log: Rename qemu_logfile to global_file util/log: Rename logfilename to global_filename util/log: Remove qemu_log_close softmmu: Use qemu_set_log_filename_flags linux-user: Use qemu_set_log_filename_flags bsd-user: Use qemu_set_log_filename_flags util/log: Introduce qemu_set_log_filename_flags sysemu/os-win32: Test for and use _lock_file/_unlock_file include/qemu/log: Move entire implementation out-of-line include/exec/log: Do not reference QemuLogFile directly tests/unit: Do not reference QemuLogFile directly linux-user: Expand log_page_dump inline bsd-user: Expand log_page_dump inline util/log: Drop call to setvbuf ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * util/log: Support per-thread log filesRichard Henderson2022-04-202-36/+128
| | | | | | | | | | | | | | | | | | | | | | | | | | Add a new log flag, tid, to turn this feature on. Require the log filename to be set, and to contain %d. Do not allow tid to be turned off once it is on, nor let the filename be change thereafter. This avoids the need for signalling each thread to re-open on a name change. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220417183019.755276-40-richard.henderson@linaro.org>
| * util/log: Limit RCUCloseFILE to file closingRichard Henderson2022-04-201-36/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | Use FILE* for global_file. We can perform an rcu_read on that just as easily as RCUCloseFILE*. This simplifies a couple of places, where previously we required taking the rcu_read_lock simply to avoid racing to dereference RCUCloseFile->fd. Only allocate the RCUCloseFile prior to call_rcu. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220417183019.755276-39-richard.henderson@linaro.org>