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* Merge remote-tracking branch 'remotes/mst/tags/for_upstream3' into stagingPeter Maydell2021-07-1643-42/+949
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pc,pci,virtio: lots of new features Lots of last minute stuff. vhost-user-i2c. vhost-vsock SOCK_SEQPACKET support. IOMMU bypass. ACPI based pci hotplug. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Fri 16 Jul 2021 16:11:27 BST # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream3: vhost-vsock: SOCK_SEQPACKET feature bit support docs: Add documentation for iommu bypass hw/i386/acpi-build: Add IVRS support to bypass iommu hw/i386/acpi-build: Add DMAR support to bypass iommu hw/arm/virt-acpi-build: Add IORT support to bypass SMMUv3 hw/pci: Add pci_bus_range() to get PCI bus number range hw/i386: Add a default_bus_bypass_iommu pc machine option hw/arm/virt: Add default_bus_bypass_iommu machine option hw/pxb: Add a bypass iommu property hw/pci/pci_host: Allow PCI host to bypass iommu docs: Add '-device intel-iommu' entry hw/virtio: add vhost-user-i2c-pci boilerplate hw/virtio: add boilerplate for vhost-user-i2c device bios-tables-test: Update golden binaries hw/acpi/ich9: Set ACPI PCI hot-plug as default on Q35 bios-tables-test: Allow changes in DSDT ACPI tables hw/pci/pcie: Do not set HPC flag if acpihp is used hw/acpi/ich9: Enable ACPI PCI hot-plug hw/i386/acpi-build: Add ACPI PCI hot-plug methods to Q35 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * vhost-vsock: SOCK_SEQPACKET feature bit supportArseny Krasnov2021-07-161-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | This adds processing of VIRTIO_VSOCK_F_SEQPACKET features bit. Guest negotiates it with vhost, thus both will know that SOCK_SEQPACKET supported by peer. Signed-off-by: Arseny Krasnov <arseny.krasnov@kaspersky.com> Message-Id: <20210622144747.2949134-1-arseny.krasnov@kaspersky.com> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * docs: Add documentation for iommu bypassXingang Wang2021-07-161-0/+89
| | | | | | | | | | | | | | Signed-off-by: Xingang Wang <wangxingang5@huawei.com> Message-Id: <1625748919-52456-10-git-send-email-wangxingang5@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * hw/i386/acpi-build: Add IVRS support to bypass iommuXingang Wang2021-07-161-1/+1
| | | | | | | | | | | | | | | | | | Check bypass_iommu to exclude the devices which will bypass iommu. Signed-off-by: Xingang Wang <wangxingang5@huawei.com> Message-Id: <1625748919-52456-9-git-send-email-wangxingang5@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * hw/i386/acpi-build: Add DMAR support to bypass iommuXingang Wang2021-07-161-2/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In DMAR table, the drhd is set to cover all PCI devices when intel_iommu is on. To support bypass iommu feature, we need to walk the PCI bus with bypass_iommu disabled and add explicit scope data in DMAR drhd structure. /mnt/sdb/wxg/qemu-next/qemu/build/x86_64-softmmu/qemu-system-x86_64 \ -machine q35,accel=kvm,default_bus_bypass_iommu=true \ -cpu host \ -m 16G \ -smp 36,sockets=2,cores=18,threads=1 \ -device pxb-pcie,bus_nr=0x10,id=pci.10,bus=pcie.0,addr=0x3 \ -device pxb-pcie,bus_nr=0x20,id=pci.20,bus=pcie.0,addr=0x4,bypass_iommu=true \ -device pcie-root-port,port=0x1,chassis=1,id=pci.11,bus=pci.10,addr=0x0 \ -device pcie-root-port,port=0x2,chassis=2,id=pci.21,bus=pci.20,addr=0x0 \ -device virtio-scsi-pci,id=scsi0,bus=pci.11,addr=0x0 \ -device virtio-scsi-pci,id=scsi1,bus=pci.21,addr=0x0 \ -drive file=/mnt/sdb/wxg/fedora-48g.qcow2,format=qcow2,if=none,id=drive-scsi0-0-0-0,cache=none,aio=native \ -device scsi-hd,bus=scsi1.0,channel=0,scsi-id=0,lun=0,drive=drive-scsi0-0-0-0,id=scsi0-0-0-0,bootindex=1 \ -device intel-iommu \ -nographic \ And we get the guest configuration: ~ lspci -vt -+-[0000:20]---00.0-[21]----00.0 Red Hat, Inc. Virtio SCSI +-[0000:10]---00.0-[11]----00.0 Red Hat, Inc. Virtio SCSI \-[0000:00]-+-00.0 Intel Corporation 82G33/G31/P35/P31 Express DRAM Controller +-01.0 Device 1234:1111 +-02.0 Intel Corporation 82574L Gigabit Network Connection +-03.0 Red Hat, Inc. QEMU PCIe Expander bridge +-04.0 Red Hat, Inc. QEMU PCIe Expander bridge +-1f.0 Intel Corporation 82801IB (ICH9) LPC Interface Controller +-1f.2 Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA Controller [AHCI mode] \-1f.3 Intel Corporation 82801I (ICH9 Family) SMBus Controller With bypass_iommu enabled on root bus, the attached devices will bypass iommu: /sys/class/iommu/dmar0 ├── devices │   ├── 0000:10:00.0 -> ../../../../pci0000:10/0000:10:00.0 │   └── 0000:11:00.0 -> ../../../../pci0000:10/0000:10:00.0/0000:11:00.0 Signed-off-by: Xingang Wang <wangxingang5@huawei.com> Message-Id: <1625748919-52456-8-git-send-email-wangxingang5@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * hw/arm/virt-acpi-build: Add IORT support to bypass SMMUv3Xingang Wang2021-07-161-11/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When we build IORT table with SMMUv3 and bypass iommu feature enabled, we can no longer setup one map from RC to SMMUv3 covering the whole RIDs. We need to walk the PCI bus and check whether the root bus will bypass iommu, setup RC -> SMMUv3 -> ITS map for RC which will not bypass iommu. When a SMMUv3 node exist, we setup the idmap from SMMUv3 to ITS covering the whole RIDs, and only modify the map from RC to SMMUv3. We build RC -> SMMUv3 -> ITS map for root bus with bypass_iommu disabled, and build idmap from RC to ITS directly for the rest of the whole RID space. For example we run qemu with command line: qemu/build/aarch64-softmmu/qemu-system-aarch64 \ -kernel arch/arm64/boot/Image \ -enable-kvm \ -cpu host \ -m 8G \ -smp 8,sockets=2,cores=4,threads=1 \ -machine virt,kernel_irqchip=on,gic-version=3,iommu=smmuv3,default_bus_bypass_iommu=true \ -drive file=./QEMU_EFI-pflash.raw,if=pflash,format=raw,unit=0,readonly=on \ -device pxb-pcie,bus_nr=0x10,id=pci.10,bus=pcie.0,addr=0x3.0x1 \ -device pxb-pcie,bus_nr=0x20,id=pci.20,bus=pcie.0,addr=0x3.0x2,bypass_iommu=true \ -device pcie-root-port,port=0x20,chassis=1,id=pci.1,bus=pcie.0,addr=0x2 \ -device pcie-root-port,port=0x20,chassis=11,id=pci.11,bus=pci.10,addr=0x1 \ -device pcie-root-port,port=0x20,chassis=21,id=pci.21,bus=pci.20,addr=0x1 \ -device virtio-scsi-pci,id=scsi0,bus=pci.1,addr=0x1 \ -device virtio-scsi-pci,id=scsi1,bus=pci.11,addr=0x1 \ -device virtio-scsi-pci,id=scsi2,bus=pci.21,addr=0x1 \ -initrd /mnt/davinci/wxg/kill-linux/rootfs/mfs.cpio.gz \ -nographic \ -append "rdinit=init console=ttyAMA0 earlycon=pl011,0x9000000 nokaslr" \ And we get guest configuration: -+-[0000:20]---01.0-[21]-- +-[0000:10]---01.0-[11]-- \-[0000:00]-+-00.0 Device 1b36:0008 +-01.0 Device 1af4:1000 \-02.0-[01]-- With bypass_iommu enabled, the attached devices will bypass iommu. /sys/class/iommu/smmu3.0x0000000009050000/ |-- device -> ../../../arm-smmu-v3.0.auto |-- devices | `-- 0000:10:01.0 -> ../../../../../pci0000:10/0000:10:01.0 Signed-off-by: Xingang Wang <wangxingang5@huawei.com> Message-Id: <1625748919-52456-7-git-send-email-wangxingang5@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * hw/pci: Add pci_bus_range() to get PCI bus number rangeXingang Wang2021-07-162-0/+17
| | | | | | | | | | | | | | | | | | | | This helps to get the min and max bus number of a PCI bus hierarchy. Signed-off-by: Xingang Wang <wangxingang5@huawei.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-Id: <1625748919-52456-6-git-send-email-wangxingang5@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * hw/i386: Add a default_bus_bypass_iommu pc machine optionXingang Wang2021-07-163-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | Add a default_bus_bypass_iommu pc machine option to enable/disable bypass_iommu for default root bus. The option is disabled by default and can be enabled with: $QEMU -machine q35,default_bus_bypass_iommu=true Signed-off-by: Xingang Wang <wangxingang5@huawei.com> Message-Id: <1625748919-52456-5-git-send-email-wangxingang5@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * hw/arm/virt: Add default_bus_bypass_iommu machine optionXingang Wang2021-07-162-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | Add a default_bus_bypass_iommu machine option to enable/disable bypass_iommu for default root bus. The option is disabled by default and can be enabled with: $QEMU -machine virt,iommu=smmuv3,default_bus_bypass_iommu=true Signed-off-by: Xingang Wang <wangxingang5@huawei.com> Message-Id: <1625748919-52456-4-git-send-email-wangxingang5@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * hw/pxb: Add a bypass iommu propertyXingang Wang2021-07-161-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Add a bypass_iommu property for pci_expander_bridge, the property is used to indicate whether pxb root bus will bypass iommu. By default the bypass_iommu is disabled, and it can be enabled with: qemu -device pxb-pcie,bus_nr=0x10,addr=0x1,bypass_iommu=true Signed-off-by: Xingang Wang <wangxingang5@huawei.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-Id: <1625748919-52456-3-git-send-email-wangxingang5@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * hw/pci/pci_host: Allow PCI host to bypass iommuXingang Wang2021-07-164-1/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | Add a new bypass_iommu property for PCI host and use it to check whether devices attached to the PCI root bus will bypass iommu. In pci_device_iommu_address_space(), check the property and avoid getting iommu address space for devices bypass iommu. Signed-off-by: Xingang Wang <wangxingang5@huawei.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-Id: <1625748919-52456-2-git-send-email-wangxingang5@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * docs: Add '-device intel-iommu' entryPeter Xu2021-07-161-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The parameters of intel-iommu device are non-trivial to understand. Add an entry for it so that people can reference to it when using. There're actually a few more options there, but I hide them explicitly because they shouldn't be used by normal QEMU users. Cc: Chao Yang <chayang@redhat.com> Cc: Lei Yang <leiyang@redhat.com> Cc: Jing Zhao <jinzhao@redhat.com> Cc: Jason Wang <jasowang@redhat.com> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Alex Williamson <alex.williamson@redhat.com> Reviewed-by: Jason Wang <jasowang@redhat.com> Reviewed-by: Yi Liu <yi.l.liu@intel.com> Signed-off-by: Peter Xu <peterx@redhat.com> Message-Id: <20210707154114.197580-1-peterx@redhat.com> Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * hw/virtio: add vhost-user-i2c-pci boilerplateViresh Kumar2021-07-162-0/+70
| | | | | | | | | | | | | | | | | | | | | | | | This allows is to instantiate a vhost-user-i2c device as part of a PCI bus. It is mostly boilerplate which looks pretty similar to the vhost-user-fs-pci device. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Message-Id: <8a083eaa57d93feaab12acd1f94b225879212f20.1625806763.git.viresh.kumar@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * hw/virtio: add boilerplate for vhost-user-i2c deviceViresh Kumar2021-07-164-0/+322
| | | | | | | | | | | | | | | | | | | | This creates the QEMU side of the vhost-user-i2c device which connects to the remote daemon. It is based of vhost-user-fs code. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Message-Id: <e80591b52fea4b51631818bb92a798a3daf90399.1625806763.git.viresh.kumar@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * bios-tables-test: Update golden binariesJulia Suvorova2021-07-1612-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add ACPI hot-plug registers to DSDT Q35 tables. Changes in the tables: + Scope (_SB.PCI0) + { + OperationRegion (PCST, SystemIO, 0x0CC4, 0x08) + Field (PCST, DWordAcc, NoLock, WriteAsZeros) + { + PCIU, 32, + PCID, 32 + } + + OperationRegion (SEJ, SystemIO, 0x0CCC, 0x04) + Field (SEJ, DWordAcc, NoLock, WriteAsZeros) + { + B0EJ, 32 + } + + OperationRegion (BNMR, SystemIO, 0x0CD4, 0x08) + Field (BNMR, DWordAcc, NoLock, WriteAsZeros) + { + BNUM, 32, + PIDX, 32 + } + + Mutex (BLCK, 0x00) + Method (PCEJ, 2, NotSerialized) + { + Acquire (BLCK, 0xFFFF) + BNUM = Arg0 + B0EJ = (One << Arg1) + Release (BLCK) + Return (Zero) + } + + Method (AIDX, 2, NotSerialized) + { + Acquire (BLCK, 0xFFFF) + BNUM = Arg0 + PIDX = (One << Arg1) + Local0 = PIDX /* \_SB_.PCI0.PIDX */ + Release (BLCK) + Return (Local0) + } + + Method (PDSM, 6, Serialized) + { + If ((Arg0 == ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */)) + { + Local0 = AIDX (Arg4, Arg5) + If ((Arg2 == Zero)) + { + If ((Arg1 == 0x02)) + { + If (!((Local0 == Zero) | (Local0 == 0xFFFFFFFF))) + { + Return (Buffer (One) + { + 0x81 // . + }) + } + } + + Return (Buffer (One) + { + 0x00 // . + }) + } + ElseIf ((Arg2 == 0x07)) + { + Local1 = Package (0x02) + { + Zero, + "" + } + Local1 [Zero] = Local0 + Return (Local1) + } + } + } + } + ... Scope (_GPE) { Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID + Method (_E01, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + Acquire (\_SB.PCI0.BLCK, 0xFFFF) + \_SB.PCI0.PCNT () + Release (\_SB.PCI0.BLCK) + } ... + + Device (PHPR) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "PCI Hotplug resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0CC4, // Range Minimum + 0x0CC4, // Range Maximum + 0x01, // Alignment + 0x18, // Length + ) + }) + } } ... And if there is a port in configuration: Device (S10) { Name (_ADR, 0x00020000) // _ADR: Address + Name (BSEL, Zero) + Device (S00) + { + Name (_SUN, Zero) // _SUN: Slot User Number + Name (_ADR, Zero) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + + Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method + { + Return (PDSM (Arg0, Arg1, Arg2, Arg3, BSEL, _SUN)) + } + } + ... + Method (DVNT, 2, NotSerialized) + { + If ((Arg0 & One)) + { + Notify (S00, Arg1) + } ... Signed-off-by: Julia Suvorova <jusual@redhat.com> Message-Id: <20210713004205.775386-7-jusual@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * hw/acpi/ich9: Set ACPI PCI hot-plug as default on Q35Julia Suvorova2021-07-162-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Q35 has three different types of PCI devices hot-plug: PCIe Native, SHPC Native and ACPI hot-plug. This patch changes the default choice for cold-plugged bridges from PCIe Native to ACPI Hot-plug with ability to use SHPC and PCIe Native for hot-plugged bridges. This is a list of the PCIe Native hot-plug issues that led to this change: * no racy behavior during boot (see 110c477c2ed) * no delay during deleting - after the actual power off software must wait at least 1 second before indicating about it. This case is quite important for users, it even has its own bug: https://bugzilla.redhat.com/show_bug.cgi?id=1594168 * no timer-based behavior - in addition to the previous example, the attention button has a 5-second waiting period, during which the operation can be canceled with a second press. While this looks fine for manual button control, automation will result in the need to queue or drop events, and the software receiving events in all sort of unspecified combinations of attention/power indicator states, which is racy and uppredictable. * fixes: * https://bugzilla.redhat.com/show_bug.cgi?id=1752465 * https://bugzilla.redhat.com/show_bug.cgi?id=1690256 To return to PCIe Native hot-plug: -global ICH9-LPC.acpi-pci-hotplug-with-bridge-support=off Known issue: older linux guests need the following flag to allow hotplugged pci express devices to use io: -device pcie-root-port,io-reserve=4096. io is unusual for pci express so this seems minor. We'll fix this by a follow up patch. Signed-off-by: Julia Suvorova <jusual@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20210713004205.775386-6-jusual@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
| * bios-tables-test: Allow changes in DSDT ACPI tablesJulia Suvorova2021-07-161-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | All DSDT Q35 tables will be modified because ACPI hot-plug is enabled by default. Signed-off-by: Julia Suvorova <jusual@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Message-Id: <20210713004205.775386-5-jusual@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * hw/pci/pcie: Do not set HPC flag if acpihp is usedJulia Suvorova2021-07-166-3/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of changing the hot-plug type in _OSC register, do not set the 'Hot-Plug Capable' flag. This way guest will choose ACPI hot-plug if it is preferred and leave the option to use SHPC with pcie-pci-bridge. The ability to control hot-plug for each downstream port is retained, while 'hotplug=off' on the port means all hot-plug types are disabled. Signed-off-by: Julia Suvorova <jusual@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20210713004205.775386-4-jusual@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * hw/acpi/ich9: Enable ACPI PCI hot-plugJulia Suvorova2021-07-166-6/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | Add acpi_pcihp to ich9_pm as part of 'acpi-pci-hotplug-with-bridge-support' option. Set default to false. Signed-off-by: Julia Suvorova <jusual@redhat.com> Signed-off-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20210713004205.775386-3-jusual@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
| * hw/i386/acpi-build: Add ACPI PCI hot-plug methods to Q35Julia Suvorova2021-07-166-16/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | Implement notifications and gpe to support q35 ACPI PCI hot-plug. Use 0xcc4 - 0xcd7 range for 'acpi-pci-hotplug' io ports. Signed-off-by: Julia Suvorova <jusual@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Message-Id: <20210713004205.775386-2-jusual@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
* | Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-07-15' into ↵Peter Maydell2021-07-164-1/+5
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging QAPI patches patches for 2021-07-15 # gpg: Signature made Thu 15 Jul 2021 13:30:14 BST # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-qapi-2021-07-15: qapi: Fix crash on missing enum member name Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | qapi: Fix crash on missing enum member nameMarkus Armbruster2021-07-154-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | New test case enum-dict-no-name.json crashes: $ python3 scripts/qapi-gen.py tests/qapi-schema/enum-dict-no-name.json Traceback (most recent call last): [...] File "/work/armbru/qemu/scripts/qapi/expr.py", line 458, in check_enum member_name = member['name'] KeyError: 'name' Root cause: we try to retrieve member 'name' before we check for missing members. With that fixed, we get the expected error "'data' member misses key 'name'". Fixes: 0825f62c842f2c07c5471391c6d7fd3f4fe83732 Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20210616072121.626431-1-armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: John Snow <jsnow@redhat.com>
* | | Merge remote-tracking branch ↵Peter Maydell2021-07-1611-75/+257
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/alistair/tags/pull-riscv-to-apply-20210715' into staging Fourth RISC-V PR for 6.1 release - Code cleanups - Documentation improvements - Hypervisor extension improvements with hideleg and hedeleg - sifive_u fixes - OpenTitan register layout updates - Fix coverity issue # gpg: Signature made Thu 15 Jul 2021 08:14:00 BST # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-to-apply-20210715: hw/riscv/boot: Check the error of fdt_pack() hw/riscv: opentitan: Add the flash alias hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri char: ibex_uart: Update the register layout hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned hw/riscv: sifive_u: Correct the CLINT timebase frequency docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot target/riscv: hardwire bits in hideleg and hedeleg docs/system: riscv: Add documentation for virt machine docs/system: riscv: Fix CLINT name in the sifive_u doc target/riscv: csr: Remove redundant check in fp csr read/write routines target/riscv: pmp: Fix some typos Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hw/riscv/boot: Check the error of fdt_pack()Alistair Francis2021-07-151-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Coverity reports that we don't check the error result of fdt_pack(), so let's save the result and assert that it is 0. Fixes: Coverity CID 1458136 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 07325315b49d5555269f76094e4bc5296e0643b9.1626303527.git.alistair.francis@wdc.com
| * | hw/riscv: opentitan: Add the flash aliasAlistair Francis2021-07-152-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | OpenTitan has an alias of flash avaliable which is called virtual flash. Add support for that in the QEMU model. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: c9cfbd2dd840fd0076877b8ea4d6dcfce60db5e9.1625801868.git.alistair.francis@wdc.com
| * | hw/riscv: opentitan: Add the unimplement rv_core_ibex_periAlistair Francis2021-07-152-0/+4
| | | | | | | | | | | | | | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: ed707782e84118e1b06a32fd79b70fecfb54ff82.1625801868.git.alistair.francis@wdc.com
| * | char: ibex_uart: Update the register layoutAlistair Francis2021-07-151-9/+10
| | | | | | | | | | | | | | | | | | | | | | | | Update the register layout to match the latest OpenTitan bitstream. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 25c8377d32f3e0f0a1a862c8a5092f8a9e3f9928.1625801868.git.alistair.francis@wdc.com
| * | hw/riscv: sifive_u: Make sure firmware info is 8-byte alignedBin Meng2021-07-151-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the firmware dynamic info (fw_dyn) is put right after the reset vector, which is not 8-byte aligned on RV64. OpenSBI fw_dynamic uses ld to read contents from 'struct fw_dynamic_info', which expects fw_dyn to be on the 8-byte boundary, otherwise the misaligned load exception may happen. Fortunately this does not cause any issue on QEMU, as QEMU does support misaligned load. RV32 does not have any issue as it is 4-byte aligned already. Change to make sure it is 8-byte aligned which works for both RV32 and RV64. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210708143319.10441-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | hw/riscv: sifive_u: Correct the CLINT timebase frequencyBin Meng2021-07-151-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present the CLINT timebase frequency is set to 10MHz on sifive_u, but on the real hardware the timebase frequency is 1Mhz. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210706102616.1922469-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | docs/system: riscv: Update Microchip Icicle Kit for direct kernel bootBin Meng2021-07-151-7/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a new section in the documentation to demonstrate how to use the new direct kernel boot feature for Microchip Icicle Kit, other than the HSS bootflow, using an upstream U-Boot v2021.07 image as an example. It also updates the truth table to have a new '-dtb' column which is required by direct kernel boot. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210706095045.1917913-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | target/riscv: hardwire bits in hideleg and hedelegJose Martins2021-07-151-23/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The specification mandates for certain bits to be hardwired in the hypervisor delegation registers. This was not being enforced. Signed-off-by: Jose Martins <josemartins90@gmail.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210522155902.374439-1-josemartins90@gmail.com [ Changes by AF: - Improve indentation - Convert delegable_excps to a #define to avoid failures with GCC 8 ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | docs/system: riscv: Add documentation for virt machineBin Meng2021-07-152-0/+139
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds detailed documentation for RISC-V `virt` machine, including the following information: - Supported devices - Hardware configuration information - Boot options - Running Linux kernel - Running U-Boot Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210627142816.19789-2-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | docs/system: riscv: Fix CLINT name in the sifive_u docBin Meng2021-07-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | It's Core *Local* Interruptor, not 'Level'. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210627142816.19789-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | target/riscv: csr: Remove redundant check in fp csr read/write routinesBin Meng2021-07-151-24/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following check: if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -RISCV_EXCP_ILLEGAL_INST; } is redundant in fflags/frm/fcsr read/write routines, as the check was already done in fs(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210627120604.11116-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | target/riscv: pmp: Fix some typosBin Meng2021-07-151-5/+5
| |/ | | | | | | | | | | | | | | | | | | | | %s/CSP/CSR %s/thie/the Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210627115716.3552-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* | Merge remote-tracking branch 'remotes/awilliam/tags/vfio-update-20210714.0' ↵Peter Maydell2021-07-153-3/+15
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging VFIO update 2021-07-14 * Coverity fix to discard listener (David Hildenbrand) * MSI-X PBA quirk for BAIDU VFs, additional helper use cases (Cai Huoqing) # gpg: Signature made Wed 14 Jul 2021 22:31:35 BST # gpg: using RSA key 42F6C04E540BD1A99E7B8A90239B9B6E3BB08B22 # gpg: issuer "alex.williamson@redhat.com" # gpg: Good signature from "Alex Williamson <alex.williamson@redhat.com>" [full] # gpg: aka "Alex Williamson <alex@shazbot.org>" [full] # gpg: aka "Alex Williamson <alwillia@redhat.com>" [full] # gpg: aka "Alex Williamson <alex.l.williamson@gmail.com>" [full] # Primary key fingerprint: 42F6 C04E 540B D1A9 9E7B 8A90 239B 9B6E 3BB0 8B22 * remotes/awilliam/tags/vfio-update-20210714.0: vfio/pci: Add pba_offset PCI quirk for BAIDU KUNLUN AI processor vfio/pci: Change to use vfio_pci_is() vfio: Fix CID 1458134 in vfio_register_ram_discard_listener() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | vfio/pci: Add pba_offset PCI quirk for BAIDU KUNLUN AI processorCai Huoqing2021-07-142-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix pba_offset initialization value for BAIDU KUNLUN Virtual Function device. The KUNLUN hardware returns an incorrect value for the VF PBA offset, and add a quirk to instead return a hardcoded value of 0xb400. Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Link: https://lore.kernel.org/r/20210713093743.942-1-caihuoqing@baidu.com [aw: comment & whitespace tuning] Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
| * | vfio/pci: Change to use vfio_pci_is()Cai Huoqing2021-07-141-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Make use of vfio_pci_is() helper function. Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Link: https://lore.kernel.org/r/20210713014831.742-1-caihuoqing@baidu.com [aw: commit log wording] Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
| * | vfio: Fix CID 1458134 in vfio_register_ram_discard_listener()David Hildenbrand2021-07-141-1/+2
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CID 1458134: Integer handling issues (BAD_SHIFT) In expression "1 << ctz64(container->pgsizes)", left shifting by more than 31 bits has undefined behavior. The shift amount, "ctz64(container->pgsizes)", is 64. Commit 5e3b981c330c ("vfio: Support for RamDiscardManager in the !vIOMMU case") added an assertion that our granularity is at least as big as the page size. Although unlikely, we could have a page size that does not fit into 32 bit. In that case, we'd try shifting by more than 31 bit. Let's use 1ULL instead and make sure we're not shifting by more than 63 bit by asserting that any bit in container->pgsizes is set. Fixes: CID 1458134 Cc: Alex Williamson <alex.williamson@redhat.com> Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: "Michael S. Tsirkin" <mst@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Dr. David Alan Gilbert <dgilbert@redhat.com> Cc: Igor Mammedov <imammedo@redhat.com> Cc: Pankaj Gupta <pankaj.gupta.linux@gmail.com> Cc: Peter Xu <peterx@redhat.com> Cc: Auger Eric <eric.auger@redhat.com> Cc: Wei Yang <richard.weiyang@linux.alibaba.com> Cc: teawater <teawaterz@linux.alibaba.com> Cc: Marek Kedzierski <mkedzier@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Pankaj Gupta <pankaj.gupta@ionos.com> Link: https://lore.kernel.org/r/20210712083135.15755-1-david@redhat.com Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
* | Merge remote-tracking branch ↵Peter Maydell2021-07-1525-913/+865
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/berrange-gitlab/tags/crypto-and-more-pull-request' into staging Merge crypto updates and misc fixes * Introduce a GNUTLS backend for crypto algorithms * Change crypto library preference gnutls > gcrypt > nettle > built-in * Remove built-in DES impl * Remove XTS mode from built-in AES impl * Fix seccomp rules to allow resource info getters * Fix migration performance test * Use GDateTime in io/ and net/rocker/ code * Improve docs for -smp # gpg: Signature made Wed 14 Jul 2021 15:08:00 BST # gpg: using RSA key DAF3A6FDB26B62912D0E8E3FBE86EBB415104FDF # gpg: Good signature from "Daniel P. Berrange <dan@berrange.com>" [full] # gpg: aka "Daniel P. Berrange <berrange@redhat.com>" [full] # Primary key fingerprint: DAF3 A6FD B26B 6291 2D0E 8E3F BE86 EBB4 1510 4FDF * remotes/berrange-gitlab/tags/crypto-and-more-pull-request: (26 commits) qemu-options: rewrite help for -smp options qemu-options: tweak to show that CPU count is optional qemu-options: re-arrange CPU topology options docs: fix typo s/Intel/AMD/ in CPU model notes tests/migration: fix unix socket migration seccomp: don't block getters for resource control syscalls io: use GDateTime for formatting timestamp for websock headers net/rocker: use GDateTime for formatting timestamp in debug messages crypto: prefer gnutls as the crypto backend if new enough crypto: add gnutls pbkdf provider crypto: add gnutls hmac provider crypto: add gnutls hash provider crypto: add gnutls cipher provider crypto: introduce build system for gnutls crypto backend crypto: flip priority of backends to prefer gcrypt crypto: replace 'des-rfb' cipher with 'des' crypto: delete built-in XTS cipher mode support crypto: delete built-in DES implementation crypto: add crypto tests for single block DES-ECB and DES-CBC crypto: drop custom XTS support in gcrypt driver ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | qemu-options: rewrite help for -smp optionsDaniel P. Berrangé2021-07-141-8/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The -smp option help is peculiarly specific about mentioning the CPU upper limits, but these are wrong. The "PC" target has varying max CPU counts depending on the machine type picked. Notes about guest OS limits are inappropriate for QEMU docs. There are way too many machine types for it to be practical to mention actual limits, and some limits are even modified by downstream distribtions. Thus it is better to remove the specific limits entirely. The CPU topology reporting is also not neccessarily specific to the PC platform and descriptions around the rules of usage are somewhat terse. Expand this information with some examples to show effects of defaulting. Reviewed-by: Pankaj Gupta <pankaj.gupta@ionos.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
| * | qemu-options: tweak to show that CPU count is optionalDaniel P. Berrangé2021-07-141-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The initial CPU count number is not required, if any of the topology options are given, since it can be computed. Reviewed-by: Pankaj Gupta <pankaj.gupta@ionos.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Yanan Wang <wangyanan55@huawei.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
| * | qemu-options: re-arrange CPU topology optionsDaniel P. Berrangé2021-07-141-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The list of CPU topology options are presented in a fairly arbitrary order currently. Re-arrange them so that they're ordered from largest to smallest unit Reviewed-by: Pankaj Gupta <pankaj.gupta@ionos.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Yanan Wang <wangyanan55@huawei.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
| * | docs: fix typo s/Intel/AMD/ in CPU model notesDaniel P. Berrangé2021-07-141-1/+1
| | | | | | | | | | | | | | | | | | | | | Reviewed-by: Pankaj Gupta <pankaj.gupta@ionos.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Yanan Wang <wangyanan55@huawei.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
| * | tests/migration: fix unix socket migrationHyman2021-07-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The test aborts and error message as the following be throwed: "No such file or directory: '/var/tmp/qemu-migrate-{pid}.migrate", when the unix socket migration test nearly done. The reason is qemu removes the unix socket file after migration before guestperf.py script do it. So pre-check if the socket file exists when removing it to prevent the guestperf program from aborting. See also commit f9cc00346d3 ("tests/migration: fix unix socket batch migration"). Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com> Signed-off-by: Hyman <huangy81@chinatelecom.cn> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
| * | seccomp: don't block getters for resource control syscallsDaniel P. Berrangé2021-07-141-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recent GLibC calls sched_getaffinity in code paths related to malloc and when QEMU blocks access, it sends it off into a bad codepath resulting in stack exhaustion[1]. The GLibC bug is being fixed[2], but none the less, GLibC has valid reasons to want to use sched_getaffinity. It is not unreasonable for code to want to run many resource syscalls for information gathering, so it is a bit too harsh for QEMU to block them. [1] https://bugzilla.redhat.com/show_bug.cgi?id=1975693 [2] https://sourceware.org/pipermail/libc-alpha/2021-June/128271.html Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Acked-by: Eduardo Otubo <otubo@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
| * | io: use GDateTime for formatting timestamp for websock headersDaniel P. Berrangé2021-07-141-8/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GDateTime APIs provided by GLib avoid portability pitfalls, such as some platforms where 'struct timeval.tv_sec' field is still 'long' instead of 'time_t'. When combined with automatic cleanup, GDateTime often results in simpler code too. Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
| * | net/rocker: use GDateTime for formatting timestamp in debug messagesDaniel P. Berrangé2021-07-141-8/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GDateTime APIs provided by GLib avoid portability pitfalls, such as some platforms where 'struct timeval.tv_sec' field is still 'long' instead of 'time_t'. When combined with automatic cleanup, GDateTime often results in simpler code too. Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
| * | crypto: prefer gnutls as the crypto backend if new enoughDaniel P. Berrangé2021-07-141-24/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | If we have gnutls >= 3.6.13, then it has enough functionality and performance that we can use it as the preferred crypto backend. Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
| * | crypto: add gnutls pbkdf providerDaniel P. Berrangé2021-07-142-1/+91
| | | | | | | | | | | | | | | | | | | | | | | | This adds support for using gnutls as a provider of the crypto pbkdf APIs. Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>