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| * bsd-user: Remove image_info.mmapRichard Henderson2023-08-282-2/+0
| | | | | | | | | | | | | | | | | | | | This value is unused. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230818175736.144194-3-richard.henderson@linaro.org> Reviewed-by: Warner Losh <imp@bsdimp.com> Signed-off-by: Warner Losh <imp@bsdimp.com>
| * bsd-user: Remove ELF_START_MMAP and image_info.start_mmapRichard Henderson2023-08-285-5/+0
| | | | | | | | | | | | | | | | | | | | | | The start_mmap value is write-only. Remove the field and the defines that populated it. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230818175736.144194-2-richard.henderson@linaro.org> Reviewed-by: Warner Losh <imp@bsdimp.com> Signed-off-by: Warner Losh <imp@bsdimp.com>
* | Merge tag 'pull-tcg-20230823-2' of https://gitlab.com/rth7680/qemu into stagingStefan Hajnoczi2023-08-2855-433/+832
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | accel/*: Widen pc/saved_insn for *_sw_breakpoint accel/tcg: Replace remaining target_ulong in system-mode accel tcg: spelling fixes tcg: Document bswap, hswap, wswap byte patterns tcg: Introduce negsetcond opcodes tcg: Fold deposit with zero to and tcg: Unify TCG_TARGET_HAS_extr[lh]_i64_i32 tcg/i386: Drop BYTEH deposits for 64-bit tcg/i386: Allow immediate as input to deposit target/*: Use tcg_gen_negsetcond_* # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmTnoP4dHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV80MAf+NCEN7bwqGWmWGtfz # YGXp6J51rDwOWVVzTZDv2Gtkc4/Cv0wwtLk4JT5Sg/LQur3tie/bgqOY1SBb4cRq # UC1ERk3oqvmh8+aUqCc2SsncVtBduxAMqdlIhuD886SuZHgdry5cp2/MaOEFL/Un # yQoKl238OzTmIuKnf4p/NnfD4PZxEtzKy9vQyHKswDH5f2+egaqpmKOL/6Xtl8rL # 2nXPbd1UTlMu/QLlQ/CLKcW3Z9eBNrYDSQV1+K2J5ZjSFey8H5RUv3UAfqRpY00b # EObcNCMSc6D9bpb2p34QENZNh9GiHE9Stg9VGNFOGilaaMxoa6yowlgz9Dz9xlWN # OHG1ug== # =ed8f # -----END PGP SIGNATURE----- # gpg: Signature made Thu 24 Aug 2023 14:27:10 EDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20230823-2' of https://gitlab.com/rth7680/qemu: (48 commits) tcg: spelling fixes docs/devel/tcg-ops: fix missing newlines in "Host vector operations" target/cris: Fix a typo in gen_swapr() tcg/tcg-op: Document wswap_i64() byte pattern tcg/tcg-op: Document hswap_i32/64() byte pattern tcg/tcg-op: Document bswap64_i64() byte pattern tcg/tcg-op: Document bswap32_i64() byte pattern tcg/tcg-op: Document bswap32_i32() byte pattern tcg/tcg-op: Document bswap16_i64() byte pattern tcg/tcg-op: Document bswap16_i32() byte pattern tcg/i386: Implement negsetcond_* tcg/i386: Use shift in tcg_out_setcond tcg/i386: Clear dest first in tcg_out_setcond if possible tcg/i386: Use CMP+SBB in tcg_out_setcond tcg/i386: Merge tcg_out_movcond{32,64} tcg/i386: Merge tcg_out_setcond{32,64} tcg/i386: Merge tcg_out_brcond{32,64} tcg/sparc64: Implement negsetcond_* tcg/s390x: Implement negsetcond_* tcg/riscv: Implement negsetcond_* ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * | tcg: spelling fixesMichael Tokarev2023-08-243-7/+9
| | | | | | | | | | | | | | | | | | | | | Acked-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Message-Id: <20230823065335.1919380-4-mjt@tls.msk.ru> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | docs/devel/tcg-ops: fix missing newlines in "Host vector operations"Mark Cave-Ayland2023-08-241-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This unintentionally causes the mov_vec, ld_vec and st_vec operations to appear on the same line. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230823141740.35974-1-mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | target/cris: Fix a typo in gen_swapr()Philippe Mathieu-Daudé2023-08-241-9/+11
| | | | | | | | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230823145542.79633-9-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/tcg-op: Document wswap_i64() byte patternPhilippe Mathieu-Daudé2023-08-241-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Document wswap_i64(), added in commit 46be8425ff ("tcg: Implement tcg_gen_{h,w}swap_{i32,i64}"). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230823145542.79633-8-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/tcg-op: Document hswap_i32/64() byte patternPhilippe Mathieu-Daudé2023-08-241-7/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Document hswap_i32() and hswap_i64(), added in commit 46be8425ff ("tcg: Implement tcg_gen_{h,w}swap_{i32,i64}"). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230823145542.79633-7-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/tcg-op: Document bswap64_i64() byte patternPhilippe Mathieu-Daudé2023-08-241-0/+5
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230823145542.79633-6-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/tcg-op: Document bswap32_i64() byte patternPhilippe Mathieu-Daudé2023-08-241-1/+10
| | | | | | | | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230823145542.79633-5-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/tcg-op: Document bswap32_i32() byte patternPhilippe Mathieu-Daudé2023-08-241-0/+5
| | | | | | | | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230823145542.79633-4-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/tcg-op: Document bswap16_i64() byte patternPhilippe Mathieu-Daudé2023-08-241-8/+19
| | | | | | | | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230823145542.79633-3-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/tcg-op: Document bswap16_i32() byte patternPhilippe Mathieu-Daudé2023-08-241-8/+19
| | | | | | | | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230823145542.79633-2-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/i386: Implement negsetcond_*Richard Henderson2023-08-242-10/+26
| | | | | | | | | | | | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/i386: Use shift in tcg_out_setcondRichard Henderson2023-08-241-0/+15
| | | | | | | | | | | | | | | | | | | | | For LT/GE vs zero, shift down the sign bit. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/i386: Clear dest first in tcg_out_setcond if possibleRichard Henderson2023-08-241-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | Using XOR first is both smaller and more efficient, though cannot be applied if it clobbers an input. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/i386: Use CMP+SBB in tcg_out_setcondRichard Henderson2023-08-241-0/+50
| | | | | | | | | | | | | | | | | | | | | Use the carry bit to optimize some forms of setcond. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/i386: Merge tcg_out_movcond{32,64}Richard Henderson2023-08-241-21/+7
| | | | | | | | | | | | | | | | | | | | | | | | Pass a rexw parameter instead of duplicating the functions. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/i386: Merge tcg_out_setcond{32,64}Richard Henderson2023-08-241-17/+7
| | | | | | | | | | | | | | | | | | | | | | | | Pass a rexw parameter instead of duplicating the functions. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/i386: Merge tcg_out_brcond{32,64}Richard Henderson2023-08-241-61/+49
| | | | | | | | | | | | | | | | | | | | | | | | Pass a rexw parameter instead of duplicating the functions. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/sparc64: Implement negsetcond_*Richard Henderson2023-08-242-12/+32
| | | | | | | | | | | | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/s390x: Implement negsetcond_*Richard Henderson2023-08-242-28/+54
| | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/riscv: Implement negsetcond_*Richard Henderson2023-08-242-2/+47
| | | | | | | | | | | | | | | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/arm: Implement negsetcond_i32Richard Henderson2023-08-242-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | Trivial, as we simply need to load a different constant in the conditional move. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/aarch64: Implement negsetcond_*Richard Henderson2023-08-242-2/+14
| | | | | | | | | | | | | | | | | | | | | Trivial, as aarch64 has an instruction for this: CSETM. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/ppc: Use the Set Boolean ExtensionRichard Henderson2023-08-241-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | The SETBC family of instructions requires exactly two insns for all comparisions, saving 0-3 insns per (neg)setcond. Tested-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/ppc: Implement negsetcond_*Richard Henderson2023-08-242-49/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the general case we simply negate. However with isel we may load -1 instead of 1 with no extra effort. Consolidate EQ0 and NE0 logic. Replace the NE0 zero-extension with inversion+negation of EQ0, which is never worse and may eliminate one insn. Provide a special case for -EQ0. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | target/tricore: Replace gen_cond_w with tcg_gen_negsetcond_tlRichard Henderson2023-08-241-10/+6
| | | | | | | | | | | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | target/sparc: Use tcg_gen_movcond_i64 in gen_edgeRichard Henderson2023-08-241-13/+4
| | | | | | | | | | | | | | | | | | | | | | | | The setcond + neg + or sequence is a complex method of performing a conditional move. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | target/ppc: Use tcg_gen_negsetcond_*Richard Henderson2023-08-242-7/+7
| | | | | | | | | | | | | | | | | | | | | Tested-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | target/openrisc: Use tcg_gen_negsetcond_*Richard Henderson2023-08-241-4/+2
| | | | | | | | | | | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | target/m68k: Use tcg_gen_negsetcond_*Richard Henderson2023-08-241-14/+10
| | | | | | | | | | | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | target/arm: Use tcg_gen_negsetcond_*Richard Henderson2023-08-242-21/+13
| | | | | | | | | | | | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | target/alpha: Use tcg_gen_movcond_i64 in gen_fold_mzeroRichard Henderson2023-08-241-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | The setcond + neg + and sequence is a complex method of performing a conditional move. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg: Use tcg_gen_negsetcond_*Richard Henderson2023-08-242-8/+4
| | | | | | | | | | | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg: Introduce negsetcond opcodesRichard Henderson2023-08-2418-1/+117
| | | | | | | | | | | | | | | | | | | | | Introduce a new opcode for negative setcond. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg: Unify TCG_TARGET_HAS_extr[lh]_i64_i32Richard Henderson2023-08-2413-26/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace the separate defines with TCG_TARGET_HAS_extr_i64_i32, so that the two parts of backend-specific type changing cannot be out of sync. Reported-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: <20230822175127.1173698-1-richard.henderson@linaro.org>
| * | docs/devel/tcg-ops: Bury mentions of trunc_shr_i64_i32()Philippe Mathieu-Daudé2023-08-241-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 609ad70562 ("tcg: Split trunc_shr_i32 opcode into extr[lh]_i64_i32") remove trunc_shr_i64_i32(). Update the backend documentation. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230822162847.71206-1-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/i386: Allow immediate as input to deposit_*Richard Henderson2023-08-242-5/+23
| | | | | | | | | | | | | | | | | | | | | | | | We can use MOVB and MOVW with an immediate just as easily as with a register input. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg: Fold deposit with zero to andRichard Henderson2023-08-241-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | Inserting a zero into a value, or inserting a value into zero at offset 0 may be implemented with AND. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg/i386: Drop BYTEH deposits for 64-bitRichard Henderson2023-08-244-8/+6
| | | | | | | | | | | | | | | | | | | | | | | | It is more useful to allow low-part deposits into all registers than to restrict allocation for high-byte deposits. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | target/m68k: Use tcg_gen_deposit_i32 in gen_partset_regRichard Henderson2023-08-241-9/+2
| | | | | | | | | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | accel/tcg: Update run_on_cpu_data static assertAnton Johansson2023-08-241-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As we are now using vaddr for representing guest addresses, update the static assert to check that vaddr fits in the run_on_cpu_data union. Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230807155706.9580-10-anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | accel/tcg: Widen address arg in tlb_compare_set()Anton Johansson2023-08-241-1/+1
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230807155706.9580-9-anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | include/exec: Widen tlb_hit/tlb_hit_page()Anton Johansson2023-08-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | tlb_addr is changed from target_ulong to uint64_t to match the type of a CPUTLBEntry value, and the addressed is changed to vaddr. Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230807155706.9580-8-anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | include/exec: typedef abi_ptr to vaddr in softmmuAnton Johansson2023-08-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In system mode, abi_ptr is primarily used for representing addresses when accessing guest memory with cpu_[st|ld]*(). Widening it from target_ulong to vaddr reduces the target dependence of these functions and is step towards building accel/ once for system mode. Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230807155706.9580-7-anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | include/exec: Replace target_ulong with abi_ptr in cpu_[st|ld]*()Anton Johansson2023-08-245-29/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changes the address type of the guest memory read/write functions from target_ulong to abi_ptr. (abi_ptr is currently typedef'd to target_ulong but that will change in a following commit.) This will reduce the coupling between accel/ and target/. Note: Function pointers that point to cpu_[st|ld]*() in target/riscv and target/rx are also updated in this commit. Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230807155706.9580-6-anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | sysemu/hvf: Use vaddr for hvf_arch_[insert|remove]_hw_breakpointAnton Johansson2023-08-243-8/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changes the signature of the target-defined functions for inserting/removing hvf hw breakpoints. The address and length arguments are now of vaddr type, which both matches the type used internally in accel/hvf/hvf-all.c and makes the api target-agnostic. Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230807155706.9580-5-anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | sysemu/kvm: Use vaddr for kvm_arch_[insert|remove]_hw_breakpointAnton Johansson2023-08-245-24/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changes the signature of the target-defined functions for inserting/removing kvm hw breakpoints. The address and length arguments are now of vaddr type, which both matches the type used internally in accel/kvm/kvm-all.c and makes the api target-agnostic. Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230807155706.9580-4-anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | accel/hvf: Widen pc/saved_insn for hvf_sw_breakpointAnton Johansson2023-08-243-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Widens the pc and saved_insn fields of hvf_sw_breakpoint from target_ulong to vaddr. Other hvf_* functions accessing hvf_sw_breakpoint are also widened to match. Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230807155706.9580-3-anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>