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| * target/i386: Fix exception classes for SSE/AVX instructions.Ricky Zhou2023-05-181-23/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the exception classes for some SSE/AVX instructions to match what is documented in the Intel manual. These changes are expected to have no functional effect on the behavior that qemu implements (primarily >= 16-byte memory alignment checks). For instance, since qemu does not implement the AC flag, there is no difference in behavior between Exception Classes 4 and 5 for instructions where the SSE version only takes <16 byte memory operands. Message-Id: <20230501111428.95998-2-ricky@rzhou.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * target/i386: Fix and add some comments next to SSE/AVX instructions.Ricky Zhou2023-05-181-12/+12
| | | | | | | | | | | | | | | | | | Adds some comments describing what instructions correspond to decoding table entries and fixes some existing comments which named the wrong instruction. Message-Id: <20230501111428.95998-1-ricky@rzhou.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * tests/tcg/i386: correct mask for VPERM2F128/VPERM2I128Paolo Bonzini2023-05-181-1/+1
| | | | | | | | | | | | The instructions also use bits 3 and 7 of their 8-byte immediate. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * target/i386: fix avx2 instructions vzeroall and vpermdqXinyu Li2023-05-182-1/+9
| | | | | | | | | | | | | | | | | | | | vzeroall: xmm_regs should be used instead of xmm_t0 vpermdq: bit 3 and 7 of imm should be considered Signed-off-by: Xinyu Li <lixinyu20s@ict.ac.cn> Message-Id: <20230510145222.586487-1-lixinyu20s@ict.ac.cn> Cc: qemu-stable@nongnu.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * target/i386: fix operand size for VCOMI/VUCOMI instructionsPaolo Bonzini2023-05-181-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Compared to other SSE instructions, VUCOMISx and VCOMISx are different: the single and double precision versions are distinguished through a prefix, however they use no-prefix and 0x66 for SS and SD respectively. Scalar values usually are associated with 0xF2 and 0xF3. Because of these, they incorrectly perform a 128-bit memory load instead of a 32- or 64-bit load. Fix this by writing a custom decoding function. I tested that the reproducer is fixed and the test-avx output does not change. Reported-by: Gabriele Svelto <gsvelto@mozilla.com> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1637 Fixes: f8d19eec0d53 ("target/i386: reimplement 0x0f 0x28-0x2f, add AVX", 2022-10-18) Cc: qemu-stable@nongnu.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * target/i386: add support for FB_CLEAR featureEmanuele Giuseppe Esposito2023-05-182-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As reported by the Intel's doc: "FB_CLEAR: The processor will overwrite fill buffer values as part of MD_CLEAR operations with the VERW instruction. On these processors, L1D_FLUSH does not overwrite fill buffer values." If this cpu feature is present in host, allow QEMU to choose whether to show it to the guest too. One disadvantage of not exposing it is that the guest will report a non existing vulnerability in /sys/devices/system/cpu/vulnerabilities/mmio_stale_data because the mitigation is present only when the cpu has (FLUSH_L1D and MD_CLEAR) or FB_CLEAR features enabled. Signed-off-by: Emanuele Giuseppe Esposito <eesposit@redhat.com> Message-Id: <20230201135759.555607-3-eesposit@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * target/i386: add support for FLUSH_L1D featureEmanuele Giuseppe Esposito2023-05-182-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As reported by Intel's doc: "L1D_FLUSH: Writeback and invalidate the L1 data cache" If this cpu feature is present in host, allow QEMU to choose whether to show it to the guest too. One disadvantage of not exposing it is that the guest will report a non existing vulnerability in /sys/devices/system/cpu/vulnerabilities/mmio_stale_data because the mitigation is present only when the cpu has (FLUSH_L1D and MD_CLEAR) or FB_CLEAR features enabled. Signed-off-by: Emanuele Giuseppe Esposito <eesposit@redhat.com> Message-Id: <20230201135759.555607-2-eesposit@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | Merge tag 'pull-target-arm-20230518' of ↵Richard Henderson2023-05-1820-904/+959
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * Fix vd == vm overlap in sve_ldff1_z * Add support for MTE with KVM guests * Add RAZ/WI handling for DBGDTR[TX|RX] * Start of conversion of A64 decoder to decodetree * Saturate L2CTLR_EL1 core count field rather than overflowing * vexpress: Avoid trivial memory leak of 'flashalias' * sbsa-ref: switch default cpu core to Neoverse-N1 * sbsa-ref: use Bochs graphics card instead of VGA * MAINTAINERS: Add Marcin Juszkiewicz to sbsa-ref reviewer list * docs: Convert u2f.txt to rST # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmRmHvMZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3vqqEACFEcWq3E2gRjwnz8JAEk/0 # jYuYg9jUG6Ev6xY5x31+M4DfK78eXgHYtCxhEcT6FSwpFg/ZXC+bPlZcRlM+8692 # gkp+JJeBA4VRy9e7Uk6GvRWnpGzjnkHTHf4E9PZB8iIvbJY9nFTtMZydn1w0EnMW # HsetnNLIxrtJaETwUa5mDWh0Bt4t6ZIEB2bJSr3O0fy7uiJ8xvpRMYxqfxvI0h+0 # 7xSaG7xb5Dy4LxohMK0CLdj1wy+8uWpYgD6ZneJ2hlqjknvNWa3zdR8bRLNT0aZL # 8ubR1ioFvfi+uA26SNVrdRrGEhqMrTxD0XstFutz0zlOjn0wjo1Ny/ojmGYWuvcU # aG09UvcecMP8hy+ygTXJ+2D04eH1VGmS1GEwRS3p+fdODsgHy0Ctln8IPK8SuG7q # 67BG/F4GNdkbktHGbZlwduxh30furH8pSSlIJOeTq7d20+atqZ94MWaoW1iQ+t4B # 9gDi3MsKoUKVNEhJPorHlDxvtlQppr0ziL0IVPeYUNJONlSza88hkx34ScA5Rl7+ # 5vQYjLkhS1qZQqvd1fNSRNtHeGx2uBeE9eZF/ZCp7bA5rxcRn//LmG7hO7Octuii # zIVaOektXeShALdJ7dMt4MZh0z1RjVVLf0ouC1HHCg9rlzvB+0I5AhXYacGkmCqW # wf9S0hvNqdGmJRQhNRonGg== # =ooCi # -----END PGP SIGNATURE----- # gpg: Signature made Thu 18 May 2023 05:49:55 AM PDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] * tag 'pull-target-arm-20230518' of https://git.linaro.org/people/pmaydell/qemu-arm: (29 commits) docs: Convert u2f.txt to rST hw/arm/vexpress: Avoid trivial memory leak of 'flashalias' target/arm: Saturate L2CTLR_EL1 core count field rather than overflowing target/arm: Convert ERET, ERETAA, ERETAB to decodetree target/arm: Convert BRAA, BRAB, BLRAA, BLRAB to decodetree target/arm: Convert BRA[AB]Z, BLR[AB]Z, RETA[AB] to decodetree target/arm: Convert BR, BLR, RET to decodetree target/arm: Convert conditional branch insns to decodetree target/arm: Convert TBZ, TBNZ to decodetree target/arm: Convert CBZ, CBNZ to decodetree target/arm: Convert unconditional branch immediate to decodetree target/arm: Convert Extract instructions to decodetree target/arm: Convert Bitfield to decodetree target/arm: Convert Move wide (immediate) to decodetree target/arm: Convert Logical (immediate) to decodetree target/arm: Replace bitmask64 with MAKE_64BIT_MASK target/arm: Convert Add/subtract (immediate with tags) to decodetree target/arm: Convert Add/subtract (immediate) to decodetree target/arm: Split gen_add_CC and gen_sub_CC target/arm: Convert PC-rel addressing to decodetree ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * docs: Convert u2f.txt to rSTPeter Maydell2023-05-184-111/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the u2f.txt file to rST, and place it in the right place in our manual layout. The old text didn't fit very well into our manual style, so the new version ends up looking like a rewrite, although some of the original text is preserved: * the 'building' section of the old file is removed, since we generally assume that users have already built QEMU * some rather verbose text has been cut back * document the passthrough device first, on the assumption that's most likely to be of interest to users * cut back on the duplication of text between sections * format example command lines etc with rST As it's a short document it seemed simplest to do this all in one go rather than try to do a minimal syntactic conversion and then clean up the wording and layout. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-id: 20230421163734.1152076-1-peter.maydell@linaro.org
| * hw/arm/vexpress: Avoid trivial memory leak of 'flashalias'Peter Maydell2023-05-181-20/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the vexpress board code, we allocate a new MemoryRegion at the top of vexpress_common_init() but only set it up and use it inside the "if (map[VE_NORFLASHALIAS] != -1)" conditional, so we leak it if not. This isn't a very interesting leak as it's a tiny amount of memory once at startup, but it's easy to fix. We could silence Coverity simply by moving the g_new() into the if() block, but this use of g_new(MemoryRegion, 1) is a legacy from when this board model was originally written; we wouldn't do that if we wrote it today. The MemoryRegions are conceptually a part of the board and must not go away until the whole board is done with (at the end of the simulation), so they belong in its state struct. This machine already has a VexpressMachineState struct that extends MachineState, so statically put the MemoryRegions in there instead of dynamically allocating them separately at runtime. Spotted by Coverity (CID 1509083). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20230512170223.3801643-3-peter.maydell@linaro.org
| * target/arm: Saturate L2CTLR_EL1 core count field rather than overflowingPeter Maydell2023-05-181-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The IMPDEF sysreg L2CTLR_EL1 found on the Cortex-A35, A53, A57, A72 and which we (arguably dubiously) also provide in '-cpu max' has a 2 bit field for the number of processors in the cluster. On real hardware this must be sufficient because it can only be configured with up to 4 CPUs in the cluster. However on QEMU if the board code does not explicitly configure the code into clusters with the right CPU count we default to "give the value assuming that all CPUs in the system are in a single cluster", which might be too big to fit in the field. Instead of just overflowing this 2-bit field, saturate to 3 (meaning "4 CPUs", so at least we don't overwrite other fields in the register. It's unlikely that any guest code really cares about the value in this field; at least, if it does it probably also wants the system to be more closely matching real hardware, i.e. not to have more than 4 CPUs. This issue has been present since the L2CTLR was first added in commit 377a44ec8f2fac5b back in 2014. It was only noticed because Coverity complains (CID 1509227) that the shift might overflow 32 bits and inadvertently sign extend into the top half of the 64 bit value. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230512170223.3801643-2-peter.maydell@linaro.org
| * target/arm: Convert ERET, ERETAA, ERETAB to decodetreePeter Maydell2023-05-182-108/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the exception-return insns ERET, ERETA and ERETB to decodetree. These were the last insns left in the legacy decoder function disas_uncond_reg_b(), which allows us to remove it. The old decoder explicitly decoded the DRPS instruction, only in order to call unallocated_encoding() on it, exactly as would have happened if it hadn't decoded it. This is because this insn always UNDEFs unless the CPU is in halting-debug state, which we don't emulate. So we list the pattern in a comment in a64.decode, but don't actively decode it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230512144106.3608981-21-peter.maydell@linaro.org
| * target/arm: Convert BRAA, BRAB, BLRAA, BLRAB to decodetreePeter Maydell2023-05-182-58/+43
| | | | | | | | | | | | | | | | | | | | | | Convert the last four BR-with-pointer-auth insns to decodetree. The remaining cases in the outer switch in disas_uncond_b_reg() all return early rather than leaving the case statement, so we can delete the now-unused code at the end of that function. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230512144106.3608981-20-peter.maydell@linaro.org
| * target/arm: Convert BRA[AB]Z, BLR[AB]Z, RETA[AB] to decodetreePeter Maydell2023-05-182-55/+84
| | | | | | | | | | | | | | | | | | | | Convert the single-register pointer-authentication variants of BR, BLR, RET to decodetree. (BRAA/BLRAA are in a different branch of the legacy decoder and will be dealt with in the next commit.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230512144106.3608981-19-peter.maydell@linaro.org
| * target/arm: Convert BR, BLR, RET to decodetreePeter Maydell2023-05-182-6/+54
| | | | | | | | | | | | | | | | | | Convert the simple (non-pointer-auth) BR, BLR and RET insns to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230512144106.3608981-18-peter.maydell@linaro.org
| * target/arm: Convert conditional branch insns to decodetreePeter Maydell2023-05-182-24/+8
| | | | | | | | | | | | | | | | | | Convert the immediate conditional branch insn B.cond to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230512144106.3608981-17-peter.maydell@linaro.org
| * target/arm: Convert TBZ, TBNZ to decodetreePeter Maydell2023-05-182-20/+11
| | | | | | | | | | | | | | | | | | Convert the test-and-branch-immediate insns TBZ and TBNZ to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230512144106.3608981-16-peter.maydell@linaro.org
| * target/arm: Convert CBZ, CBNZ to decodetreePeter Maydell2023-05-182-20/+11
| | | | | | | | | | | | | | | | | | Convert the compare-and-branch-immediate insns CBZ and CBNZ to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230512144106.3608981-15-peter.maydell@linaro.org
| * target/arm: Convert unconditional branch immediate to decodetreePeter Maydell2023-05-182-19/+19
| | | | | | | | | | | | | | | | | | Convert the unconditional branch immediate insns B and BL to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230512144106.3608981-14-peter.maydell@linaro.org
| * target/arm: Convert Extract instructions to decodetreePeter Maydell2023-05-182-63/+34
| | | | | | | | | | | | | | | | | | | | | | Convert the EXTR instruction to decodetree (this is the only one in the 'Extract" class). This is the last of the dp-immediate insns in the legacy decoder, so we can now remove disas_data_proc_imm(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230512144106.3608981-13-peter.maydell@linaro.org
| * target/arm: Convert Bitfield to decodetreeRichard Henderson2023-05-182-57/+88
| | | | | | | | | | | | | | | | | | | | | | Convert the BFM, SBFM, UBFM instructions. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230512144106.3608981-12-peter.maydell@linaro.org [PMM: Rebased] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Convert Move wide (immediate) to decodetreeRichard Henderson2023-05-182-43/+41
| | | | | | | | | | | | | | | | | | | | | | | | Convert the MON, MOVZ, MOVK instructions. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230512144106.3608981-11-peter.maydell@linaro.org [PMM: Rebased] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Convert Logical (immediate) to decodetreeRichard Henderson2023-05-182-64/+43
| | | | | | | | | | | | | | | | | | | | | | Convert the ADD, ORR, EOR, ANDS (immediate) instructions. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230512144106.3608981-10-peter.maydell@linaro.org [PMM: rebased] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Replace bitmask64 with MAKE_64BIT_MASKRichard Henderson2023-05-181-9/+2
| | | | | | | | | | | | | | | | | | Use the bitops.h macro rather than rolling our own here. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230512144106.3608981-9-peter.maydell@linaro.org
| * target/arm: Convert Add/subtract (immediate with tags) to decodetreeRichard Henderson2023-05-182-27/+19
| | | | | | | | | | | | | | | | | | | | | | | | Convert the ADDG and SUBG (immediate) instructions. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230512144106.3608981-8-peter.maydell@linaro.org [PMM: Rebased; use TRANS_FEAT()] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Convert Add/subtract (immediate) to decodetreeRichard Henderson2023-05-183-53/+42
| | | | | | | | | | | | | | | | | | | | | | | | Convert the ADD and SUB (immediate) instructions. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230512144106.3608981-7-peter.maydell@linaro.org [PMM: Rebased; adjusted to use translate.h's TRANS macro] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Split gen_add_CC and gen_sub_CCRichard Henderson2023-05-181-60/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Split out specific 32-bit and 64-bit functions. These carry the same signature as tcg_gen_add_i64, and so will be easier to pass as callbacks. Retain gen_add_CC and gen_sub_CC during conversion. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230512144106.3608981-6-peter.maydell@linaro.org [PMM: rebased] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Convert PC-rel addressing to decodetreeRichard Henderson2023-05-182-24/+27
| | | | | | | | | | | | | | | | | | | | | | | | Convert the ADR and ADRP instructions. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230512144106.3608981-5-peter.maydell@linaro.org [PMM: Rebased] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Pull calls to disas_sve() and disas_sme() out of legacy decoderPeter Maydell2023-05-181-16/+4
| | | | | | | | | | | | | | | | | | | | | | | | The SVE and SME decode is already done by decodetree. Pull the calls to these decoders out of the legacy decoder. This doesn't change behaviour because all the patterns in sve.decode and sme.decode already require the bits that the legacy decoder is decoding to have the correct values. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230512144106.3608981-4-peter.maydell@linaro.org
| * target/arm: Create decodetree skeleton for A64Peter Maydell2023-05-183-7/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A64 translator uses a hand-written decoder for everything except SVE or SME. It's fairly well structured, but it's becoming obvious that it's still more painful to add instructions to than the A32 translator, because putting a new instruction into the right place in a hand-written decoder is much harder than adding new instruction patterns to a decodetree file. As the first step in conversion to decodetree, create the skeleton of the decodetree decoder; where it does not handle instructions we will fall back to the legacy decoder (which will be for everything at the moment, since there are no patterns in a64.decode). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230512144106.3608981-3-peter.maydell@linaro.org
| * target/arm: Split out disas_a64_legacyRichard Henderson2023-05-181-38/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | Split out all of the decode stuff from aarch64_tr_translate_insn. Call it disas_a64_legacy to indicate it will be replaced. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230512144106.3608981-2-peter.maydell@linaro.org [PMM: Rebased] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * sbsa-ref: use Bochs graphics card instead of VGAMarcin Juszkiewicz2023-05-181-1/+1
| | | | | | | | | | | | | | | | | | | | Bochs card is normal PCI Express card so it fits better in system with PCI Express bus. VGA is simple legacy PCI card. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Message-id: 20230505120936.1097060-1-marcin.juszkiewicz@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: add RAZ/WI handling for DBGDTR[TX|RX]Alex Bennée2023-05-181-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit b3aa2f2128 (target/arm: provide stubs for more external debug registers) was added to handle HyperV's unconditional usage of Debug Communications Channel. It turns out that Linux will similarly break if you enable CONFIG_HVC_DCC "ARM JTAG DCC console". Extend the registers we RAZ/WI set to avoid this. Cc: Anders Roxell <anders.roxell@linaro.org> Cc: Evgeny Iakovlev <eiakovlev@linux.microsoft.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230516104420.407912-1-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * arm/kvm: add support for MTECornelia Huck2023-05-186-34/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extend the 'mte' property for the virt machine to cover KVM as well. For KVM, we don't allocate tag memory, but instead enable the capability. If MTE has been enabled, we need to disable migration, as we do not yet have a way to migrate the tags as well. Therefore, MTE will stay off with KVM unless requested explicitly. Signed-off-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230428095533.21747-2-cohuck@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * Maintainers: add myself as reviewer for sbsa-refMarcin Juszkiewicz2023-05-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | At Linaro I work on sbsa-ref, know direction it goes. May not get code details each time. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20230515143753.365591-1-marcin.juszkiewicz@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Fix vd == vm overlap in sve_ldff1_zRichard Henderson2023-05-181-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | If vd == vm, copy vm to scratch, so that we can pre-zero the output and still access the gather indicies. Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1612 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230504104232.1877774-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * sbsa-ref: switch default cpu core to Neoverse-N1Marcin Juszkiewicz2023-05-181-1/+1
|/ | | | | | | | | | The world outside moves to newer and newer cpu cores. Let move SBSA Reference Platform to something newer as well. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Message-id: 20230506183417.1360427-1-marcin.juszkiewicz@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* qapi/parser: Drop two bad type hints for nowMarkus Armbruster2023-05-171-2/+2
| | | | | | | | | | | | | Two type hints fail centos-stream-8-x86_64 CI. They are actually broken. Changing them to Optional[re.Match[str]] fixes them locally for me, but then CI fails differently. Drop them for now. Fixes: 3e32dca3f0d1 (qapi: Rewrite parsing of doc comment section symbols and tags) Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20230517061600.1782455-1-armbru@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* Merge tag 'linux-user-for-8.1-pull-request' of ↵Richard Henderson2023-05-174-42/+176
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://github.com/vivier/qemu into staging linux-user pull request 20230512-v4 add open_tree(), move_mount() add /proc/cpuinfo for riscv fixes and cleanup # -----BEGIN PGP SIGNATURE----- # # iQJGBAABCAAwFiEEzS913cjjpNwuT1Fz8ww4vT8vvjwFAmRkiZISHGxhdXJlbnRA # dml2aWVyLmV1AAoJEPMMOL0/L748FdIP/RC1JaCftkP7ajAstNbZLMLegMxjUYHV # TrdhsMOsm804ZmLgTqqfS3bJ080mIHup0xUnHBckcEtUcwaz54cJ1BAR2WlM3/8A # t3fHMt3PDkh3OPd/3AnmpLE8XRh7yBztirPYfZc6SKqnFzT0TZrwBoQnwprEnZ5r # c0gbrgLZLunZhrWU1BbQmuIufW1qDoQo4PzwnyZeux1fHA1/v/dx3wgSLpv3V4k6 # x0Kj8TvtMUU4/io2RqYF4jKopfhwsh0jnr9rlOmydOExalKq1VbRptJI2UC4KVOY # MZuApF1EaZfrW+v/WSlvmzaZ/zRzP1L0X3Xh0wB4J9Rj3057/elXr6bi+R+rM46p # xGTcti9ahWKP2J4/xrazRw2lfPsLcw/YbqVGG79AX1xLJPCiWq6lamzc/g3ptFnx # F/RRETe65z7apzF/nzU7SDOsMdN5p4/fMb1SysLuAov5OepNVjNVWyiTgqOHB5uC # ye+lOYkkvk+qRdMbls/fIcjDQ3C4AjoBWj4QlgRc0/Qf6ac4TkVjzPa70Y6eyzzS # LEV9D4fXD8EZgYWENNGmbbKPNbtfqc9uR6gXdgkEsKDx/rf5IMf1d6r1C99dhB3A # nbu0JpFKKY2lhD2oGVPDE3UQMW9DXXhZpDApUBsLNiEwfuoXZee+apH+6jc8tbn6 # r+8LFB1mM9os # =NfIV # -----END PGP SIGNATURE----- # gpg: Signature made Wed 17 May 2023 01:00:18 AM PDT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [undefined] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [undefined] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * tag 'linux-user-for-8.1-pull-request' of https://github.com/vivier/qemu: linux-user: fix getgroups/setgroups allocations linux-user: Fix mips fp64 executables loading linux-user: Don't require PROT_READ for mincore linux-user: Add new flag VERIFY_NONE linux-user/main: Use list_cpus() instead of cpu_list() linux-user: Add open_tree() syscall linux-user: Add move_mount() syscall linux-user: report ENOTTY for unknown ioctls linux-user: Emulate /proc/cpuinfo output for riscv Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * linux-user: fix getgroups/setgroups allocationsMichael Tokarev2023-05-171-31/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | linux-user getgroups(), setgroups(), getgroups32() and setgroups32() used alloca() to allocate grouplist arrays, with unchecked gidsetsize coming from the "guest". With NGROUPS_MAX being 65536 (linux, and it is common for an application to allocate NGROUPS_MAX for getgroups()), this means a typical allocation is half the megabyte on the stack. Which just overflows stack, which leads to immediate SIGSEGV in actual system getgroups() implementation. An example of such issue is aptitude, eg https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=811087#72 Cap gidsetsize to NGROUPS_MAX (return EINVAL if it is larger than that), and use heap allocation for grouplist instead of alloca(). While at it, fix coding style and make all 4 implementations identical. Try to not impose random limits - for example, allow gidsetsize to be negative for getgroups() - just do not allocate negative-sized grouplist in this case but still do actual getgroups() call. But do not allow negative gidsetsize for setgroups() since its argument is unsigned. Capping by NGROUPS_MAX seems a bit arbitrary, - we can do more, it is not an error if set size will be NGROUPS_MAX+1. But we should not allow integer overflow for the array being allocated. Maybe it is enough to just call g_try_new() and return ENOMEM if it fails. Maybe there's also no need to convert setgroups() since this one is usually smaller and known beforehand (KERN_NGROUPS_MAX is actually 63, - this is apparently a kernel-imposed limit for runtime group set). The patch fixes aptitude segfault mentioned above. Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Message-Id: <20230409105327.1273372-1-mjt@msgid.tls.msk.ru> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * linux-user: Fix mips fp64 executables loadingDaniil Kovalev2023-05-171-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | If a program requires fr1, we should set the FR bit of CP0 control status register and add F64 hardware flag. The corresponding `else if` branch statement is copied from the linux kernel sources (see `arch_check_elf` function in linux/arch/mips/kernel/elf.c). Signed-off-by: Daniil Kovalev <dkovalev@compiler-toolchain-for.me> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20230404052153.16617-1-dkovalev@compiler-toolchain-for.me> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * linux-user: Don't require PROT_READ for mincoreThomas Weißschuh2023-05-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The kernel does not require PROT_READ for addresses passed to mincore. For example the fincore(1) tool from util-linux uses PROT_NONE and currently does not work under qemu-user. Example (with fincore(1) from util-linux 2.38): $ fincore /proc/self/exe RES PAGES SIZE FILE 24K 6 22.1K /proc/self/exe $ qemu-x86_64 /usr/bin/fincore /proc/self/exe fincore: failed to do mincore: /proc/self/exe: Cannot allocate memory With this patch: $ ./build/qemu-x86_64 /usr/bin/fincore /proc/self/exe RES PAGES SIZE FILE 24K 6 22.1K /proc/self/exe Signed-off-by: Thomas Weißschuh <thomas@t-8ch.de> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20230422100314.1650-3-thomas@t-8ch.de> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * linux-user: Add new flag VERIFY_NONEThomas Weißschuh2023-05-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This can be used to validate that an address range is mapped but without being readable or writable. It will be used by an updated implementation of mincore(). Signed-off-by: Thomas Weißschuh <thomas@t-8ch.de> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20230422100314.1650-2-thomas@t-8ch.de> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * linux-user/main: Use list_cpus() instead of cpu_list()Thomas Huth2023-05-171-4/+1
| | | | | | | | | | | | | | | | | | | | | | This way we can get rid of the if'deffery and the XXX comment here (it's repeated in the list_cpus() function anyway). Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230424122126.236586-1-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * linux-user: Add open_tree() syscallThomas Weißschuh2023-05-171-0/+33
| | | | | | | | | | | | | | | | | | Signed-off-by: Thomas Weißschuh <thomas@t-8ch.de> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20230424153429.276788-2-thomas@t-8ch.de> [lv: move declaration at the beginning of the block, define syscall] Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * linux-user: Add move_mount() syscallThomas Weißschuh2023-05-171-0/+33
| | | | | | | | | | | | | | | | Signed-off-by: Thomas Weißschuh <thomas@t-8ch.de> Reviewed-by: Laurent Vivier <laurent@vivier.eu> [lv: define syscall] Message-Id: <20230424153429.276788-1-thomas@t-8ch.de> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * linux-user: report ENOTTY for unknown ioctlsThomas Weißschuh2023-05-171-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The correct error number for unknown ioctls is ENOTTY. ENOSYS would mean that the ioctl() syscall itself is not implemented, which is very improbable and unexpected for userspace. ENOTTY means "Inappropriate ioctl for device". This is what the kernel returns on unknown ioctls, what qemu is trying to express and what userspace is prepared to handle. Signed-off-by: Thomas Weißschuh <thomas@t-8ch.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230426070659.80649-1-thomas@t-8ch.de> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * linux-user: Emulate /proc/cpuinfo output for riscvAfonso Bordado2023-05-171-2/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RISC-V does not expose all extensions via hwcaps, thus some userspace applications may want to query these via /proc/cpuinfo. Currently when querying this file the host's file is shown instead which is slightly confusing. Emulate a basic /proc/cpuinfo file with mmu info and an ISA string. Signed-off-by: Afonso Bordado <afonsobordado@gmail.com> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-Id: <167873059442.9885.15152085316575248452-0@git.sr.ht> [lv: removed the test that fails in CI for unknown reason] Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* | Merge tag 'pull-tcg-20230516-3' of https://gitlab.com/rth7680/qemu into stagingRichard Henderson2023-05-1650-3327/+5320
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | tcg/i386: Fix tcg_out_addi_ptr for win64 tcg: Implement atomicity for TCGv_i128 tcg: First quarter of cleanups for building tcg once # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmRkWC8dHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/I+wf8CUF+J/E9u0EuurrB # 1asDicANUJIACnqlcEpSPKuSMtbzo1RDTQUR+d3GWJjyLASvSJZFZTQqWBdACRpc # sNuDz3/1a6FbiM14CwIVmPpcjQXa+18Ck670Chmw51KyEt2xyDJTySFIGEqjiuTf # YVDBbOs8neFZdcDvAs1qNUTjhRj4nNtkpQoBpv0tGH7E0CzPp6OcvxwfieVyLOIa # Cy1ELM3aMyVN5MTjnORYLK70Pa9emdjB88SlypZx363ARKC7B50lzYPQ4E5zrOZq # FKrOq5nFWLCtn4BID0R+jUmuUP6znR/hTlToDmf/9B4j9TUivERWlc54lz3YU6Gn # su3FKg== # =LVOb # -----END PGP SIGNATURE----- # gpg: Signature made Tue 16 May 2023 09:29:35 PM PDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate] * tag 'pull-tcg-20230516-3' of https://gitlab.com/rth7680/qemu: (74 commits) tcg: Split out exec/user/guest-base.h tcg: Add tlb_dyn_max_bits to TCGContext tcg: Add page_bits and page_mask to TCGContext tcg: Remove TARGET_LONG_BITS, TCG_TYPE_TL tcg/mips: Remove TARGET_LONG_BITS, TCG_TYPE_TL tcg/loongarch64: Remove TARGET_LONG_BITS, TCG_TYPE_TL tcg/aarch64: Remove TARGET_LONG_BITS, TCG_TYPE_TL tcg/aarch64: Remove USE_GUEST_BASE tcg/arm: Remove TARGET_LONG_BITS tcg/i386: Remove TARGET_LONG_BITS, TCG_TYPE_TL tcg/i386: Adjust type of tlb_mask tcg/i386: Conditionalize tcg_out_extu_i32_i64 tcg/i386: Always enable TCG_TARGET_HAS_extr[lh]_i64_i32 tcg/tci: Elimnate TARGET_LONG_BITS, target_ulong tcg: Split INDEX_op_qemu_{ld,st}* for guest address size tcg: Remove TCGv from tcg_gen_atomic_* tcg: Remove TCGv from tcg_gen_qemu_{ld,st}_* tcg: Add addr_type to TCGContext accel/tcg: Widen plugin_gen_empty_mem_callback to i64 tcg: Reduce copies for plugin_gen_mem_callbacks ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | tcg: Split out exec/user/guest-base.hRichard Henderson2023-05-163-4/+16
| | | | | | | | | | | | | | | | | | | | | | | | TCG will need this declaration, without all of the other bits that come with cpu-all.h. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>