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* hw/pci-bridge/cxl_upstream: Fix problem with g_steal_pointer()Thomas Huth2024-03-092-7/+9
| | | | | | | | | | | | | | | | | | | | | When setting GLIB_VERSION_MAX_ALLOWED to GLIB_VERSION_2_58 or higher, glib adds type safety checks to the g_steal_pointer() macro. This triggers errors in the build_cdat_table() function which uses the g_steal_pointer() for type-casting from one pointer type to the other (which also looks quite weird since the local pointers have all been declared with g_autofree though they are never freed here). Let's fix it by using a proper typecast instead. For making this possible, we have to remove the QEMU_PACKED attribute from some structs since GCC otherwise complains that the source and destination pointer might have different alignment restrictions. Removing the QEMU_PACKED should be fine here since the structs are already naturally aligned. Anyway, add some QEMU_BUILD_BUG_ON() statements to make sure that we've got the right sizes (without padding in the structs). Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* hw/cxl/cxl-cdat: Fix type of buf in ct3_load_cdat()Thomas Huth2024-03-091-2/+2
| | | | | | | | | | | | | | | When setting GLIB_VERSION_MAX_ALLOWED to GLIB_VERSION_2_58 or higher (which we'll certainly do in the not too distant future), glib adds type safety checks to the g_steal_pointer() macro. This trigger an error in the ct3_load_cdat() function: The local char *buf variable is assigned to uint8_t *buf in CDATObject, i.e. a pointer of a different type. Change the local variable to the same type as buf in CDATObject to avoid the error. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* qerror: QERR_DEVICE_IN_USE is no longer used, dropMarkus Armbruster2024-03-091-3/+0
| | | | | | | Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* blockdev: Fix block_resize error reporting for op blockersMarkus Armbruster2024-03-091-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When block_resize() runs into an op blocker, it creates an error like this: error_setg(errp, "Device '%s' is in use", device); Trouble is @device can be null. My system formats null as "(null)", but other systems might crash. Reproducer: 1. Create two block devices -> {"execute": "blockdev-add", "arguments": {"driver": "file", "node-name": "blk0", "filename": "64k.img"}} <- {"return": {}} -> {"execute": "blockdev-add", "arguments": {"driver": "file", "node-name": "blk1", "filename": "m.img"}} <- {"return": {}} 2. Put a blocker on one them -> {"execute": "blockdev-mirror", "arguments": {"job-id": "job0", "device": "blk0", "target": "blk1", "sync": "full"}} {"return": {}} -> {"execute": "job-pause", "arguments": {"id": "job0"}} {"return": {}} -> {"execute": "job-complete", "arguments": {"id": "job0"}} {"return": {}} Note: job events elided for brevity. 3. Attempt to resize -> {"execute": "block_resize", "arguments": {"node-name": "blk1", "size":32768}} <- {"error": {"class": "GenericError", "desc": "Device '(null)' is in use"}} Broken when commit 3b1dbd11a60 made @device optional. Fixed in commit ed3d2ec98a3 (block: Add errp to b{lk,drv}_truncate()), except for this one instance. Fix it by using the error message provided by the op blocker instead, so it fails like this: <- {"error": {"class": "GenericError", "desc": "Node 'blk1' is busy: block device is in use by block job: mirror"}} Fixes: 3b1dbd11a60d (qmp: Allow block_resize to manipulate bs graph nodes.) Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* char: Slightly better error reporting when chardev is in useMarkus Armbruster2024-03-091-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | Both $ qemu-system-x86_64 -chardev null,id=chr0,mux=on -mon chardev=chr0 -mon chardev=chr0 -mon chardev=chr0 -mon chardev=chr0 -mon chardev=chr0 and $ qemu-system-x86_64 -chardev null,id=chr0 -mon chardev=chr0 -mon chardev=chr0 fail with qemu-system-x86_64: -mon chardev=chr0: Device 'chr0' is in use Improve to qemu-system-x86_64: -mon chardev=chr0: too many uses of multiplexed chardev 'chr0' (maximum is 4) and qemu-system-x86_64: -mon chardev=chr0: chardev 'chr0' is already in use Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* make-release: switch to .xz format by defaultMichael Tokarev2024-03-091-1/+1
| | | | | | | | | | | | | | | For a long time, we provide two compression formats in the download area, .bz2 and .xz. There's absolutely no reason to provide two in parallel, .xz compresses better, and all the links we use points to .xz. Downstream distributions mostly use .xz too. For the release maintenance providing two formats is definitely extra burden too. Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
* hw/scsi/lsi53c895a: Fix typo in commentBALATON Zoltan2024-03-091-1/+1
| | | | | | Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* hw/vfio/pci.c: Make some structure staticFrediano Ziglio2024-03-091-2/+2
| | | | | | | | | | Not used outside C module. Signed-off-by: Frediano Ziglio <frediano.ziglio@cloud.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* replay: Improve error messages about configuration conflictsMarkus Armbruster2024-03-092-2/+2
| | | | | | | | | | | | | | | | | | | | Improve Record/replay feature is not supported for '-rtc base=localtime' Record/replay feature is not supported for 'smp' Record/replay feature is not supported for '-snapshot' to Record/replay is not supported with -rtc base=localtime Record/replay is not supported with multiple CPUs Record/replay is not supported with -snapshot Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* Merge tag 'darwin-20240305' of https://github.com/philmd/qemu into stagingPeter Maydell2024-03-082-308/+270
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Darwin Cocoa patches: - Add 'zoom-interpolation' to smooth scaled display with 'zoom-to-fit' (Carwyn) - Set clipsToBounds on macOS 14 to fix window clipping (David) - Use NSWindow's ability to resize (Akihiko) # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmXm/GcACgkQ4+MsLN6t # wN6/hw//erpUlp7YR1Ra+BtVbn9GA8UeXITYN03FSdz45b9DVTwA6C1kid3ljZWG # OhlT8QlXcp4lXRUrGkeVwF5EiBjTT5YGAlzQ9+FnZSo+KSMEtPm9ixmARJgzp0Lg # rLKmIA0YMEeWuknR/DngyRBFT+P3z4/IdTTtVYYd+vUnuWvmUYVk81hh6mlsBC3U # bDenS1IFGWET+FinNRhB8ib+JGbxsaij1m7rcIhOW06cg3uBLcgCbvFUGOWmHDAm # sVYoOq/4gXZMZyvlhzxtPt51OqIBa4wxRIKss4sDlpnvvb8sJ16PWGw7CMb/9TC8 # 0lTzaSNs8Z+fqU5bmfUMIuLu36j/8eN5nxvcrg+vwTXTPmJ6z0j7oP7jJod1cwFq # ZeIEtN5QBKCY5i+vYf7ve2frUUf3sS2TKjssFjghlfYksVMRkjLZjyLJVqTl3YP3 # 5FxOZ89bKvSFtbFczC0ErpAP9HpqplTGqmbUSAXA4EsGG/X4fkH7ElZS8fAgD5oB # nsEKS7BCXA5k9Vswu6wBO9bvFxp0puy/uIVabK8tOBZ5WjQeDPfM94QTEDGKYvK4 # Tpa4vnvdDJYB6x5WK3onVIAdYvuM0DT5/jECpdlNXQPmh3glfoHkAkM540gXtqfO # ooS6fvvDhdB0gj8FMd4AgiiL3h4Tt+yREq/DJ0kuHti1z1iqOnk= # =I4BB # -----END PGP SIGNATURE----- # gpg: Signature made Tue 05 Mar 2024 11:05:11 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'darwin-20240305' of https://github.com/philmd/qemu: ui/cocoa: Remove stretch_video flag ui/cocoa: Call console_select() with the BQL ui/cocoa: Make window resizable ui/cocoa: Remove normalWindow ui/cocoa: Let the platform toggle fullscreen ui/cocoa: Fix pause label coordinates ui/cocoa: Scale with NSView instead of Core Graphics ui/cocoa: Release specific mouse buttons ui/cocoa: Immediately call [-QemuCocoaView handleMouseEvent:buttons:] ui/cocoa: Split [-QemuCocoaView handleEventLocked:] ui/cocoa: Fix window clipping on macOS 14 ui/cocoa: add zoom-interpolation display option Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * ui/cocoa: Remove stretch_video flagAkihiko Odaki2024-03-051-13/+6
| | | | | | | | | | | | | | | | | | | | Evaluate [normalWindow styleMask] & NSWindowStyleMaskResizable instead. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Tested-by: Rene Engel <ReneEngel80@emailn.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-ID: <20240224-cocoa-v12-10-e89f70bdda71@daynix.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * ui/cocoa: Call console_select() with the BQLAkihiko Odaki2024-03-051-1/+3
| | | | | | | | | | | | | | | | | | | | | | [-QemuCocoaView displayConsole:] can be called anytime so explicitly take the BQL before it calls console_select(). Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Tested-by: Rene Engel <ReneEngel80@emailn.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-ID: <20240224-cocoa-v12-9-e89f70bdda71@daynix.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * ui/cocoa: Make window resizableAkihiko Odaki2024-03-051-0/+3
| | | | | | | | | | | | | | | | | | | | The window will be resizable when zoom-to-fit is on. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Tested-by: Rene Engel <ReneEngel80@emailn.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-ID: <20240224-cocoa-v12-8-e89f70bdda71@daynix.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * ui/cocoa: Remove normalWindowAkihiko Odaki2024-03-051-16/+17
| | | | | | | | | | | | | | | | | | | | | | | | QemuCocoaView used to have fullScreenWindow but now it's gone, so we do no longer have to call the window specifically "normalWindow". Instead, refer to it with [-QemuCocoaView window]. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Tested-by: Rene Engel <ReneEngel80@emailn.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-ID: <20240224-cocoa-v12-7-e89f70bdda71@daynix.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * ui/cocoa: Let the platform toggle fullscreenAkihiko Odaki2024-03-051-227/+181
| | | | | | | | | | | | | | | | | | | | | | It allows making the window full screen by clicking full screen button provided by the platform (the left-top green button) and save some code. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Tested-by: Rene Engel <ReneEngel80@emailn.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-ID: <20240224-cocoa-v12-6-e89f70bdda71@daynix.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * ui/cocoa: Fix pause label coordinatesAkihiko Odaki2024-03-051-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | A subview is positioned in the superview so the superview's frame should be used instead of one of the window to determine the coordinates. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Tested-by: Rene Engel <ReneEngel80@emailn.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-ID: <20240224-cocoa-v12-5-e89f70bdda71@daynix.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * ui/cocoa: Scale with NSView instead of Core GraphicsAkihiko Odaki2024-03-051-14/+10
| | | | | | | | | | | | | | | | | | | | Core Graphics is not accelerated and slow. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Tested-by: Rene Engel <ReneEngel80@emailn.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-ID: <20240224-cocoa-v12-4-e89f70bdda71@daynix.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * ui/cocoa: Release specific mouse buttonsAkihiko Odaki2024-03-051-21/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | ui/cocoa used to release all mouse buttons when it sees NSEventTypeLeftMouseUp, NSEventTypeRightMouseUp, or NSEventTypeOtherMouseUp, but it can instead release specific one according to the delivered event. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Tested-by: Rene Engel <ReneEngel80@emailn.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-ID: <20240224-cocoa-v12-3-e89f70bdda71@daynix.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * ui/cocoa: Immediately call [-QemuCocoaView handleMouseEvent:buttons:]Akihiko Odaki2024-03-051-57/+30
| | | | | | | | | | | | | | | | | | | | | | Instead of using mouse_event variable to tell to handle a mouse event later, immediately call [-QemuCocoaView handleMouseEvent:buttons:]. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Rene Engel <ReneEngel80@emailn.de> Message-ID: <20240224-cocoa-v12-2-e89f70bdda71@daynix.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * ui/cocoa: Split [-QemuCocoaView handleEventLocked:]Akihiko Odaki2024-03-051-33/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently [-QemuCocoaView handleEventLocked:] parses the passed event, stores operations to be done to variables, and perform them according to the variables. This construct will be cluttered with variables and hard to read when we need more different operations for different events. Split the methods so that we can call appropriate methods depending on events instead of relying on variables. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Tested-by: Rene Engel <ReneEngel80@emailn.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-ID: <20240224-cocoa-v12-1-e89f70bdda71@daynix.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * ui/cocoa: Fix window clipping on macOS 14David Parsons2024-03-051-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | macOS Sonoma changes the NSView.clipsToBounds to false by default where it was true in earlier version of macOS. This causes the window contents to be occluded by the frame at the top of the window. This fixes the issue by conditionally compiling the clipping on Sonoma to true. NSView only exposes the clipToBounds in macOS 14 and so has to be fixed via conditional compilation. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1994 Signed-off-by: David Parsons <dave@daveparsons.net> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-ID: <20240224140620.39200-1-dave@daveparsons.net> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * ui/cocoa: add zoom-interpolation display optionCarwyn Ellis2024-03-052-2/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Provides a new display option, zoom-interpolation, that enables interpolation of the scaled display when zoom-to-fit is enabled. Also provides a corresponding view menu item to allow this to be toggled as required. Signed-off-by: Carwyn Ellis <carwynellis@gmail.com> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-ID: <20231110161729.36822-2-carwynellis@gmail.com> [PMD: QAPI @zoom-interpolation since 9.0] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
* | Merge tag 'pull-target-arm-20240308' of ↵Peter Maydell2024-03-0831-457/+1963
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * Implement FEAT_ECV * STM32L4x5: Implement GPIO device * Fix 32-bit SMOPA * Refactor v7m related code from cpu32.c into its own file * hw/rtc/sun4v-rtc: Relicense to GPLv2-or-later # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmXrM50ZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3l3aD/9BDWm3LNSIyHQ0qFD1l6wc # JeAymSBecMD6sfRaPloLaB5HlU9AhLQWHe8Sa/hkWdYPhvhh6keESlVScJXi6Irq # wm3MuDJwr9QZgXWuHsEwXj4sve+O/MgDHcYSyEldbcyqjbivMCUKCGXeT2VxQftd # LarETxUTsdPeaWm3Lm11CkiO5r0DMJyebgVc6jloT9O1oK8szrkDix09U6eCGhXy # l1ep0KY2mk+MtoboDflD3W/Zu0LrAZ1159r4LqTMD2Hp9Tt222aDOjEKi+Qjns22 # E86YCy7kPcsHVOskF42SkZ8M044T/tCetKgnOHqn8hbTCW5uNT+zJNC1feAB92pi # 4xWErOfYy7d5UVzWfUYudGKrb91rr5h2jd1SWn2NeQtdmU8KyFEjQS1y4FNZvPTD # lrzyuTv8daeKSImq6JPzws/MJRh5I87TpRgKDg6hTJDaUCLu0yIuV9pkUsIdJ5mW # 01ol8tmDgpBRsxjJlIf40KxOt5SQ2VoYh7L8jgRjGv9DEP5hU1AkPqQGtyx7Wcd/ # ImRYQ/cOqircJPqX60DHljZDACVOzrFIEmpKvu45tt1On0iNXKCMuIl0vwI9XERx # CSgqIz7KDI5gNlruZQDyHvVehQZW7sJo9rH5RawqObsUHTlg5rLb++79Da2RWtbV # yvQLaI3qPngknz//1eAKxg== # =YmPl # -----END PGP SIGNATURE----- # gpg: Signature made Fri 08 Mar 2024 15:49:49 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20240308' of https://git.linaro.org/people/pmaydell/qemu-arm: target/arm: Move v7m-related code from cpu32.c into a separate file hw/rtc/sun4v-rtc: Relicense to GPLv2-or-later target/arm: Fix 32-bit SMOPA tests/qtest: Add STM32L4x5 GPIO QTest testcase hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC hw/gpio: Implement STM32L4x5 GPIO target/arm: Enable FEAT_ECV for 'max' CPU target/arm: Implement FEAT_ECV CNTPOFF_EL2 handling target/arm: Define CNTPCTSS_EL0 and CNTVCTSS_EL0 target/arm: Implement new FEAT_ECV trap bits target/arm: Don't allow RES0 CNTHCTL_EL2 bits to be written target/arm: use FIELD macro for CNTHCTL bit definitions target/arm: Timer _EL02 registers UNDEF for E2H == 0 target/arm: Move some register related defines to internals.h Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm: Move v7m-related code from cpu32.c into a separate fileThomas Huth2024-03-084-261/+296
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the code to a separate file so that we do not have to compile it anymore if CONFIG_ARM_V7M is not set. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-id: 20240308141051.536599-2-thuth@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hw/rtc/sun4v-rtc: Relicense to GPLv2-or-laterPeter Maydell2024-03-072-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sun4v RTC device model added under commit a0e893039cf2ce0 in 2016 was unfortunately added with a license of GPL-v3-or-later, which is not compatible with other QEMU code which has a GPL-v2-only license. Relicense the code in the .c and the .h file to GPL-v2-or-later, to make it compatible with the rest of QEMU. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Paolo Bonzini (for Red Hat) <pbonzini@redhat.com> Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Acked-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20240223161300.938542-1-peter.maydell@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm: Fix 32-bit SMOPARichard Henderson2024-03-074-34/+148
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While the 8-bit input elements are sequential in the input vector, the 32-bit output elements are not sequential in the output matrix. Do not attempt to compute 2 32-bit outputs at the same time. Cc: qemu-stable@nongnu.org Fixes: 23a5e3859f5 ("target/arm: Implement SME integer outer product") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2083 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240305163931.242795-1-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | tests/qtest: Add STM32L4x5 GPIO QTest testcaseInès Varhol2024-03-072-1/+553
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The testcase contains : - `test_idr_reset_value()` : Checks the reset values of MODER, OTYPER, PUPDR, ODR and IDR. - `test_gpio_output_mode()` : Checks that writing a bit in register ODR results in the corresponding pin rising or lowering, if this pin is configured in output mode. - `test_gpio_input_mode()` : Checks that a input pin set high or low externally results in the pin rising and lowering. - `test_pull_up_pull_down()` : Checks that a floating pin in pull-up/down mode is actually high/down. - `test_push_pull()` : Checks that a pin set externally is disconnected when configured in push-pull output mode, and can't be set externally while in this mode. - `test_open_drain()` : Checks that a pin set externally high is disconnected when configured in open-drain output mode, and can't be set high while in this mode. - `test_bsrr_brr()` : Checks that writing to BSRR and BRR has the desired result in ODR. - `test_clock_enable()` : Checks that GPIO clock is at the right frequency after enabling it. Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Message-id: 20240305210444.310665-4-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoCInès Varhol2024-03-076-18/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20240305210444.310665-3-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hw/gpio: Implement STM32L4x5 GPIOInès Varhol2024-03-077-1/+559
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Features supported : - the 8 STM32L4x5 GPIOs are initialized with their reset values (except IDR, see below) - input mode : setting a pin in input mode "externally" (using input irqs) results in an out irq (transmitted to SYSCFG) - output mode : setting a bit in ODR sets the corresponding out irq (if this line is configured in output mode) - pull-up, pull-down - push-pull, open-drain Difference with the real GPIOs : - Alternate Function and Analog mode aren't implemented : pins in AF/Analog behave like pins in input mode - floating pins stay at their last value - register IDR reset values differ from the real one : values are coherent with the other registers reset values and the fact that AF/Analog modes aren't implemented - setting I/O output speed isn't supported - locking port bits isn't supported - ADC function isn't supported - GPIOH has 16 pins instead of 2 pins - writing to registers LCKR, AFRL, AFRH and ASCR is ineffective Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20240305210444.310665-2-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm: Enable FEAT_ECV for 'max' CPUPeter Maydell2024-03-072-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable all FEAT_ECV features on the 'max' CPU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240301183219.2424889-9-peter.maydell@linaro.org
| * | target/arm: Implement FEAT_ECV CNTPOFF_EL2 handlingPeter Maydell2024-03-074-2/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When ID_AA64MMFR0_EL1.ECV is 0b0010, a new register CNTPOFF_EL2 is implemented. This is similar to the existing CNTVOFF_EL2, except that it controls a hypervisor-adjustable offset made to the physical counter and timer. Implement the handling for this register, which includes control/trap bits in SCR_EL3 and CNTHCTL_EL2. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240301183219.2424889-8-peter.maydell@linaro.org
| * | target/arm: Define CNTPCTSS_EL0 and CNTVCTSS_EL0Peter Maydell2024-03-071-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For FEAT_ECV, new registers CNTPCTSS_EL0 and CNTVCTSS_EL0 are defined, which are "self-synchronized" views of the physical and virtual counts as seen in the CNTPCT_EL0 and CNTVCT_EL0 registers (meaning that no barriers are needed around accesses to them to ensure that reads of them do not occur speculatively and out-of-order with other instructions). For QEMU, all our system registers are self-synchronized, so we can simply copy the existing implementation of CNTPCT_EL0 and CNTVCT_EL0 to the new register encodings. This means we now implement all the functionality required for ID_AA64MMFR0_EL1.ECV == 0b0001. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240301183219.2424889-7-peter.maydell@linaro.org
| * | target/arm: Implement new FEAT_ECV trap bitsPeter Maydell2024-03-072-5/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The functionality defined by ID_AA64MMFR0_EL1.ECV == 1 is: * four new trap bits for various counter and timer registers * the CNTHCTL_EL2.EVNTIS and CNTKCTL_EL1.EVNTIS bits which control scaling of the event stream. This is a no-op for us, because we don't implement the event stream (our WFE is a NOP): all we need to do is allow CNTHCTL_EL2.ENVTIS to be read and written. * extensions to PMSCR_EL1.PCT, PMSCR_EL2.PCT, TRFCR_EL1.TS and TRFCR_EL2.TS: these are all no-ops for us, because we don't implement FEAT_SPE or FEAT_TRF. * new registers CNTPCTSS_EL0 and NCTVCTSS_EL0 which are "self-sychronizing" views of the CNTPCT_EL0 and CNTVCT_EL0, meaning that no barriers are needed around their accesses. For us these are just the same as the normal views, because all our sysregs are inherently self-sychronizing. In this commit we implement the trap handling and permit the new CNTHCTL_EL2 bits to be written. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240301183219.2424889-6-peter.maydell@linaro.org
| * | target/arm: Don't allow RES0 CNTHCTL_EL2 bits to be writtenPeter Maydell2024-03-071-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't allow the guest to write CNTHCTL_EL2 bits which don't exist. This is not strictly architecturally required, but it is how we've tended to implement registers more recently. In particular, bits [19:18] are only present with FEAT_RME, and bits [17:12] will only be present with FEAT_ECV. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240301183219.2424889-5-peter.maydell@linaro.org
| * | target/arm: use FIELD macro for CNTHCTL bit definitionsPeter Maydell2024-03-072-7/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We prefer the FIELD macro over ad-hoc #defines for register bits; switch CNTHCTL to that style before we add any more bits. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240301183219.2424889-4-peter.maydell@linaro.org
| * | target/arm: Timer _EL02 registers UNDEF for E2H == 0Peter Maydell2024-03-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The timer _EL02 registers should UNDEF for invalid accesses from EL2 or EL3 when HCR_EL2.E2H == 0, not take a cp access trap. We were delivering the exception to EL2 with the wrong syndrome. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240301183219.2424889-3-peter.maydell@linaro.org
| * | target/arm: Move some register related defines to internals.hPeter Maydell2024-03-072-128/+128
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cpu.h has a lot of #defines relating to CPU register fields. Most of these aren't actually used outside target/arm code, so there's no point in cluttering up the cpu.h file with them. Move some easy ones to internals.h. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240301183219.2424889-2-peter.maydell@linaro.org
* | | Merge tag 'pull-riscv-to-apply-20240308-1' of ↵Peter Maydell2024-03-0850-347/+1213
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://github.com/alistair23/qemu into staging RISC-V PR for 9.0 * Update $ra with current $pc in trans_cm_jalt * Enable SPCR for SCPI virt machine * Allow large kernels to boot by moving the initrd further away in RAM * Sync hwprobe keys with kernel * Named features riscv,isa, 'svade' rework * FIX xATP_MODE validation * Add missing include guard in pmu.h * Add SRAT and SLIT ACPI tables * libqos fixes and add a riscv machine * Add Ztso extension * Use 'zfa' instead of 'Zfa' * Update KVM exts to Linux 6.8 * move ratified/frozen exts to non-experimental * Ensure mcountinhibit, mcounteren, scounteren, hcounteren are 32-bit * mark_vs_dirty() before loads and stores * Remove 'is_store' bool from load/store fns * Fix shift count overflow * Fix setipnum_le write emulation for APLIC MSI-mode * Fix in_clrip[x] read emulation * Fix privilege mode of G-stage translation for debugging * Fix ACPI MCFG table for virt machine # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmXq8joACgkQr3yVEwxT # gBMCRxAAvG1RsCxWhMjLYDEYuUhQkP2nd86PHJMrNxAeb5WUIrgrYyT6OLXpfuKN # 8Hz5sR1bJnZSxKfGSFIHoPVxvW788fg7c5fIgg9txEssEQYhd7rCCPALxdiu/zlb # 0fbfx9Ir0nb9qS6vQuT4dEddmljKYKPry8dH0anWI7SVIfdor2TTlP4xOAR88Yq7 # gdGIKvr7PrUhI5JdoWBe8R6w7vguT35EO6aiC+7PA+8AT1SXrxFrg86bYtDUffD+ # LktGcI7GhlIeosolodU8iNK7CdZTywRuyIQ+/KF4mmC7qaC8yJNVVTwX9/vXbH36 # dWIFkOv3VRnLBKt3/PW1DRZoUbSLpWjwH7WZsvQWPW5Ql717pGWId4eXSemxCFLN # u7gGZ29/1jxMuYue+FImHTbBf6fSV25VOfo5ZfR/AfzxLBbugsP56CPwfK3K2OBq # fQ+k3hl8iCx62rZrcAa69TuMBQJB5Q94NIFP1m5u/bPIZZhT311RVY1xx/dRCXnI # 9/7DiPUyMeV4np2j4crvs4/QVTqYvpt4U9ElYrMWUxsTUyBEGEaSzpRsR5FCRmSH # 2IrJsVWw5QsTlHukCMvxWIiWnYS5KIe764LsY31FNOlbl8eNJkyapc+BE8HWjgPa # xYROCWOL7T/E1BPJ7wbEBlzPhuJOndZX91Zbfq0n+SAYq4YnNu4= # =sCqM # -----END PGP SIGNATURE----- # gpg: Signature made Fri 08 Mar 2024 11:10:50 GMT # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20240308-1' of https://github.com/alistair23/qemu: (34 commits) target/riscv: fix ACPI MCFG table target/riscv: Fix privilege mode of G-stage translation for debugging hw/intc/riscv_aplic: Fix in_clrip[x] read emulation hw/intc/riscv_aplic: Fix setipnum_le write emulation for APLIC MSI-mode target/riscv: Fix shift count overflow trans_rvv.c.inc: remove 'is_store' bool from load/store fns trans_rvv.c.inc: mark_vs_dirty() before loads and stores target/riscv: mcountinhibit, mcounteren, scounteren, hcounteren is 32-bit target/riscv: move ratified/frozen exts to non-experimental target/riscv/kvm: update KVM exts to Linux 6.8 linux-headers: Update to Linux v6.8-rc6 tests: riscv64: Use 'zfa' instead of 'Zfa' linux-user/riscv: Add Ztso extension to hwprobe RISC-V: Add support for Ztso tests/libqos: add riscv/virt machine nodes hw/riscv/virt.c: make aclint compatible with 'qtest' accel hw/riscv/virt.c: add virtio-iommu-pci hotplug support hw/riscv/virt.c: create '/soc/pci@...' fdt node earlier hw/riscv/virt-acpi-build.c: Add SRAT and SLIT ACPI tables target/riscv: Add missing include guard in pmu.h ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/riscv: fix ACPI MCFG tableIlya Chugin2024-03-081-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MCFG segments should point to PCI configuration range, not BAR MMIO. Signed-off-by: Ilya Chugin <danger_mail@list.ru> Fixes: 55ecd83b36 ("hw/riscv/virt-acpi-build.c: Add IO controllers and devices") Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Message-ID: <180d236d-c8e4-411a-b4d2-632eb82092fa@list.ru> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | target/riscv: Fix privilege mode of G-stage translation for debuggingHiroaki Yamamoto2024-03-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | G-stage translation should be considered to be user-level access in riscv_cpu_get_phys_page_debug(), as already done in riscv_cpu_tlb_fill(). This fixes a bug that prevents gdb from reading memory while the VM is running in VS-mode. Signed-off-by: Hiroaki Yamamoto <hrak1529@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240228081028.35081-1-hrak1529@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | hw/intc/riscv_aplic: Fix in_clrip[x] read emulationAnup Patel2024-03-081-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The reads to in_clrip[x] registers return rectified input values of the interrupt sources. A rectified input value of an interrupt source is defined by the section "4.5.2 Source configurations (sourcecfg[1]–sourcecfg[1023])" of the RISC-V AIA specification as: "rectified input value = (incoming wire value) XOR (source is inverted)" Update the riscv_aplic_read_input_word() implementation to match the above. Fixes: e8f79343cfc8 ("hw/intc: Add RISC-V AIA APLIC device emulation") Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240306095722.463296-3-apatel@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | hw/intc/riscv_aplic: Fix setipnum_le write emulation for APLIC MSI-modeAnup Patel2024-03-081-4/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The writes to setipnum_le register in APLIC MSI-mode have special consideration for level-triggered interrupts as-per section "4.9.2 Special consideration for level-sensitive interrupt sources" of the RISC-V AIA specification. Particularly, the below text from the RISC-V specification defines the behaviour of writes to setipnum_le for level-triggered interrupts: "A second option is for the interrupt service routine to write the APLIC’s source identity number for the interrupt to the domain’s setipnum register just before exiting. This will cause the interrupt’s pending bit to be set to one again if the source is still asserting an interrupt, but not if the source is not asserting an interrupt." Fix setipnum_le write emulation for APLIC MSI-mode by implementing the above behaviour in riscv_aplic_set_pending() function. Fixes: e8f79343cfc8 ("hw/intc: Add RISC-V AIA APLIC device emulation") Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240306095722.463296-2-apatel@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | target/riscv: Fix shift count overflowdemin.han2024-03-081-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The result of (8 - 3 - vlmul) is negative when vlmul >= 6, and results in wrong vill. Signed-off-by: demin.han <demin.han@starfivetech.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240225174114.5298-1-demin.han@starfivetech.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | trans_rvv.c.inc: remove 'is_store' bool from load/store fnsDaniel Henrique Barboza2024-03-081-29/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After the 'mark_vs_dirty' changes from the previous patch the 'is_store' bool is unused in some load/store functions that were changed. Remove it. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240306171932.549549-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | trans_rvv.c.inc: mark_vs_dirty() before loads and storesDaniel Henrique Barboza2024-03-081-15/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While discussing a problem with how we're (not) setting vstart_eq_zero Richard had the following to say w.r.t the conditional mark_vs_dirty() calls on load/store functions [1]: "I think it's required to have stores set dirty unconditionally, before the operation. Consider a store that traps on the 2nd element, leaving vstart = 2, and exiting to the main loop via exception. The exception enters the kernel page fault handler. The kernel may need to fault in the page for the process, and in the meantime task switch. If vs dirty is not already set, the kernel won't know to save vector state on task switch." Do a mark_vs_dirty() before both loads and stores. [1] https://lore.kernel.org/qemu-riscv/72c7503b-0f43-44b8-aa82-fbafed2aac0c@linaro.org/ Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240306171932.549549-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | target/riscv: mcountinhibit, mcounteren, scounteren, hcounteren is 32-bitVadim Shakirov2024-03-082-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mcountinhibit, mcounteren, scounteren and hcounteren must always be 32-bit by privileged spec Signed-off-by: Vadim Shakirov <vadim.shakirov@syntacore.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20240202113919.18236-1-vadim.shakirov@syntacore.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | target/riscv: move ratified/frozen exts to non-experimentalDaniel Henrique Barboza2024-03-081-13/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | smaia and ssaia were ratified in August 25th 2023 [1]. zvfh and zvfhmin were ratified in August 2nd 2023 [2]. zfbfmin and zvfbf(min|wma) are frozen and moved to public review since Dec 16th 2023 [3]. zaamo and zalrsc are both marked as "Frozen" since January 24th 2024 [4]. [1] https://jira.riscv.org/browse/RVS-438 [2] https://jira.riscv.org/browse/RVS-871 [3] https://jira.riscv.org/browse/RVS-704 [4] https://jira.riscv.org/browse/RVS-1995 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240301144053.265964-1-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | target/riscv/kvm: update KVM exts to Linux 6.8Daniel Henrique Barboza2024-03-081-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | The last KVM extensions added were back in 6.6. Sync them to Linux 6.8. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240304134732.386590-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | linux-headers: Update to Linux v6.8-rc6Daniel Henrique Barboza2024-03-0823-112/+381
| | | | | | | | | | | | | | | | | | | | | | | | | | | The idea with this update is to get the latest KVM caps for RISC-V. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240304134732.386590-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | tests: riscv64: Use 'zfa' instead of 'Zfa'Christoph Müllner2024-03-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Running test-fcvtmod triggers the following deprecation warning: warning: CPU property 'Zfa' is deprecated. Please use 'zfa' instead Let's fix that. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240229180656.1208881-1-christoph.muellner@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>