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| * | target/arm: Convert LDAPR/STLR (imm) to decodetreePeter Maydell2023-06-192-84/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the instructions in the LDAPR/STLR (unscaled immediate) group to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230602155223.2040685-18-peter.maydell@linaro.org
| * | target/arm: Convert load (pointer auth) insns to decodetreePeter Maydell2023-06-192-67/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the instructions in the load/store register (pointer authentication) group ot decodetree: LDRAA, LDRAB. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230602155223.2040685-17-peter.maydell@linaro.org
| * | target/arm: Convert atomic memory ops to decodetreePeter Maydell2023-06-192-98/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the insns in the atomic memory operations group to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230602155223.2040685-16-peter.maydell@linaro.org
| * | target/arm: Convert LDR/STR reg+reg to decodetreePeter Maydell2023-06-192-87/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the LDR and STR instructions which take a register plus register offset to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230602155223.2040685-15-peter.maydell@linaro.org
| * | target/arm: Convert LDR/STR with 12-bit immediate to decodetreePeter Maydell2023-06-192-88/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the LDR and STR instructions which use a 12-bit immediate offset to decodetree. We can reuse the existing LDR and STR trans functions for these. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230602155223.2040685-14-peter.maydell@linaro.org
| * | target/arm: Convert ld/st reg+imm9 insns to decodetreePeter Maydell2023-06-192-118/+149
| | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the load and store instructions which use a 9-bit immediate offset to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230602155223.2040685-13-peter.maydell@linaro.org
| * | target/arm: Convert load/store-pair to decodetreePeter Maydell2023-06-192-196/+249
| | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the load/store register pair insns (LDP, STP, LDNP, STNP, LDPSW, STGP) to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230602155223.2040685-12-peter.maydell@linaro.org Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
| * | target/arm: Convert load reg (literal) group to decodetreePeter Maydell2023-06-192-54/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the "Load register (literal)" instruction class to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230602155223.2040685-11-peter.maydell@linaro.org
| * | target/arm: Convert LDXP, STXP, CASP, CAS to decodetreePeter Maydell2023-06-192-76/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the load/store exclusive pair (LDXP, STXP, LDAXP, STLXP), compare-and-swap pair (CASP, CASPA, CASPAL, CASPL), and compare-and swap (CAS, CASA, CASAL, CASL) instructions to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230602155223.2040685-10-peter.maydell@linaro.org
| * | target/arm: Convert load/store exclusive and ordered to decodetreePeter Maydell2023-06-192-62/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the instructions in the load/store exclusive (STXR, STLXR, LDXR, LDAXR) and load/store ordered (STLR, STLLR, LDAR, LDLAR) to decodetree. Note that for STLR, STLLR, LDAR, LDLAR this fixes an under-decoding in the legacy decoder where we were not checking that the RES1 bits in the Rs and Rt2 fields were set. The new function ldst_iss_sf() is equivalent to the existing disas_ldst_compute_iss_sf(), but it takes the pre-decoded 'ext' field rather than taking an undecoded two-bit opc field and extracting 'ext' from it. Once all the loads and stores have been converted to decodetree disas_ldst_compute_iss_sf() will be unused and can be deleted. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230602155223.2040685-9-peter.maydell@linaro.org
| * | target/arm: Convert exception generation instructions to decodetreePeter Maydell2023-06-192-106/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the exception generation instructions SVC, HVC, SMC, BRK and HLT to decodetree. The old decoder decoded the halting-debug insnns DCPS1, DCPS2 and DCPS3 just in order to then make them UNDEF; as with DRPS, we don't bother to decode them, but document the patterns in a64.decode. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230602155223.2040685-8-peter.maydell@linaro.org
| * | target/arm: Convert MSR (reg), MRS, SYS, SYSL to decodetreePeter Maydell2023-06-192-28/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert MSR (reg), MRS, SYS, SYSL to decodetree. For QEMU these are all essentially the same instruction (system register access). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230602155223.2040685-7-peter.maydell@linaro.org Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * | target/arm: Convert MSR (immediate) to decodetreePeter Maydell2023-06-192-115/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the MSR (immediate) insn to decodetree. Our implementation has basically no commonality between the different destinations, so we decode the destination register in a64.decode. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230602155223.2040685-6-peter.maydell@linaro.org
| * | target/arm: Convert CFINV, XAFLAG and AXFLAG to decodetreePeter Maydell2023-06-192-27/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the CFINV, XAFLAG and AXFLAG insns to decodetree. The old decoder handles these in handle_msr_i(), but the architecture defines them as separate instructions from MSR (immediate). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230602155223.2040685-5-peter.maydell@linaro.org
| * | target/arm: Convert barrier insns to decodetreePeter Maydell2023-06-192-53/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the insns in the "Barriers" instruction class to decodetree: CLREX, DSB, DMB, ISB and SB. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230602155223.2040685-4-peter.maydell@linaro.org Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * | target/arm: Convert hint instruction space to decodetreePeter Maydell2023-06-192-123/+185
| | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the various instructions in the hint instruction space to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230602155223.2040685-3-peter.maydell@linaro.org
| * | target/arm: Consistently use finalize_memop_asimd() for ASIMD loads/storesPeter Maydell2023-06-191-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the recent refactoring we missed a few places which should be calling finalize_memop_asimd() for ASIMD loads and stores but instead are just calling finalize_memop(); fix these. For the disas_ldst_single_struct() and disas_ldst_multiple_struct() cases, this is not a behaviour change because there the size is never MO_128 and the two finalize functions do the same thing. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
| * | target/arm: Pass memop to gen_mte_check1_mmuidx() in reg_imm9 decodePeter Maydell2023-06-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In disas_ldst_reg_imm9() we missed one place where a call to a gen_mte_check* function should now be passed the memop we have created rather than just being passed the size. Fix this. Fixes: 0a9091424d ("target/arm: Pass memop to gen_mte_check1*") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * | target/arm: Return correct result for LDG when ATA=0Peter Maydell2023-06-191-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The LDG instruction loads the tag from a memory address (identified by [Xn + offset]), and then merges that tag into the destination register Xt. We implemented this correctly for the case when allocation tags are enabled, but didn't get it right when ATA=0: instead of merging the tag bits into Xt, we merged them into the memory address [Xn + offset] and then set Xt to that. Merge the tag bits into the old Xt value, as they should be. Cc: qemu-stable@nongnu.org Fixes: c15294c1e36a7dd9b25 ("target/arm: Implement LDG, STG, ST2G instructions") Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | target/arm: Fix return value from LDSMIN/LDSMAX 8/16 bit atomicsPeter Maydell2023-06-191-2/+16
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The atomic memory operations are supposed to return the old memory data value in the destination register. This value is not sign-extended, even if the operation is the signed minimum or maximum. (In the pseudocode for the instructions the returned data value is passed to ZeroExtend() to create the value in the register.) We got this wrong because we were doing a 32-to-64 zero extend on the result for 8 and 16 bit data values, rather than the correct amount of zero extension. Fix the bug by using ext8u and ext16u for the MO_8 and MO_16 data sizes rather than ext32u. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230602155223.2040685-2-peter.maydell@linaro.org
* | Merge tag 'pull-loongarch-20230616' of https://gitlab.com/gaosong/qemu into ↵Richard Henderson2023-06-166-38/+235
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging pull-loongarch-20230616 # -----BEGIN PGP SIGNATURE----- # # iLMEAAEIAB0WIQS4/x2g0v3LLaCcbCxAov/yOSY+3wUCZIwysgAKCRBAov/yOSY+ # 39FYA/465KtY2jDt4xG6AdwZDHckfxZQWlrfhyZvtapOkUG4AprOBV2nSS/ukyD4 # V8bg2/6cLS0GRKfDsqA3DcxSASWCAggIU4fTSj+DlYOZhNUIq14qzwqciZnO5CIH # QDczSqu2LKRdP9j6MCtzIaZq/8pPDcOlgm7Dyct/kDo/64E2sg== # =rD4j # -----END PGP SIGNATURE----- # gpg: Signature made Fri 16 Jun 2023 12:00:18 PM CEST # gpg: using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF # gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C 6C2C 40A2 FFF2 3926 3EDF * tag 'pull-loongarch-20230616' of https://gitlab.com/gaosong/qemu: target/loongarch: Fix CSR.DMW0-3.VSEG check hw/loongarch: Supplement cpu topology arguments hw/loongarch: Add numa support hw/intc: Set physical cpuid route for LoongArch ipi device hw/loongarch/virt: Add cpu arch_id support Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | target/loongarch: Fix CSR.DMW0-3.VSEG checkJiajie Chen2023-06-161-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The previous code checks whether the highest 16 bits of virtual address equal to that of CSR.DMW0-3. This is incorrect according to the spec, and is corrected to compare only the highest four bits instead. Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230614065556.2397513-1-c@jia.je> Signed-off-by: Song Gao <gaosong@loongson.cn>
| * | hw/loongarch: Supplement cpu topology argumentsTianrui Zhao2023-06-162-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Supplement LoongArch cpu topology arguments, including support socket and threads per core. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230613123251.2471878-1-zhaotianrui@loongson.cn>
| * | hw/loongarch: Add numa supportTianrui Zhao2023-06-163-24/+139
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Implement some functions for LoongArch numa support; 2. Implement fdt_add_memory_node() for fdt; 3. build_srat() fills node_id and adds build numa memory. Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230613122613.2471743-1-zhaotianrui@loongson.cn>
| * | hw/intc: Set physical cpuid route for LoongArch ipi deviceTianrui Zhao2023-06-163-7/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LoongArch ipi device uses physical cpuid to route to different vcpus rather logical cpuid, and the physical cpuid is the same with cpuid in acpi dsdt and srat table. Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230613120552.2471420-3-zhaotianrui@loongson.cn>
| * | hw/loongarch/virt: Add cpu arch_id supportTianrui Zhao2023-06-162-8/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With acpi madt table, there is cpu physical coreid, which may be different with logical id in qemu. This patch adds cpu arch_id support, and fill madt table with arch_id. For the present cpu arch_id is still equal to logical id. Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230613120552.2471420-2-zhaotianrui@loongson.cn>
* | | Merge tag 'xenpvh5-tag' of https://gitlab.com/sstabellini/qemu into stagingRichard Henderson2023-06-1619-1009/+1349
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | xenpvh5 # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEE0E4zq6UfZ7oH0wrqiU+PSHDhrpAFAmSLo0QACgkQiU+PSHDh # rpB1Gw/9H5Cx7wQZVyKfFwnyOoP2QTedCISxC0HL5qFmUGcJY21gXaJZ10JaU/HM # zHEJj2M17EgVCTkZVqZeKuj+nzyjbRKatT3YmFqKqFNNt5M1yQxC9BfVgso4PND/ # SY0/8BvqumgJEqD3sf76KbQAILKwahPtA42LTM7S7r2ZsmQpvmOpdOhCVugpnqs/ # FheP8N6hdlZ7GnRGtXv9QnKxMVThuE3mRCUWCyYsV/Roz6uvPsvskrdSeC3LzzBd # Ewq56vB+qQg+WbNTgK2BcVOzV/89k9tjWsUnamfhjD2lUxfHrne1FBclhKMcHhUv # T53zjhxjlRfmzUxC4917Krt4Tw/AaDW7v1pn6RokUq5U059Wb8q0IjzL75FOeD3o # e9DNp+RR8py44ejfi2WHR7jqayMPVIO86uJ3usshiZ9YgK5efFAtlwN/KNR5JX8k # Y1BR9O8BebtRymljtiLWUFXlu3xywGSA23KotT7XtzXKEaTZkIHdI395YKksYPkG # pil0C0bh5ZW3ZWd4M/CNcVOb69R53p15O77mjmKtjnkQYJAPD6Kbc9thZ1zdWwPR # ivFPdiTJb0FElS0ywZwezKYRKXje6E9ejXgAzgFuZI/rFdeO0HfkifiNoro1NAxK # g4V+LE5oPt09GpL2nuHrh/y9g9MnLlXyNBhPV0CRelU6fPKIk1w= # =543t # -----END PGP SIGNATURE----- # gpg: Signature made Fri 16 Jun 2023 01:48:20 AM CEST # gpg: using RSA key D04E33ABA51F67BA07D30AEA894F8F4870E1AE90 # gpg: Good signature from "Stefano Stabellini <sstabellini@kernel.org>" [unknown] # gpg: aka "Stefano Stabellini <stefano.stabellini@eu.citrix.com>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: D04E 33AB A51F 67BA 07D3 0AEA 894F 8F48 70E1 AE90 * tag 'xenpvh5-tag' of https://gitlab.com/sstabellini/qemu: test/qtest: add xepvh to skip list for qtest meson.build: enable xenpv machine build for ARM hw/arm: introduce xenpvh machine meson.build: do not set have_xen_pci_passthrough for aarch64 targets hw/xen/xen-hvm-common: Use g_new and error_report hw/xen/xen-hvm-common: skip ioreq creation on ioreq registration failure include/hw/xen/xen_common: return error from xen_create_ioreq_server xen-hvm: reorganize xen-hvm and move common function to xen-hvm-common hw/i386/xen/xen-hvm: move x86-specific fields out of XenIOState hw/i386/xen: rearrange xen_hvm_init_pc hw/i386/xen/: move xen-mapcache.c to hw/xen/ Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | | test/qtest: add xepvh to skip list for qtestVikram Garhwal2023-06-151-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Like existing xen machines, xenpvh also cannot be used for qtest. Signed-off-by: Vikram Garhwal <vikram.garhwal@amd.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
| * | | meson.build: enable xenpv machine build for ARMVikram Garhwal2023-06-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add CONFIG_XEN for aarch64 device to support build for ARM targets. Signed-off-by: Vikram Garhwal <vikram.garhwal@amd.com> Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
| * | | hw/arm: introduce xenpvh machineVikram Garhwal2023-06-156-0/+229
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new machine xenpvh which creates a IOREQ server to register/connect with Xen Hypervisor. Optional: When CONFIG_TPM is enabled, it also creates a tpm-tis-device, adds a TPM emulator and connects to swtpm running on host machine via chardev socket and support TPM functionalities for a guest domain. Extra command line for aarch64 xenpvh QEMU to connect to swtpm: -chardev socket,id=chrtpm,path=/tmp/myvtpm2/swtpm-sock \ -tpmdev emulator,id=tpm0,chardev=chrtpm \ -machine tpm-base-addr=0x0c000000 \ swtpm implements a TPM software emulator(TPM 1.2 & TPM 2) built on libtpms and provides access to TPM functionality over socket, chardev and CUSE interface. Github repo: https://github.com/stefanberger/swtpm Example for starting swtpm on host machine: mkdir /tmp/vtpm2 swtpm socket --tpmstate dir=/tmp/vtpm2 \ --ctrl type=unixio,path=/tmp/vtpm2/swtpm-sock & Signed-off-by: Vikram Garhwal <vikram.garhwal@amd.com> Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
| * | | meson.build: do not set have_xen_pci_passthrough for aarch64 targetsStefano Stabellini2023-06-151-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | have_xen_pci_passthrough is only used for Xen x86 VMs. Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
| * | | hw/xen/xen-hvm-common: Use g_new and error_reportVikram Garhwal2023-06-151-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace g_malloc with g_new and perror with error_report. Signed-off-by: Vikram Garhwal <vikram.garhwal@amd.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Reviewed-by: Paul Durrant <paul@xen.org>
| * | | hw/xen/xen-hvm-common: skip ioreq creation on ioreq registration failureStefano Stabellini2023-06-151-19/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On ARM it is possible to have a functioning xenpv machine with only the PV backends and no IOREQ server. If the IOREQ server creation fails continue to the PV backends initialization. Also, moved the IOREQ registration and mapping subroutine to new function xen_do_ioreq_register(). Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com> Signed-off-by: Vikram Garhwal <vikram.garhwal@amd.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Reviewed-by: Paul Durrant <paul@xen.org>
| * | | include/hw/xen/xen_common: return error from xen_create_ioreq_serverStefano Stabellini2023-06-151-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is done to prepare for enabling xenpv support for ARM architecture. On ARM it is possible to have a functioning xenpv machine with only the PV backends and no IOREQ server. If the IOREQ server creation fails, continue to the PV backends initialization. Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com> Signed-off-by: Vikram Garhwal <vikram.garhwal@amd.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Reviewed-by: Paul Durrant <paul@xen.org>
| * | | xen-hvm: reorganize xen-hvm and move common function to xen-hvm-commonStefano Stabellini2023-06-158-968/+1054
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch does following: 1. creates arch_handle_ioreq() and arch_xen_set_memory(). This is done in preparation for moving most of xen-hvm code to an arch-neutral location, move the x86-specific portion of xen_set_memory to arch_xen_set_memory. Also, move handle_vmport_ioreq to arch_handle_ioreq. 2. Pure code movement: move common functions to hw/xen/xen-hvm-common.c Extract common functionalities from hw/i386/xen/xen-hvm.c and move them to hw/xen/xen-hvm-common.c. These common functions are useful for creating an IOREQ server. xen_hvm_init_pc() contains the architecture independent code for creating and mapping a IOREQ server, connecting memory and IO listeners, initializing a xen bus and registering backends. Moved this common xen code to a new function xen_register_ioreq() which can be used by both x86 and ARM machines. Following functions are moved to hw/xen/xen-hvm-common.c: xen_vcpu_eport(), xen_vcpu_ioreq(), xen_ram_alloc(), xen_set_memory(), xen_region_add(), xen_region_del(), xen_io_add(), xen_io_del(), xen_device_realize(), xen_device_unrealize(), cpu_get_ioreq_from_shared_memory(), cpu_get_ioreq(), do_inp(), do_outp(), rw_phys_req_item(), read_phys_req_item(), write_phys_req_item(), cpu_ioreq_pio(), cpu_ioreq_move(), cpu_ioreq_config(), handle_ioreq(), handle_buffered_iopage(), handle_buffered_io(), cpu_handle_ioreq(), xen_main_loop_prepare(), xen_hvm_change_state_handler(), xen_exit_notifier(), xen_map_ioreq_server(), destroy_hvm_domain() and xen_shutdown_fatal_error() 3. Removed static type from below functions: 1. xen_region_add() 2. xen_region_del() 3. xen_io_add() 4. xen_io_del() 5. xen_device_realize() 6. xen_device_unrealize() 7. xen_hvm_change_state_handler() 8. cpu_ioreq_pio() 9. xen_exit_notifier() 4. Replace TARGET_PAGE_SIZE with XC_PAGE_SIZE to match the page side with Xen. Signed-off-by: Vikram Garhwal <vikram.garhwal@amd.com> Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com> Acked-by: Stefano Stabellini <sstabellini@kernel.org>
| * | | hw/i386/xen/xen-hvm: move x86-specific fields out of XenIOStateStefano Stabellini2023-06-151-31/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation to moving most of xen-hvm code to an arch-neutral location, move: - shared_vmport_page - log_for_dirtybit - dirty_bitmap - suspend - wakeup out of XenIOState struct as these are only used on x86, especially the ones related to dirty logging. Updated XenIOState can be used for both aarch64 and x86. Also, remove free_phys_offset as it was unused. Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com> Signed-off-by: Vikram Garhwal <vikram.garhwal@amd.com> Reviewed-by: Paul Durrant <paul@xen.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
| * | | hw/i386/xen: rearrange xen_hvm_init_pcVikram Garhwal2023-06-151-24/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation to moving most of xen-hvm code to an arch-neutral location, move non IOREQ references to: - xen_get_vmport_regs_pfn - xen_suspend_notifier - xen_wakeup_notifier - xen_ram_init towards the end of the xen_hvm_init_pc() function. This is done to keep the common ioreq functions in one place which will be moved to new function in next patch in order to make it common to both x86 and aarch64 machines. Signed-off-by: Vikram Garhwal <vikram.garhwal@amd.com> Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com> Reviewed-by: Paul Durrant <paul@xen.org>
| * | | hw/i386/xen/: move xen-mapcache.c to hw/xen/Vikram Garhwal2023-06-156-6/+10
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | xen-mapcache.c contains common functions which can be used for enabling Xen on aarch64 with IOREQ handling. Moving it out from hw/i386/xen to hw/xen to make it accessible for both aarch64 and x86. Signed-off-by: Vikram Garhwal <vikram.garhwal@amd.com> Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com> Reviewed-by: Paul Durrant <paul@xen.org>
* | | Merge tag 'pull-aspeed-20230615' of https://github.com/legoater/qemu into ↵Richard Henderson2023-06-169-26/+160
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging aspeed queue: * extension of the rainier machine with VPD contents * fixes for Coverity issues * new "bmc-console" machine option * new "vfp-d32" ARM CPU property # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmSLQjcACgkQUaNDx8/7 # 7KE/XRAAkMZN7o+5vR7NocAbj9FasFq8G5Du8L5V52k7kjhmTIMtY2StKyXYBI4o # MXe89P88gT5kmwAzyzFVkbLwZcS9wnA/71Pv+dc9Fe9fK9Q+1Tn9AGR+nJM7ZsOk # qOP2SUfKqoeHBlFaWJAFSs09jPOzQr0elB55YErwXkjkJN9+PcI5l8E3aZGZz9qQ # SZY1JpBYXidoF3bqEfQUs1SzszfFOrW9QYO5s93EYfyXTsV93JPfKVviy8DtNQjc # EE+mSgvGSELu8ODMzk/b+O1OQ39S+AJ/qoqhYFZWrsxhROfLiFxV8ksAX52sdJeY # z7hot8KUaAka2to+7OFQJn6N9i12MsSZ17XQhoOKC0IMwDtFIMFTIm7fkwxuJh9m # ktiadL6MEWZCiiq8jLkM1sz/V9BcVEV/zI2WAJnOh8tniGG9U2xWGL7Ijf2Lnxs7 # P8cjT0XfBB6LzyEk1OSCScoBBdc3bHJD4xUpnr1ehscg58gyaPVMkkTziqWbeVH1 # CvxmGufS0jYXYS5R4/U4PEY5FQdBww77x/JTXx/NYc0ZWetgKCA/jqFtSgINgtdd # jKFHPnvOv8NWDagy/+Vb0xZPHbXoYkliMtAV789FujI/6VzPrdW8YljPos/rX/oY # b6/Yh1vCwuzVRut5wqMNefmX1ez36rdy3KDvg99Pu3Ln4QqBXhE= # =qTHL # -----END PGP SIGNATURE----- # gpg: Signature made Thu 15 Jun 2023 06:54:15 PM CEST # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-aspeed-20230615' of https://github.com/legoater/qemu: target/arm: Allow users to set the number of VFP registers aspeed: Introduce a "bmc-console" machine option aspeed: Use the boot_rom region of the fby35 machine aspeed: Introduce a boot_rom region at the machine level aspeed/hace: Initialize g_autofree pointer hw/arm/aspeed: Add VPD data for Rainier machine Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | target/arm: Allow users to set the number of VFP registersCédric Le Goater2023-06-153-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cortex A7 CPUs with an FPU implementing VFPv4 without NEON support have 16 64-bit FPU registers and not 32 registers. Let users set the number of VFP registers with a CPU property. The primary use case of this property is for the Cortex A7 of the Aspeed AST2600 SoC. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * | aspeed: Introduce a "bmc-console" machine optionCédric Le Goater2023-06-152-2/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most of the Aspeed machines use the UART5 device for the boot console, and QEMU connects the first serial Chardev to this SoC device for this purpose. See routine connect_serial_hds_to_uarts(). Nevertheless, some machines use another boot console, such as the fuji, and commit 5d63d0c76c ("hw/arm/aspeed: Allow machine to set UART default") introduced a SoC class attribute 'uart_default' and property to be able to change the boot console device. It was later changed by commit d2b3eaefb4 ("aspeed: Refactor UART init for multi-SoC machines"). The "bmc-console" machine option goes a step further and lets the user define the UART device from the QEMU command line without introducing a new machine definition. For instance, to use device UART3 (mapped on /dev/ttyS2 under Linux) instead of the default UART5, one would use : -M ast2500-evb,bmc-console=uart3 Cc: Abhishek Singh Dagur <abhishek@drut.io> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * | aspeed: Use the boot_rom region of the fby35 machineCédric Le Goater2023-06-151-14/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change completes commits 5aa281d757 ("aspeed: Introduce a spi_boot region under the SoC") and 8b744a6a47 ("aspeed: Add a boot_rom overlap region in the SoC spi_boot container") which introduced a spi_boot container at the SoC level to map the boot rom region as an overlap. It also fixes a Coverity report (CID 1508061) for a memory leak warning when the QEMU process exits by using an bmc_boot_rom MemoryRegion available at the machine level. Cc: Peter Delevoryas <peter@pjd.dev> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * | aspeed: Introduce a boot_rom region at the machine levelCédric Le Goater2023-06-151-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This should also avoid Coverity to report a memory leak warning when the QEMU process exits. See CID 1508061. Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * | aspeed/hace: Initialize g_autofree pointerCédric Le Goater2023-06-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As mentioned in docs/devel/style.rst "Automatic memory deallocation": * Variables declared with g_auto* MUST always be initialized, otherwise the cleanup function will use uninitialized stack memory This avoids QEMU to coredump when running the "hash test" command under Zephyr. Cc: Steven Lee <steven_lee@aspeedtech.com> Cc: Joel Stanley <joel@jms.id.au> Cc: qemu-stable@nongnu.org Fixes: c5475b3f9a ("hw: Model ASPEED's Hash and Crypto Engine") Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Message-Id: <20230421131547.2177449-1-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * | hw/arm/aspeed: Add VPD data for Rainier machineNinad Palsule2023-06-153-3/+53
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current modeling of Rainier machine creates zero filled VPDs(EEPROMs). This makes some services and applications unhappy and causing them to fail. Hence this drop adds some fabricated data for system and BMC FRU so that vpd services are happy and active. Tested: - The system-vpd.service is active. - VPD service related to bmc is active. Signed-off-by: Ninad Palsule <ninad@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> [ clg: commit title cleanup ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
* | Merge tag 'pull-riscv-to-apply-20230614' of ↵Richard Henderson2023-06-1429-1102/+1442
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://github.com/alistair23/qemu into staging Second RISC-V PR for 8.1 * Skip Vector set tail when vta is zero * Move zc* out of the experimental properties * Mask the implicitly enabled extensions in isa_string based on priv version * Rework CPU extension validation and validate MISA changes * Fixup PMP TLB cacheing errors * Writing to pmpaddr and MML/MMWP correctly triggers TLB flushes * Fixup PMP bypass checks * Deny access if access is partially inside a PMP entry * Correct OpenTitanState parent type/size * Fix QEMU crash when NUMA nodes exceed available CPUs * Fix pointer mask transformation for vector address * Updates and improvements for Smstateen * Support disas for Zcm* extensions * Support disas for Z*inx extensions * Remove unused decomp_rv32/64 value for vector instructions * Enable PC-relative translation * Assume M-mode FW in pflash0 only when "-bios none" * Support using pflash via -blockdev option * Add vector registers to log * Clean up reference of Vector MTYPE * Remove the check for extra Vector tail elements * Smepmp: Return error when access permission not allowed in PMP * Fixes for smsiaddrcfg and smsiaddrcfgh in AIA # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmSJFRoACgkQr3yVEwxT # gBMUkg/8Cuhqpx+zy7MeouVkyhEjUuhtCWyr0WVZBJzDkVEOrlY6TyR0hb5/o1Js # LZf6ZMF6JQDN78bmUct8yFBZBGafey5tyonDCsnD7CNQuLPf2NSjTHhu9n5hKFqF # F8Mpn9iFu6k1pr0iF7FbCccVWuDb3P4h2PaM0iFhmf4uz42BCMYdgJThhvv38xlt # jr6A3dcjTpp8yB+iRCuhL2IU2XVee0XBiDUECqRXd0gmtOtqJNST8L+l8YkLy1VO # WUMe8RCO6NMP7BLJ383WwCDeiFTo0mJebZQ0eR/G1xEhy7c8BBMh/CgQmq2F3wDZ # Q0biaeozADgAaCC7aOAHI+1sAoMhOm1v2WhIVmh+XXUqT9856cKwc7DUPBmzb9Sj # N5Zh+t9WCnZG7qpfxvkDF0Y/aRODMHZ1BW5L/ky9yBtyuRwXOJ6VycZTFyRkSwnN # Gd/s9IClDOP1IP5s4TSMGGdelk4lH97x7fZE/2hxn59lp761JtMxbaEceBtqaBh8 # zNMTNN/KHs8LeiIBI2ZZ+nQav452Y6XYBivQ7OdsI8xkjnjG9gfgXXjvX1TIh0ow # Hy5ZxtAtjXty49Gmjkx5VcBx4auJcnRDlLTzoZjTxq1te+gEWpw6O1EsEKasVLZe # uN6PxTOxS3nHvRvPgQc1xNUdhDRqBaYsju6b9YmMxz1uefAjGM0= # =fOTc # -----END PGP SIGNATURE----- # gpg: Signature made Wed 14 Jun 2023 03:17:14 AM CEST # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20230614' of https://github.com/alistair23/qemu: (60 commits) hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only. target/riscv: Smepmp: Return error when access permission not allowed in PMP target/riscv/vector_helper.c: Remove the check for extra tail elements target/riscv/vector_helper.c: clean up reference of MTYPE target/riscv: Fix initialized value for cur_pmmask util/log: Add vector registers to log docs/system: riscv: Add pflash usage details riscv/virt: Support using pflash via -blockdev option hw/riscv: virt: Assume M-mode FW in pflash0 only when "-bios none" target/riscv: Remove pc_succ_insn from DisasContext target/riscv: Enable PC-relative translation target/riscv: Use true diff for gen_pc_plus_diff target/riscv: Change gen_set_pc_imm to gen_update_pc target/riscv: Change gen_goto_tb to work on displacements target/riscv: Introduce cur_insn_len into DisasContext target/riscv: Fix target address to update badaddr disas/riscv.c: Remove redundant parentheses disas/riscv.c: Fix lines with over 80 characters disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructions disas/riscv.c: Support disas for Z*inx extensions ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only.Tommy Wu2023-06-141-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the `The RISC-V Advanced Interrupt Architecture` document, if register `mmsiaddrcfgh` of the domain has bit L set to one, then `smsiaddrcfg` and `smsiaddrcfgh` are locked as read-only alongside `mmsiaddrcfg` and `mmsiaddrcfgh`. Signed-off-by: Tommy Wu <tommy.wu@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Anup Patel <anup@brainfault.org> Message-Id: <20230609055936.3925438-1-tommy.wu@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | target/riscv: Smepmp: Return error when access permission not allowed in PMPHimanshu Chauhan2023-06-131-8/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On an address match, skip checking for default permissions and return error based on access defined in PMP configuration. v3 Changes: o Removed explicit return of boolean value from comparision of priv/allowed_priv v2 Changes: o Removed goto to return in place when address matches o Call pmp_hart_has_privs_default at the end of the loop Fixes: 90b1fafce06 ("target/riscv: Smepmp: Skip applying default rules when address matches") Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-Id: <20230605164548.715336-1-hchauhan@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | target/riscv/vector_helper.c: Remove the check for extra tail elementsXiao Wang2023-06-131-16/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 752614cab8e6 ("target/riscv: rvv: Add tail agnostic for vector load / store instructions") added an extra check for LMUL fragmentation, intended for setting the "rest tail elements" in the last register for a segment load insn. Actually, the max_elements derived in vext_ld*() won't be a fraction of vector register size, since the lmul encoded in desc is emul, which has already been adjusted to 1 for LMUL fragmentation case by vext_get_emul() in trans_rvv.c.inc, for ld_stride(), ld_us(), ld_index() and ldff(). Besides, vext_get_emul() has also taken EEW/SEW into consideration, so no need to call vext_get_total_elems() which would base on the emul to derive another emul, the second emul would be incorrect when esz differs from sew. Thus this patch removes the check for extra tail elements. Fixes: 752614cab8e6 ("target/riscv: rvv: Add tail agnostic for vector load / store instructions") Signed-off-by: Xiao Wang <xiao.w.wang@intel.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-Id: <20230607091646.4049428-1-xiao.w.wang@intel.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | target/riscv/vector_helper.c: clean up reference of MTYPEXiao Wang2023-06-131-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's no code using MTYPE, which was a concept used in older vector implementation. Signed-off-by: Xiao Wang <xiao.w.wang@intel.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-Id: <20230608053517.4102648-1-xiao.w.wang@intel.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>