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* 9pfs: make V9fsPath usable via P9Array APIChristian Schoenebeck2021-10-272-0/+4
| | | | | Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Message-Id: <79a0ddf8375f6c95f0565ef155a1bf1e9387664f.1633097129.git.qemu_oss@crudebyte.com>
* 9pfs: make V9fsString usable via P9Array APIChristian Schoenebeck2021-10-272-0/+5
| | | | | Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Message-Id: <ce9f7a0a63585dc27f4545c485109efbec1251da.1633097129.git.qemu_oss@crudebyte.com>
* fsdev/p9array.h: check scalar type in P9ARRAY_NEW()Christian Schoenebeck2021-10-271-0/+6
| | | | | | | | | | Make sure at compile time that the scalar type of the array requested to be created via P9ARRAY_NEW() matches the scalar type of the passed auto reference variable (unique pointer). Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Message-Id: <c1965e2a096835dc9e1d4d659dfb15d96755cbe0.1633097129.git.qemu_oss@crudebyte.com>
* 9pfs: introduce P9ArrayChristian Schoenebeck2021-10-271-0/+154
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implements deep auto free of arrays while retaining common C-style squared bracket access. Main purpose of this API is to get rid of error prone individual array deallocation pathes in user code, i.e. turning something like this: void doSomething(size_t n) { Foo *foos = malloc(n * sizeof(Foo)); for (...) { foos[i].s = malloc(...); if (...) { goto out; } } out: if (...) { for (...) { /* deep deallocation */ free(foos[i].s); } /* array deallocation */ free(foos); } } into something more simple and safer like: void doSomething(size_t n) { P9ARRAY_REF(Foo) foos = NULL; P9ARRAY_NEW(Foo, foos, n); for (...) { foos[i].s = malloc(...); if (...) { return; /* array auto freed here */ } } /* array auto freed here */ } Unlike GArray, P9Array does not require special macros, function calls or struct member dereferencing to access the individual array elements: C-array = P9Array: vs. GArray: for (...) { | for (...) { ... = arr[i].m; | ... = g_array_index(arr, Foo, i).m; arr[i].m = ... ; | g_array_index(arr, Foo, i).m = ... ; } | } So existing C-style array code can be retained with only very little changes; basically limited to replacing array allocation call and of course removing individual array deallocation pathes. In this initial version P9Array only supports the concept of unique pointers, i.e. it does not support reference counting. The array (and all dynamically allocated memory of individual array elements) is auto freed once execution leaves the scope of the reference variable (unique pointer) associated with the array. Internally a flex array struct is used in combination with macros spanned over a continuous memory space for both the array's meta data (private) and the actual C-array user data (public): struct P9Array##scalar_type { size_t len; /* private, hidden from user code */ scalar_type first[]; /* public, directly exposed to user code */ }; Which has the advantage that the compiler automatically takes care about correct padding, alignment and overall size for all scalar data types on all systems and that the user space exposed pointer can directly be translated back and forth between user space C-array pointer and internal P9Array struct whenever needed, in a type-safe manner. This header file is released under MIT license, to allow this file being used in other C-projects as well. The common QEMU license GPL2+ might have construed a conflict for other projects. Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Message-Id: <a954ef47b5ac26085a16c5c2aec8695374e0424d.1633097129.git.qemu_oss@crudebyte.com>
* 9pfs: simplify blksize_to_iounit()Christian Schoenebeck2021-10-271-2/+1
| | | | | | | | | | | Use QEMU_ALIGN_DOWN() macro to reduce code and to make it more human readable. Suggested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <b84eb324d2ebdcc6f9c442c97b5b4d01eecb4f43.1632758315.git.qemu_oss@crudebyte.com>
* 9pfs: deduplicate iounit codeChristian Schoenebeck2021-10-271-21/+20
| | | | | | | | | Remove redundant code that translates host fileystem's block size into 9p client (guest side) block size. Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Reviewed-by: Greg Kurz <groug@kaod.org> Message-Id: <129bb71d5119e61d335f1e3107e472e4beea223a.1632758315.git.qemu_oss@crudebyte.com>
* 9pfs: fix wrong I/O block size in RgetattrChristian Schoenebeck2021-10-271-1/+20
| | | | | | | | | | | | | | | | | | | | When client sent a 9p Tgetattr request then the wrong I/O block size value was returned by 9p server; instead of host file system's I/O block size it should rather return an I/O block size according to 9p session's 'msize' value, because the value returned to client should be an "optimum" block size for I/O (i.e. to maximize performance), it should not reflect the actual physical block size of the underlying storage media. The I/O block size of a host filesystem is typically 4k, so the value returned was far too low for good 9p I/O performance. This patch adds stat_to_iounit() with a similar approach as the existing get_iounit() function. Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Reviewed-by: Greg Kurz <groug@kaod.org> Message-Id: <E1mT2Js-0000DW-OH@lizzy.crudebyte.com>
* Merge remote-tracking branch 'remotes/dagrh/tags/pull-virtiofs-20211026' ↵Richard Henderson2021-10-263-45/+58
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging Virtiofsd pull 2021-10-26 New 'unsupported' feature for xattr mapping Good for hiding selinux Plus some tidy ups and error handling. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> # gpg: Signature made Tue 26 Oct 2021 03:28:44 AM PDT # gpg: using RSA key 45F5C71B4A0CB7FB977A9FA90516331EBC5BFDE7 # gpg: Good signature from "Dr. David Alan Gilbert (RH2) <dgilbert@redhat.com>" [full] * remotes/dagrh/tags/pull-virtiofs-20211026: virtiofsd: Error on bad socket group name virtiofsd: Add a helper to stop all queues virtiofsd: Add a helper to send element on virtqueue virtiofsd: Remove unused virtio_fs_config definition virtiofsd: xattr mapping add a new type "unsupported" Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * virtiofsd: Error on bad socket group nameDr. David Alan Gilbert2021-10-251-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | Make the '--socket-group=' option fail if the group name is unknown: ./tools/virtiofsd/virtiofsd .... --socket-group=zaphod vhost socket: unable to find group 'zaphod' Reported-by: Xiaoling Gao <xiagao@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20211014122554.34599-1-dgilbert@redhat.com> Reviewed-by: Vivek Goyal <vgoyal@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
| * virtiofsd: Add a helper to stop all queuesVivek Goyal2021-10-251-9/+13
| | | | | | | | | | | | | | | | | | | | Use a helper to stop all the queues. Later in the patch series I am planning to use this helper at one more place later in the patch series. Signed-off-by: Vivek Goyal <vgoyal@redhat.com> Message-Id: <20210930153037.1194279-6-vgoyal@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
| * virtiofsd: Add a helper to send element on virtqueueVivek Goyal2021-10-251-27/+18
| | | | | | | | | | | | | | | | | | | | | | We have open coded logic to take locks and push element on virtqueue at three places. Add a helper and use it everywhere. Code is easier to read and less number of lines of code. Signed-off-by: Vivek Goyal <vgoyal@redhat.com> Message-Id: <20210930153037.1194279-5-vgoyal@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
| * virtiofsd: Remove unused virtio_fs_config definitionVivek Goyal2021-10-251-6/+0
| | | | | | | | | | | | | | | | | | | | "struct virtio_fs_config" definition seems to be unused in fuse_virtio.c. Remove it. Signed-off-by: Vivek Goyal <vgoyal@redhat.com> Message-Id: <20210930153037.1194279-4-vgoyal@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
| * virtiofsd: xattr mapping add a new type "unsupported"Vivek Goyal2021-10-252-3/+20
|/ | | | | | | | | | | | | | | | | | | | | | | | | | Right now for xattr remapping, we support types of "prefix", "ok" or "bad". Type "bad" returns -EPERM on setxattr and hides xattr in listxattr. For getxattr, mapping code returns -EPERM but getxattr code converts it to -ENODATA. I need a new semantics where if an xattr is unsupported, then getxattr()/setxattr() return -ENOTSUP and listxattr() should hide the xattr. This is needed to simulate that security.selinux is not supported by virtiofs filesystem and in that case client falls back to some default label specified by policy. So add a new type "unsupported" which returns -ENOTSUP on getxattr() and setxattr() and hides xattrs in listxattr(). For example, one can use following mapping rule to not support security.selinux xattr and allow others. "-o xattrmap=/unsupported/all/security.selinux/security.selinux//ok/all///" Suggested-by: "Dr. David Alan Gilbert" <dgilbert@redhat.com> Signed-off-by: Vivek Goyal <vgoyal@redhat.com> Message-Id: <YUt9qbmgAfCFfg5t@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
* Merge remote-tracking branch ↵Richard Henderson2021-10-2311-90/+87
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/vivier/tags/trivial-branch-for-6.2-pull-request' into staging Trivial patches pull request 20211023 # gpg: Signature made Sat 23 Oct 2021 11:30:42 AM PDT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] * remotes/vivier/tags/trivial-branch-for-6.2-pull-request: analyze-migration.py: fix extract contents ('-x') errors analyze-migration.py: fix a long standing typo README: Fix some documentation URLs hw/nvram: Fix Memory Leak in Xilinx ZynqMP eFuse device hw/nvram: Fix Memory Leak in Xilinx Versal eFuse device hw/nvram: Fix Memory Leak in Xilinx eFuse QOM softmmu/physmem.c: Fix typo in comment MAINTAINERS: Add myself as reviewer of 'Machine core' API disas/nios2: Simplify endianess conversion disas/nios2: Fix style in print_insn_nios2() po: update turkish translation Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * analyze-migration.py: fix extract contents ('-x') errorsLaurent Vivier2021-10-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When we try to use 'analyze-migration.py -x' with python3, we have the following errors: Traceback (most recent call last): File "scripts/analyze-migration.py", line 593, in <module> f.write(jsonenc.encode(dump.vmsd_desc)) TypeError: a bytes-like object is required, not 'str' Traceback (most recent call last): File "scripts/analyze-migration.py", line 601, in <module> f.write(jsonenc.encode(dict)) TypeError: a bytes-like object is required, not 'str' This happens because the file 'f' is open in binary mode while jsonenc.encode() returns a string. The results are human-readable files, 'desc.json' and 'state.json', so there is no reason to use the binary mode. Signed-off-by: Laurent Vivier <lvivier@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20211015131645.501281-3-lvivier@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * analyze-migration.py: fix a long standing typoLaurent Vivier2021-10-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | The parameters of '-d' can be either 'state' or 'desc', not 'dump' as it is reported in the error message. Fixes: b17425701d66 ("Add migration stream analyzation script") Signed-off-by: Laurent Vivier <lvivier@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20211015131645.501281-2-lvivier@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * README: Fix some documentation URLsGreg Kurz2021-10-231-7/+7
| | | | | | | | | | | | | | | | | | | | All of these pages live in the wiki, not in the main web site. Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Tested-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <163456470882.196333.17366490695504718038.stgit@bahia.huguette> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * hw/nvram: Fix Memory Leak in Xilinx ZynqMP eFuse deviceTong Ho2021-10-231-6/+12
| | | | | | | | | | | | | | | | | | Signed-off-by: Tong Ho <tong.ho@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211015203532.2463705-4-tong.ho@xilinx.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * hw/nvram: Fix Memory Leak in Xilinx Versal eFuse deviceTong Ho2021-10-231-5/+15
| | | | | | | | | | | | | | | | | | Signed-off-by: Tong Ho <tong.ho@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211015203532.2463705-3-tong.ho@xilinx.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * hw/nvram: Fix Memory Leak in Xilinx eFuse QOMTong Ho2021-10-231-3/+6
| | | | | | | | | | | | | | | | | | Signed-off-by: Tong Ho <tong.ho@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211015203532.2463705-2-tong.ho@xilinx.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * softmmu/physmem.c: Fix typo in commentGreg Kurz2021-10-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the comment to match what the code is doing, as explained in the changelog of commit 86cf9e154632cb28d749db0ea47946fba8cf3f09 that introduced the change: Commit 9458a9a1df1a4c719e24512394d548c1fc7abd22 added synchronization of vCPU and migration operations through calling run_on_cpu operation. However, in replay mode this synchronization is unneeded, because I/O and vCPU threads are already synchronized. This patch disables such synchronization for record/replay mode. Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <163429018454.1146856.3429437540871060739.stgit@bahia.huguette> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * MAINTAINERS: Add myself as reviewer of 'Machine core' APIPhilippe Mathieu-Daudé2021-10-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | In order to help Eduardo and Marcel with the machine core API, add myself as reviewer. That will also help me to learn more about this subsystem :) Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Message-Id: <20211007093108.323223-1-philmd@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * disas/nios2: Simplify endianess conversionPhilippe Mathieu-Daudé2021-10-223-26/+5
| | | | | | | | | | | | | | | | | | | | | | | | Since commit 12b6e9b27d4 ("disas: Clean up CPUDebug initialization") the disassemble_info->bfd_endian enum is set for all targets in target_disas(). We can directly call print_insn_nios2() and simplify. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210807110939.95853-3-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * disas/nios2: Fix style in print_insn_nios2()Philippe Mathieu-Daudé2021-10-221-28/+27
| | | | | | | | | | | | | | | | | | | | We are going to modify this function, fix its style first. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210807110939.95853-2-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| * po: update turkish translationOğuz Ersen2021-10-221-13/+12
| | | | | | | | | | | | | | | | Message-Id: <lDpmNUjNrVETJ2QoHoYmSoRvKoEIVFbF4IZAa1R5PVzqPCTh7nmV_ERHQlgYtNJN1Ppagtvelbo4uhSihEd5bSqIxCvGQchEWVpP-ofn2kw=@protonmail.com> Signed-off-by: Oğuz Ersen <oguzersen@protonmail.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> [lv,pb: s/K_opyala/_Kopyala/;s/Se_kmeleri/_Sekmeleri/] Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* | Merge remote-tracking branch ↵Richard Henderson2021-10-2228-779/+720
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/alistair23/tags/pull-riscv-to-apply-20211022-2' into staging Fourth RISC-V PR for QEMU 6.2 - Vector extension bug fixes - Bit manipulation extension bug fix - Support vhost-user and numa mem options on all boards - Rationalise XLEN and operand lengths - Bump the OpenTitan FPGA support - Remove the Ibex PLIC - General code cleanup # gpg: Signature made Fri 22 Oct 2021 06:36:10 AM PDT # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] * remotes/alistair23/tags/pull-riscv-to-apply-20211022-2: (33 commits) hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id hw/intc: sifive_plic: Cleanup the irq_request function hw/intc: sifive_plic: Cleanup the realize function hw/intc: sifive_plic: Move the properties hw/intc: Remove the Ibex PLIC hw/riscv: opentitan: Update to the latest build target/riscv: Compute mstatus.sd on demand target/riscv: Use riscv_csrrw_debug for cpu_dump target/riscv: Use gen_shift*_per_ol for RVB, RVI target/riscv: Use gen_unary_per_ol for RVB target/riscv: Adjust trans_rev8_32 for riscv64 target/riscv: Use gen_arith_per_ol for RVM target/riscv: Replace DisasContext.w with DisasContext.ol target/riscv: Replace is_32bit with get_xl/get_xlen target/riscv: Properly check SEW in amo_op ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * | hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_idBin Meng2021-10-221-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using memory_region_init_ram(), which can't possibly handle vhost-user, and can't work as expected with '-numa node,memdev' options. Use MachineState::ram instead of manually initializing RAM memory region, as well as by providing MachineClass::default_ram_id to opt in to memdev scheme. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20211020014112.7336-7-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_idBin Meng2021-10-221-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using memory_region_init_ram(), which can't possibly handle vhost-user, and can't work as expected with '-numa node,memdev' options. Use MachineState::ram instead of manually initializing RAM memory region, as well as by providing MachineClass::default_ram_id to opt in to memdev scheme. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20211020014112.7336-6-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_idBin Meng2021-10-221-4/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using memory_region_init_ram(), which can't possibly handle vhost-user, and can't work as expected with '-numa node,memdev' options. Use MachineState::ram instead of manually initializing RAM memory region, as well as by providing MachineClass::default_ram_id to opt in to memdev scheme. While at it add check for user supplied RAM size and error out if it mismatches board expected value. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 20211020014112.7336-5-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_idBin Meng2021-10-221-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using memory_region_init_ram(), which can't possibly handle vhost-user, and can't work as expected with '-numa node,memdev' options. Use MachineState::ram instead of manually initializing RAM memory region, as well as by providing MachineClass::default_ram_id to opt in to memdev scheme. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20211020014112.7336-4-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_idBin Meng2021-10-221-4/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using memory_region_init_ram(), which can't possibly handle vhost-user, and can't work as expected with '-numa node,memdev' options. Use MachineState::ram instead of manually initializing RAM memory region, as well as by providing MachineClass::default_ram_id to opt in to memdev scheme. While at it add check for user supplied RAM size and error out if it mismatches board expected value. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 20211020014112.7336-3-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | hw/riscv: microchip_pfsoc: Use MachineState::ram and ↵Bin Meng2021-10-221-16/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MachineClass::default_ram_id Using memory_region_init_ram(), which can't possibly handle vhost-user, and can't work as expected with '-numa node,memdev' options. Use MachineState::ram instead of manually initializing RAM memory region, as well as by providing MachineClass::default_ram_id to opt in to memdev scheme. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 20211020014112.7336-2-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | hw/intc: sifive_plic: Cleanup the irq_request functionAlistair Francis2021-10-221-6/+4
| | | | | | | | | | | | | | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 4200da222a65c89ed1ba35f754dcca7fdd9f08d6.1634524691.git.alistair.francis@wdc.com
| * | hw/intc: sifive_plic: Cleanup the realize functionAlistair Francis2021-10-221-21/+24
| | | | | | | | | | | | | | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: b94c098cb221e744683349b1ac794c23102ef471.1634524691.git.alistair.francis@wdc.com
| * | hw/intc: sifive_plic: Move the propertiesAlistair Francis2021-10-221-15/+15
| | | | | | | | | | | | | | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 3c125e27c49a4969df82bf8b197535ccd1996939.1634524691.git.alistair.francis@wdc.com
| * | hw/intc: Remove the Ibex PLICAlistair Francis2021-10-222-308/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | The Ibex PLIC is now spec compliant. Let's remove the Ibex PLIC and instead use the SiFive PLIC. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 5557935c2660c5e6281b6d21e6514e019593662e.1634524691.git.alistair.francis@wdc.com
| * | hw/riscv: opentitan: Update to the latest buildAlistair Francis2021-10-222-8/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | Update the OpenTitan machine model to match the latest OpenTitan FPGA design. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 18b1b681b0f8dd2461e819d1217bf0b530812680.1634524691.git.alistair.francis@wdc.com
| * | target/riscv: Compute mstatus.sd on demandRichard Henderson2021-10-223-20/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The position of this read-only field is dependent on the current xlen. Rather than having to compute that difference in many places, compute it only on read. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-16-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | target/riscv: Use riscv_csrrw_debug for cpu_dumpRichard Henderson2021-10-221-44/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the official debug read interface to the csrs, rather than referencing the env slots directly. Put the list of csrs to dump into a table. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-15-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | target/riscv: Use gen_shift*_per_ol for RVB, RVIRichard Henderson2021-10-223-52/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most shift instructions require a separate implementation for RV32 when TARGET_LONG_BITS == 64. Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-14-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | target/riscv: Use gen_unary_per_ol for RVBRichard Henderson2021-10-222-17/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The count zeros instructions require a separate implementation for RV32 when TARGET_LONG_BITS == 64. Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-13-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | target/riscv: Adjust trans_rev8_32 for riscv64Richard Henderson2021-10-221-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When target_long is 64-bit, we still want a 32-bit bswap for rev8. Since this opcode is specific to RV32, we need not conditionalize. Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-12-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | target/riscv: Use gen_arith_per_ol for RVMRichard Henderson2021-10-222-3/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The multiply high-part instructions require a separate implementation for RV32 when TARGET_LONG_BITS == 64. Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-11-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | target/riscv: Replace DisasContext.w with DisasContext.olRichard Henderson2021-10-224-43/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation for RV128, consider more than just "w" for operand size modification. This will be used for the "d" insns from RV128 as well. Rename oper_len to get_olen to better match get_xlen. Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-10-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | target/riscv: Replace is_32bit with get_xl/get_xlenRichard Henderson2021-10-221-14/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation for RV128, replace a simple predicate with a more versatile test. Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-9-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | target/riscv: Properly check SEW in amo_opRichard Henderson2021-10-221-12/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We're currently assuming SEW <= 3, and the "else" from the SEW == 3 must be less. Use a switch and explicitly bound both SEW and SEQ for all cases. Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-8-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | target/riscv: Use REQUIRE_64BIT in amo_check64Richard Henderson2021-10-221-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the same REQUIRE_64BIT check that we use elsewhere, rather than open-coding the use of is_32bit. Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-7-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | target/riscv: Add MXL/SXL/UXL to TB_FLAGSRichard Henderson2021-10-225-1/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Begin adding support for switching XLEN at runtime. Extract the effective XLEN from MISA and MSTATUS and store for use during translation. Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-6-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxlRichard Henderson2021-10-228-34/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Shortly, the set of supported XL will not be just 32 and 64, and representing that properly using the enumeration will be imperative. Two places, booting and gdb, intentionally use misa_mxl_max to emphasize the use of the reset value of misa.mxl, and not the current cpu state. Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-5-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | target/riscv: Split misa.mxl and misa.extRichard Henderson2021-10-228-69/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The hw representation of misa.mxl is at the high bits of the misa csr. Representing this in the same way inside QEMU results in overly complex code trying to check that field. Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-4-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>