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* hw/ssi: Rename SSI 'slave' as 'peripheral'Philippe Mathieu-Daudé2020-12-1014-117/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | In order to use inclusive terminology, rename SSI 'slave' as 'peripheral', following the specification resolution: https://www.oshwa.org/a-resolution-to-redefine-spi-signal-names/ Patch created mechanically using: $ sed -i s/SSISlave/SSIPeripheral/ $(git grep -l SSISlave) $ sed -i s/SSI_SLAVE/SSI_PERIPHERAL/ $(git grep -l SSI_SLAVE) $ sed -i s/ssi-slave/ssi-peripheral/ $(git grep -l ssi-slave) $ sed -i s/ssi_slave/ssi_peripheral/ $(git grep -l ssi_slave) $ sed -i s/ssi_create_slave/ssi_create_peripheral/ \ $(git grep -l ssi_create_slave) Then in VMStateDescription vmstate_ssi_peripheral we restored the "SSISlave" migration stream name (to avoid breaking migration). Finally the following files have been manually tweaked: - hw/ssi/pl022.c - hw/ssi/xilinx_spips.c Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201012124955.3409127-4-f4bug@amsat.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* hw/ssi: Update coding style to make checkpatch.pl happyPhilippe Mathieu-Daudé2020-12-101-7/+9
| | | | | | | | To make the next commit easier to review, clean this code first. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201012124955.3409127-3-f4bug@amsat.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* hw/ssi/aspeed_smc: Rename 'max_slaves' variable as 'max_peripherals'Philippe Mathieu-Daudé2020-12-102-27/+28
| | | | | | | | | | | | | | | | | | | In order to use inclusive terminology, rename max_slaves as max_peripherals. Patch generated using: $ sed -i s/slave/peripheral/ \ hw/ssi/aspeed_smc.c include/hw/ssi/aspeed_smc.h One line in aspeed_smc_read() has been manually tweaked to pass checkpatch. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20201012124955.3409127-2-f4bug@amsat.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* pci: Let pci_dma_write() propagate MemTxResultPhilippe Mathieu-Daudé2020-12-101-2/+14
| | | | | | | | | | | pci_dma_rw() returns a MemTxResult type. Do not discard it, return it to the caller. Reviewed-by: Li Qiang <liq3ea@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20201023151923.3243652-11-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* pci: Let pci_dma_read() propagate MemTxResultPhilippe Mathieu-Daudé2020-12-101-2/+14
| | | | | | | | | | | pci_dma_rw() returns a MemTxResult type. Do not discard it, return it to the caller. Reviewed-by: Li Qiang <liq3ea@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20201023151923.3243652-10-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* pci: Let pci_dma_rw() propagate MemTxResultPhilippe Mathieu-Daudé2020-12-101-2/+16
| | | | | | | | | | | dma_memory_rw() returns a MemTxResult type. Do not discard it, return it to the caller. Reviewed-by: Li Qiang <liq3ea@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20201023151923.3243652-9-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* dma: Let dma_memory_write() propagate MemTxResultPhilippe Mathieu-Daudé2020-12-101-4/+18
| | | | | | | | | | | | dma_memory_rw_relaxed() returns a MemTxResult type. Do not discard it, return it to the caller. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Li Qiang <liq3ea@gmail.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20201023151923.3243652-8-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* dma: Let dma_memory_read() propagate MemTxResultPhilippe Mathieu-Daudé2020-12-101-4/+17
| | | | | | | | | | | | dma_memory_rw_relaxed() returns a MemTxResult type. Do not discard it, return it to the caller. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Li Qiang <liq3ea@gmail.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20201023151923.3243652-7-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* dma: Let dma_memory_rw() propagate MemTxResultPhilippe Mathieu-Daudé2020-12-101-8/+22
| | | | | | | | | | | | address_space_rw() returns a MemTxResult type. Do not discard it, return it to the caller. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Li Qiang <liq3ea@gmail.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20201023151923.3243652-6-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* dma: Let dma_memory_set() propagate MemTxResultPhilippe Mathieu-Daudé2020-12-102-4/+18
| | | | | | | | | | | | address_space_write() returns a MemTxResult type. Do not discard it, return it to the caller. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Li Qiang <liq3ea@gmail.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20201023151923.3243652-5-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* dma: Document address_space_map/address_space_unmap() prototypesPhilippe Mathieu-Daudé2020-12-101-1/+28
| | | | | | | | | | Add documentation based on address_space_map / address_space_unmap. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20201023151923.3243652-4-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* qom: eliminate identical functionsPaolo Bonzini2020-12-101-29/+7
| | | | | | | Most property release functions in qom/object.c only free the opaque value. Combine all of them into a single function. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* docs/devel/loads-stores: Add regexp for DMA functionsPhilippe Mathieu-Daudé2020-12-101-0/+2
| | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20201023151923.3243652-3-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* WHPX: support for the kernel-irqchip on/offSunil Muthuswamy2020-12-1010-40/+578
| | | | | | | | | | | | | This patch adds support the kernel-irqchip option for WHPX with on or off value. 'split' value is not supported for the option. The option only works for the latest version of Windows (ones that are coming out on Insiders). The change maintains backward compatibility on older version of Windows where this option is not supported. Signed-off-by: Sunil Muthuswamy <sunilmut@microsoft.com> Message-Id: <SN4PR2101MB0880B13258DA9251F8459F4DC0170@SN4PR2101MB0880.namprd21.prod.outlook.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target/i386: seg_helper: Correct segment selector nullification in the ↵Bin Meng2020-12-101-1/+4
| | | | | | | | | | | | | | | | | RET/IRET helper Per the SDM, when returning to outer privilege level, for segment registers (ES, FS, GS, and DS) if the check fails, the segment selector becomes null, but QEMU clears the base/limit/flags as well as nullifying the segment selector, which should be a spec violation. Real hardware seems to be compliant with the spec, at least on one Coffee Lake board I tested. Signed-off-by: Bin Meng <bin.meng@windriver.com> Message-Id: <1605261378-77971-1-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target/i386: Support up to 32768 CPUs without IRQ remappingDavid Woodhouse2020-12-106-30/+78
| | | | | | | | | | | | | | | | | | | | The IOAPIC has an 'Extended Destination ID' field in its RTE, which maps to bits 11-4 of the MSI address. Since those address bits fall within a given 4KiB page they were historically non-trivial to use on real hardware. The Intel IOMMU uses the lowest bit to indicate a remappable format MSI, and then the remaining 7 bits are part of the index. Where the remappable format bit isn't set, we can actually use the other seven to allow external (IOAPIC and MSI) interrupts to reach up to 32768 CPUs instead of just the 255 permitted on bare metal. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Message-Id: <78097f9218300e63e751e077a0a5ca029b56ba46.camel@infradead.org> [Fix UBSAN warning. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: David Woodhouse <dwmw2@infradead.org>
* target/i386: fix operand order for PDEP and PEXTPaolo Bonzini2020-12-103-4/+49
| | | | | | | | | | | | | | For PDEP and PEXT, the mask is provided in the memory (mod+r/m) operand, and therefore is loaded in s->T0 by gen_ldst_modrm. The source is provided in the second source operand (VEX.vvvv) and therefore is loaded in s->T1. Fix the order in which they are passed to the helpers. Reported-by: Lenard Szolnoki <blog@lenardszolnoki.com> Analyzed-by: Lenard Szolnoki <blog@lenardszolnoki.com> Fixes: https://bugs.launchpad.net/qemu/+bug/1605123 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20201210' ↵Peter Maydell2020-12-1010-8/+542
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging Aspeed patches : * New device model for EMC1413/EMC1414 temperature sensors (I2C) * New g220a-bmc Aspeed machine * couple of Aspeed cleanups # gpg: Signature made Thu 10 Dec 2020 11:58:10 GMT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * remotes/legoater/tags/pull-aspeed-20201210: aspeed: g220a-bmc: Add an FRU aspeed/smc: Add support for address lane disablement ast2600: SRAM is 89KB aspeed: Add support for the g220a-bmc board hw/misc: add an EMC141{3,4} device model Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * aspeed: g220a-bmc: Add an FRUJohn Wang2020-12-101-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add an eeprom device and fill it with fru information $ ipmitool fru print 0 Product Manufacturer : Bytedance Product Name : G220A Signed-off-by: John Wang <wangzhiqiang.bj@bytedance.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20201210103607.556-1-wangzhiqiang.bj@bytedance.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * aspeed/smc: Add support for address lane disablementCédric Le Goater2020-12-101-7/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The controller can be configured to disable or enable address and data byte lanes when issuing commands. This is useful in read command mode to send SPI NOR commands that don't have an address space, such as RDID. It's a good way to have a unified read operation for registers and flash contents accesses. A new SPI driver proposed by Aspeed makes use of this feature. Add support for address lanes to start with. We will do the same for the data lanes if they are controlled one day. Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-Id: <20201120161547.740806-2-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * ast2600: SRAM is 89KBJoel Stanley2020-12-101-1/+1
| | | | | | | | | | | | | | | | | | | | On the AST2600A1, the SRAM size was increased to 89KB. Fixes: 7582591ae745 ("aspeed: Support AST2600A1 silicon revision") Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20201112012113.835858-1-joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * aspeed: Add support for the g220a-bmc boardJohn Wang2020-12-101-0/+60
| | | | | | | | | | | | | | | | | | | | | | G220A is a 2 socket x86 motherboard supported by OpenBMC. Strapping configuration was obtained from hardware. Signed-off-by: John Wang <wangzhiqiang.bj@bytedance.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-Id: <20201122105134.671-2-wangzhiqiang.bj@bytedance.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * hw/misc: add an EMC141{3,4} device modelJohn Wang2020-12-107-0/+451
| | | | | | | | | | | | | | | | | | | | | | | | | | Largely inspired by the TMP421 temperature sensor, here is a model for the EMC1413/EMC1414 temperature sensors. Specs can be found here : http://ww1.microchip.com/downloads/en/DeviceDoc/20005274A.pdf Signed-off-by: John Wang <wangzhiqiang.bj@bytedance.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20201122105134.671-1-wangzhiqiang.bj@bytedance.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* | Merge remote-tracking branch ↵Peter Maydell2020-12-1010-32/+128
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/kraxel/tags/microvm-20201210-pull-request' into staging microvm: add support for second ioapic # gpg: Signature made Thu 10 Dec 2020 12:13:42 GMT # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/microvm-20201210-pull-request: tests/acpi: disallow updates for expected data files tests/acpi: update expected data files tests/acpi: add ioapic2=on test for microvm tests/acpi: add data files for ioapic2 test variant tests/acpi: allow updates for expected data files microvm: add second ioapic microvm: drop microvm_gsi_handler() microvm: make pcie irq base runtime changeable microvm: make number of virtio transports runtime changeable x86: add support for second ioapic x86: rewrite gsi_handler() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | tests/acpi: disallow updates for expected data filesGerd Hoffmann2020-12-101-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Sergio Lopez <slp@redhat.com> Message-id: 20201203105423.10431-13-kraxel@redhat.com
| * | tests/acpi: update expected data filesGerd Hoffmann2020-12-102-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Sergio Lopez <slp@redhat.com> Message-id: 20201203105423.10431-12-kraxel@redhat.com
| * | tests/acpi: add ioapic2=on test for microvmGerd Hoffmann2020-12-101-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | APIC table changes: [034h 0052 1] Subtable Type : 01 [I/O APIC] [035h 0053 1] Length : 0C [036h 0054 1] I/O Apic ID : 00 [037h 0055 1] Reserved : 00 [038h 0056 4] Address : FEC00000 [03Ch 0060 4] Interrupt : 00000000 +[040h 0064 1] Subtable Type : 01 [I/O APIC] +[041h 0065 1] Length : 0C +[042h 0066 1] I/O Apic ID : 01 +[043h 0067 1] Reserved : 00 +[044h 0068 4] Address : FEC10000 +[048h 0072 4] Interrupt : 00000018 DSDT table changes: - Device (VR07) + Device (VR23) { Name (_HID, "LNRO0005") // _HID: Hardware ID - Name (_UID, 0x07) // _UID: Unique ID + Name (_UID, 0x17) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { Memory32Fixed (ReadWrite, - 0xFEB00E00, // Address Base + 0xFEB02E00, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) { - 0x00000017, + 0x0000002F, } }) } } Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Sergio Lopez <slp@redhat.com> Message-id: 20201203105423.10431-11-kraxel@redhat.com
| * | tests/acpi: add data files for ioapic2 test variantGerd Hoffmann2020-12-102-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Copy microvm/APIC -> microvm/APIC.ioapic2 Copy microvm/DSDT -> microvm/DSDT.ioapic2 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Sergio Lopez <slp@redhat.com> Message-id: 20201203105423.10431-10-kraxel@redhat.com
| * | tests/acpi: allow updates for expected data filesGerd Hoffmann2020-12-101-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Sergio Lopez <slp@redhat.com> Message-id: 20201203105423.10431-9-kraxel@redhat.com
| * | microvm: add second ioapicGerd Hoffmann2020-12-103-9/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create second ioapic, route virtio-mmio IRQs to it, allow more virtio-mmio devices (24 instead of 8). Needs ACPI, enabled by default, can be turned off using -machine ioapic2=off Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Sergio Lopez <slp@redhat.com> Message-id: 20201203105423.10431-8-kraxel@redhat.com
| * | microvm: drop microvm_gsi_handler()Gerd Hoffmann2020-12-101-13/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the improved gsi_handler() we don't need our private version any more. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Sergio Lopez <slp@redhat.com> Message-id: 20201203105423.10431-7-kraxel@redhat.com
| * | microvm: make pcie irq base runtime changeableGerd Hoffmann2020-12-102-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allows to move them in case we have enough irq lines available. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Sergio Lopez <slp@redhat.com> Message-id: 20201203105423.10431-6-kraxel@redhat.com
| * | microvm: make number of virtio transports runtime changeableGerd Hoffmann2020-12-102-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This will allow to increase the number of transports in case we have enough irq lines available for them all. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Sergio Lopez <slp@redhat.com> Message-id: 20201203105423.10431-5-kraxel@redhat.com
| * | x86: add support for second ioapicGerd Hoffmann2020-12-105-1/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add ioapic_init_secondary to initialize it, wire up in gsi handling and acpi apic table creation. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Sergio Lopez <slp@redhat.com> Message-id: 20201203105423.10431-4-kraxel@redhat.com
| * | x86: rewrite gsi_handler()Gerd Hoffmann2020-12-101-4/+10
| |/ | | | | | | | | | | | | | | | | | | | | Rewrite function to use switch() for IRQ number mapping. Check i8259_irq exists before raising it so the function also works in case no i8259 (aka pic) is present. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 20201203105423.10431-3-kraxel@redhat.com
* | Merge remote-tracking branch ↵Peter Maydell2020-12-1034-150/+2710
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/pmaydell/tags/pull-target-arm-20201210' into staging target-arm queue: * hw/arm/smmuv3: Fix up L1STD_SPAN decoding * xlnx-zynqmp: Support Xilinx ZynqMP CAN controllers * sbsa-ref: allow to use Cortex-A53/57/72 cpus * Various minor code cleanups * hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault * Implement more pieces of ARMv8.1M support # gpg: Signature made Thu 10 Dec 2020 11:46:43 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20201210: (36 commits) hw/arm/armv7m: Correct typo in QOM object name hw/intc/armv7m_nvic: Implement read/write for RAS register block target/arm: Implement M-profile "minimal RAS implementation" hw/intc/armv7m_nvic: Fix "return from inactive handler" check target/arm: Implement CCR_S.TRD behaviour for SG insns hw/intc/armv7m_nvic: Support v8.1M CCR.TRD bit target/arm: Implement new v8.1M VLLDM and VLSTM encodings target/arm: Implement new v8.1M NOCP check for exception return target/arm: Implement v8.1M REVIDR register target/arm: In v8.1M, don't set HFSR.FORCED on vector table fetch failures target/arm: For v8.1M, always clear R0-R3, R12, APSR, EPSR on exception entry hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1M target/arm: Implement FPCXT_S fp system register target/arm: Factor out preserve-fp-state from full_vfp_access_check() target/arm: Use new FPCR_NZCV_MASK constant target/arm: Implement M-profile FPSCR_nzcvqc target/arm: Implement VLDR/VSTR system register target/arm: Move general-use constant expanders up in translate.c target/arm: Refactor M-profile VMSR/VMRS handling target/arm: Enforce M-profile VMRS/VMSR register restrictions ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/armv7m: Correct typo in QOM object namePeter Maydell2020-12-101-1/+1
| | | | | | | | | | | | | | | | | | Correct a typo in the name we give the NVIC object. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201119215617.29887-28-peter.maydell@linaro.org
| * hw/intc/armv7m_nvic: Implement read/write for RAS register blockPeter Maydell2020-12-102-0/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RAS feature has a block of memory-mapped registers at offset 0x5000 within the PPB. For a "minimal RAS" implementation we provide no error records and so the only registers that exist in the block are ERRIIDR and ERRDEVID. The "RAZ/WI for privileged, BusFault for nonprivileged" behaviour of the "nvic-default" region is actually valid for minimal-RAS, so the main benefit of providing an explicit implementation of the register block is more accurate LOG_UNIMP messages, and a framework for where we could add a real RAS implementation later if necessary. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201119215617.29887-27-peter.maydell@linaro.org
| * target/arm: Implement M-profile "minimal RAS implementation"Peter Maydell2020-12-103-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For v8.1M the architecture mandates that CPUs must provide at least the "minimal RAS implementation" from the Reliability, Availability and Serviceability extension. This consists of: * an ESB instruction which is a NOP -- since it is in the HINT space we need only add a comment * an RFSR register which will RAZ/WI * a RAZ/WI AIRCR.IESB bit -- the code which handles writes to AIRCR does not allow setting of RES0 bits, so we already treat this as RAZ/WI; add a comment noting that this is deliberate * minimal implementation of the RAS register block at 0xe0005000 -- this will be in a subsequent commit * setting the ID_PFR0.RAS field to 0b0010 -- we will do this when we add the Cortex-M55 CPU model Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201119215617.29887-26-peter.maydell@linaro.org
| * hw/intc/armv7m_nvic: Fix "return from inactive handler" checkPeter Maydell2020-12-101-27/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In commit 077d7449100d824a4 we added code to handle the v8M requirement that returns from NMI or HardFault forcibly deactivate those exceptions regardless of what interrupt the guest is trying to deactivate. Unfortunately this broke the handling of the "illegal exception return because the returning exception number is not active" check for those cases. In the pseudocode this test is done on the exception the guest asks to return from, but because our implementation was doing this in armv7m_nvic_complete_irq() after the new "deactivate NMI/HardFault regardless" code we ended up doing the test on the VecInfo for that exception instead, which usually meant failing to raise the illegal exception return fault. In the case for "configurable exception targeting the opposite security state" we detected the illegal-return case but went ahead and deactivated the VecInfo anyway, which is wrong because that is the VecInfo for the other security state. Rearrange the code so that we first identify the illegal return cases, then see if we really need to deactivate NMI or HardFault instead, and finally do the deactivation. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201119215617.29887-25-peter.maydell@linaro.org
| * target/arm: Implement CCR_S.TRD behaviour for SG insnsPeter Maydell2020-12-101-0/+86
| | | | | | | | | | | | | | | | | | | | v8.1M introduces a new TRD flag in the CCR register, which enables checking for stack frame integrity signatures on SG instructions. Add the code in the SG insn implementation for the new behaviour. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201119215617.29887-24-peter.maydell@linaro.org
| * hw/intc/armv7m_nvic: Support v8.1M CCR.TRD bitPeter Maydell2020-12-102-8/+20
| | | | | | | | | | | | | | | | | | | | | | v8.1M introduces a new TRD flag in the CCR register, which enables checking for stack frame integrity signatures on SG instructions. This bit is not banked, and is always RAZ/WI to Non-secure code. Adjust the code for handling CCR reads and writes to handle this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201119215617.29887-23-peter.maydell@linaro.org
| * target/arm: Implement new v8.1M VLLDM and VLSTM encodingsPeter Maydell2020-12-102-1/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v8.1M adds new encodings of VLLDM and VLSTM (where bit 7 is set). The only difference is that: * the old T1 encodings UNDEF if the implementation implements 32 Dregs (this is currently architecturally impossible for M-profile) * the new T2 encodings have the implementation-defined option to read from memory (discarding the data) or write UNKNOWN values to memory for the stack slots that would be D16-D31 We choose not to make those accesses, so for us the two instructions behave identically assuming they don't UNDEF. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201119215617.29887-21-peter.maydell@linaro.org
| * target/arm: Implement new v8.1M NOCP check for exception returnPeter Maydell2020-12-101-1/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In v8.1M a new exception return check is added which may cause a NOCP UsageFault (see rule R_XLTP): before we clear s0..s15 and the FPSCR we must check whether access to CP10 from the Security state of the returning exception is disabled; if it is then we must take a fault. (Note that for our implementation CPPWR is always RAZ/WI and so can never cause CP10 accesses to fail.) The other v8.1M change to this register-clearing code is that if MVE is implemented VPR must also be cleared, so add a TODO comment to that effect. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201119215617.29887-20-peter.maydell@linaro.org
| * target/arm: Implement v8.1M REVIDR registerPeter Maydell2020-12-101-0/+5
| | | | | | | | | | | | | | | | | | | | In v8.1M a REVIDR register is defined, which is at address 0xe00ecfc and is a read-only IMPDEF register providing implementation specific minor revision information, like the v8A REVIDR_EL1. Implement this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201119215617.29887-19-peter.maydell@linaro.org
| * target/arm: In v8.1M, don't set HFSR.FORCED on vector table fetch failuresPeter Maydell2020-12-101-1/+5
| | | | | | | | | | | | | | | | | | | | In v8.1M, vector table fetch failures don't set HFSR.FORCED (see rule R_LLRP). (In previous versions of the architecture this was either required or IMPDEF.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201119215617.29887-18-peter.maydell@linaro.org
| * target/arm: For v8.1M, always clear R0-R3, R12, APSR, EPSR on exception entryPeter Maydell2020-12-101-4/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In v8.0M, on exception entry the registers R0-R3, R12, APSR and EPSR are zeroed for an exception taken to Non-secure state; for an exception taken to Secure state they become UNKNOWN, and we chose to leave them at their previous values. In v8.1M the behaviour is specified more tightly and these registers are always zeroed regardless of the security state that the exception targets (see rule R_KPZV). Implement this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201119215617.29887-17-peter.maydell@linaro.org
| * hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1MPeter Maydell2020-12-103-1/+16
| | | | | | | | | | | | | | | | | | | | | | The FPDSCR register has a similar layout to the FPSCR. In v8.1M it gains new fields FZ16 (if half-precision floating point is supported) and LTPSIZE (always reads as 4). Update the reset value and the code that handles writes to this register accordingly. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201119215617.29887-16-peter.maydell@linaro.org
| * target/arm: Implement FPCXT_S fp system registerPeter Maydell2020-12-101-0/+58
| | | | | | | | | | | | | | | | | | | | | | Implement the new-in-v8.1M FPCXT_S floating point system register. This is for saving and restoring the secure floating point context, and it reads and writes bits [27:0] from the FPSCR and the CONTROL.SFPA bit in bit [31]. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201119215617.29887-14-peter.maydell@linaro.org
| * target/arm: Factor out preserve-fp-state from full_vfp_access_check()Peter Maydell2020-12-101-18/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Factor out the code which handles M-profile lazy FP state preservation from full_vfp_access_check(); accesses to the FPCXT_NS register are a special case which need to do just this part (corresponding in the pseudocode to the PreserveFPState() function), and not the full set of actions matching the pseudocode ExecuteFPCheck() which normal FP instructions need to do. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201119215617.29887-13-peter.maydell@linaro.org