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* rust: qemu_api_macros: add Wrapper derive macroPaolo Bonzini2025-03-064-9/+141
| | | | | | | | | | Add a derive macro that makes it easy to peel off all the layers of specialness (UnsafeCell, MaybeUninit, etc.) and just get a pointer to the wrapped type; and likewise add them back starting from a *mut. Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* rust: cell: add wrapper for FFI typesPaolo Bonzini2025-03-062-16/+224
| | | | | | | | | | | Inspired by the same-named type in Linux. This type provides the compiler with a correct view of what goes on with FFI types. In addition, it separates the glue code from the bindgen-generated code, allowing traits such as Send, Sync or Zeroable to be specified independently for C and Rust structs. Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* scripts: dump stdin on meson-buildoptions errorNabih Estefan2025-03-061-2/+8
| | | | | | | | | | Dump sys.stdin when it errors on meson-buildoptions.py, letting us debug the build errors instead of just saying "Couldn't parse" Signed-off-by: Nabih Estefan <nabihestefan@google.com> Signed-off-by: Patrick Venture <venture@google.com> Link: https://lore.kernel.org/r/20250227180454.2006757-1-venture@google.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* chardev: express dependency on io/Paolo Bonzini2025-03-061-1/+1
| | | | | | | | | chardev is using qio functions, so express that in the Meson internal dependency. (I found this when adding character devices bindings for Rust; they initially needed the io dependency added by hand). Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* Merge tag 'ui-pull-request' of https://gitlab.com/marcandre.lureau/qemu into ↵Stefan Hajnoczi2025-03-052-15/+149
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging UI-related for 10.0 # -----BEGIN PGP SIGNATURE----- # # iQJQBAABCAA6FiEEh6m9kz+HxgbSdvYt2ujhCXWWnOUFAmfH8VIcHG1hcmNhbmRy # ZS5sdXJlYXVAcmVkaGF0LmNvbQAKCRDa6OEJdZac5fpaD/41MyK8mvNINCBh/zNs # BttToR+P2OKDdJcg+fiq8nSaBOqk8TnxWNdfKhd8bdPY3yD56zGzgYhZVLm+d0a6 # a54jkSYLxpM7LL9nKFjLSXDqhmrreU94YGIADzG5WPhndBBHg7ZtHoS5fhlCt4dq # 0YiPMdQqYf75lSk0w/q+KG+MNX/kA/2Yq2vmxMSRT+DniW7PfcO5MixYfaAs5zJz # JazcCZTDgbv/DrIsNeaEyMraE3GBnY1fU2obbwoQ2D+eFGA4SpUwjHKZnVkKuD0I # jYV53BQ+dQMGpN0kmQEyQOj25HvUR5WWlsvSYqHaWupUmg3P+Ne+RaGBUmymgwAU # FI8SVo9njl/4N8uaSDN76Ed6hpQh+LnnuR0pSDdxLLTef7JwC07009a1tYNeo3gq # xzTT0NlD8g8oTA/p/2HVAE2nKQME9qK3v3gqfVwZGlPnOBnL2S8+9qO5qK3xHUd0 # g3YwbaKl5aRDs2t2gzrUVEk6VO9TdpllzkskF26YuDmGgPHIU8y0P2TafPgtJ1cI # emlT06PiNwbJrpOLlLf8SaFXKWgDigt4mTUHg5ZNEDVOfs59qxcTPS1HdSKmA1nP # x5Zhq4AUFGAxJxziUznFvCYuqwiPqVkiqvrZF2PIAgkBCb0P8JtDbk+6DtTrrP+m # y2ODr8nH3Oo3hgDk7SOh577NKQ== # =KDTR # -----END PGP SIGNATURE----- # gpg: Signature made Wed 05 Mar 2025 14:38:10 HKT # gpg: using RSA key 87A9BD933F87C606D276F62DDAE8E10975969CE5 # gpg: issuer "marcandre.lureau@redhat.com" # gpg: Good signature from "Marc-André Lureau <marcandre.lureau@redhat.com>" [full] # gpg: aka "Marc-André Lureau <marcandre.lureau@gmail.com>" [full] # Primary key fingerprint: 87A9 BD93 3F87 C606 D276 F62D DAE8 E109 7596 9CE5 * tag 'ui-pull-request' of https://gitlab.com/marcandre.lureau/qemu: chardev: use remoteAddr if the chardev is client ui/console-vc: implement DCH (delete) and ICH (insert) commands ui/console-vc: add support for cursor DECSC and DECRC commands ui/console-vc: report cursor position in the screen not in the scroll buffer ui/console-vc: report to the application instead of screen rendering ui/console-vc: introduce parsing of the 'ESC ( <ch>' sequence Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * chardev: use remoteAddr if the chardev is clientHaoqian He2025-03-051-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | If the chardev is client, the socket file path in localAddr may be NULL. This is because the socket path comes from getsockname(), according to man page, getsockname() returns the current address bound by the socket sockfd. If the chardev is client, it's socket is unbound sockfd. Therefore, when computing the client chardev socket file path, using remoteAddr is more appropriate. Signed-off-by: Haoqian He <haoqian.he@smartx.com> Acked-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-ID: <20250225104526.2924175-1-haoqian.he@smartx.com>
| * ui/console-vc: implement DCH (delete) and ICH (insert) commandsRoman Penyaev2025-03-051-0/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements DCH (delete character) and ICH (insert character) commands. DCH - Delete Character: "As characters are deleted, the remaining characters between the cursor and right margin move to the left. Character attributes move with the characters. The terminal adds blank spaces with no visual character attributes at the right margin. DCH has no effect outside the scrolling margins" [1]. ICH - Insert Character: "The ICH sequence inserts Pn blank characters with the normal character attribute. The cursor remains at the beginning of the blank characters. Text between the cursor and right margin moves to the right. Characters scrolled past the right margin are lost. ICH has no effect outside the scrolling margins" [2]. Without these commands console is barely usable. [1] https://vt100.net/docs/vt510-rm/DCH.html [1] https://vt100.net/docs/vt510-rm/ICH.html Signed-off-by: Roman Penyaev <r.peniaev@gmail.com> Cc: "Marc-André Lureau" <marcandre.lureau@redhat.com> Cc: qemu-devel@nongnu.org Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-ID: <20250226075913.353676-6-r.peniaev@gmail.com>
| * ui/console-vc: add support for cursor DECSC and DECRC commandsRoman Penyaev2025-03-051-6/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are aliases for save and restore cursor commands: * save cursor `ESC 7` (DEC Save Cursor [1], older VT100) `ESC [ s` (CSI Save Cursor, standard ANSI) * load cursor `ESC 8` (DEC Restore Cursor [2], older VT100) `ESC [ u` (CSI Restore Cursor, standard ANSI) This change introduces older DEC sequencies for compatibility with some scripts (for example [3]) and tools. This change also adds saving and restoring of character attributes, which is according to the VT spec [1][2] [1] https://vt100.net/docs/vt510-rm/DECSC.html [2] https://vt100.net/docs/vt510-rm/DECRC.html [3] https://wiki.archlinux.org/title/Working_with_the_serial_console#Resizing_a_terminal Signed-off-by: Roman Penyaev <r.peniaev@gmail.com> Cc: "Marc-André Lureau" <marcandre.lureau@redhat.com> Cc: qemu-devel@nongnu.org Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-ID: <20250226075913.353676-5-r.peniaev@gmail.com>
| * ui/console-vc: report cursor position in the screen not in the scroll bufferRoman Penyaev2025-03-051-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The format of the CSI cursor position report is `ESC[row;columnR`, where `row` is a row of a cursor in the screen, not in the scrollback buffer. What's the difference? Let's say the terminal screen has 24 lines, no matter how long the scrollback buffer may be, the last line is the 24th. For example the following command can be executed in xterm on the last screen line: $ echo -en '\e[6n'; IFS='[;' read -sdR _ row col; echo $row:$col 24:1 It shows the cursor position on the current screen and not relative to the backscroll buffer. Before this change the row number was always increasing for the QEMU VC and represents the cursor position relative to the backscroll buffer. Signed-off-by: Roman Penyaev <r.peniaev@gmail.com> Cc: "Marc-André Lureau" <marcandre.lureau@redhat.com> Cc: qemu-devel@nongnu.org Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-ID: <20250226075913.353676-4-r.peniaev@gmail.com>
| * ui/console-vc: report to the application instead of screen renderingRoman Penyaev2025-03-051-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Terminal Device Status Report (DSR) [1] should be sent to an application, not rendered to the screen. This patch fixes rendering of terminal report, which appear only on the graphical screen of the terminal (console "vc") and can be reproduced by the following command: echo -en '\e[6n'; IFS='[;' read -sdR _ row col; echo $row:$col Command requests cursor position and waits for terminal response, but instead, the response is rendered to the graphical screen and never sent to an application. Why bother? Busybox shell (ash) in Alpine distribution requests cursor position on each shell prompt (once <ENTER> is pressed), which makes a prompt on a graphical screen corrupted with repeating Cursor Position Report (CPR) [2]: [root@alpine ~]# \033[57;1R] Which is very annoying and incorrect. [1] https://vt100.net/docs/vt100-ug/chapter3.html#DSR [2] https://vt100.net/docs/vt100-ug/chapter3.html#CPR Signed-off-by: Roman Penyaev <r.peniaev@gmail.com> Cc: "Marc-André Lureau" <marcandre.lureau@redhat.com> Cc: qemu-devel@nongnu.org Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-ID: <20250226075913.353676-3-r.peniaev@gmail.com>
| * ui/console-vc: introduce parsing of the 'ESC ( <ch>' sequenceRoman Penyaev2025-03-051-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change introduces parsing of the 'ESC ( <ch>' sequence, which is supposed to change character set [1]. In the QEMU case, the introduced parsing logic does not actually change the character set, but simply parses the sequence and does not let output of a tool to be corrupted with leftovers: `top` sends 'ESC ( B', so if character sequence is not parsed correctly, chracter 'B' appears in the output: Btop - 11:08:42 up 5 min, 1 user, load average: 0BB Tasks:B 158 Btotal,B 1 Brunning,B 157 Bsleeping,B 0 BsBB %Cpu(s):B 0.0 Bus,B 0.0 Bsy,B 0.0 Bni,B 99.8 Bid,B 0.2 BB MiB Mem :B 7955.6 Btotal,B 7778.6 Bfree,B 79.6 BB MiB Swap:B 0.0 Btotal,B 0.0 Bfree,B 0.0 BB PID USER PR NI VIRT RES SHR S B B 735 root 20 0 9328 3540 3152 R B B 1 root 20 0 20084 10904 8404 S B B 2 root 20 0 0 0 0 S B [1] https://vt100.net/docs/vt100-ug/chapter3.html#SCS Signed-off-by: Roman Penyaev <r.peniaev@gmail.com> Cc: "Marc-André Lureau" <marcandre.lureau@redhat.com> Cc: qemu-devel@nongnu.org Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-ID: <20250226075913.353676-2-r.peniaev@gmail.com>
* | Merge tag 'pull-loongarch-20250305' of https://gitlab.com/bibo-mao/qemu into ↵Stefan Hajnoczi2025-03-059-44/+493
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging loongarch queue # -----BEGIN PGP SIGNATURE----- # # iHUEABYKAB0WIQQNhkKjomWfgLCz0aQfewwSUazn0QUCZ8ezJgAKCRAfewwSUazn # 0T9pAQCKb+C69kbf9cEVg7PU/z5I0ALFtCNWCKxSkWZPDPik4gEA3IYwdrJ+csuX # 8nWL0fzyk+8+LDzEwEgCYoNcMnttRQw= # =P8mi # -----END PGP SIGNATURE----- # gpg: Signature made Wed 05 Mar 2025 10:12:54 HKT # gpg: using EDDSA key 0D8642A3A2659F80B0B3D1A41F7B0C1251ACE7D1 # gpg: Good signature from "bibo mao <maobibo@loongson.cn>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 7044 3A00 19C0 E97A 31C7 13C4 8E86 8FB7 A176 9D4C # Subkey fingerprint: 0D86 42A3 A265 9F80 B0B3 D1A4 1F7B 0C12 51AC E7D1 * tag 'pull-loongarch-20250305' of https://gitlab.com/bibo-mao/qemu: target/loongarch: Adjust the cpu reset action to a proper position hw/loongarch/virt: Enable cpu hotplug feature on virt machine hw/loongarch/virt: Update the ACPI table for hotplug cpu hw/loongarch/virt: Implement cpu plug interface hw/loongarch/virt: Implement cpu unplug interface hw/loongarch/virt: Add basic cpu plug interface framework hw/loongarch/virt: Add topo properties on CPU object hw/loongarch/virt: Add CPU topology support hw/intc/loongarch_extioi: Use cpu plug notification hw/intc/loongarch_extioi: Implment cpu hotplug interface hw/intc/loongarch_extioi: Add basic hotplug framework hw/intc/loongarch_extioi: Move gpio irq initial to common code hw/intc/loongarch_ipi: Notify ipi object when cpu is plugged hw/intc/loongarch_ipi: Implment cpu hotplug interface hw/intc/loongarch_ipi: Add basic hotplug framework Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * | target/loongarch: Adjust the cpu reset action to a proper positionXianglai Li2025-03-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit 5a99a10da6cf ("target/loongarch: fix vcpu reset command word issue") fixes the error in the cpu reset ioctl command word delivery process, so that the command word can be delivered correctly, and adds the judgment and processing of the error return value, which exposes another problem that under loongarch, the cpu reset action is earlier than the creation of vcpu. An error occurs when the cpu reset command is sent. Now adjust the order of cpu reset and vcpu create actions to fix this problem Signed-off-by: Xianglai Li <lixianglai@loongson.cn> Acked-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
| * | hw/loongarch/virt: Enable cpu hotplug feature on virt machineBibo Mao2025-03-051-2/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On virt machine, enable CPU hotplug feature has_hotpluggable_cpus. For hot-added CPUs, there is socket-id/core-id/thread-id property set, arch_id can be caculated from these properties. So that cpu slot can be searched from its arch_id. Co-developed-by: Xianglai Li <lixianglai@loongson.cn> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
| * | hw/loongarch/virt: Update the ACPI table for hotplug cpuBibo Mao2025-03-054-3/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | On LoongArch virt machine, ACPI GED hardware is used for CPU hotplug handler, here CPU hotplug support feature is added based on GED handler, also CPU scan and reject method is added about CPU device in DSDT table. Co-developed-by: Xianglai Li <lixianglai@loongson.cn> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
| * | hw/loongarch/virt: Implement cpu plug interfaceBibo Mao2025-03-052-11/+78
| | | | | | | | | | | | | | | | | | | | | | | | Implement cpu plug interface, and cold-plug cpu uses plug interface when cpu object is created. Co-developed-by: Xianglai Li <lixianglai@loongson.cn> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
| * | hw/loongarch/virt: Implement cpu unplug interfaceBibo Mao2025-03-051-0/+58
| | | | | | | | | | | | | | | | | | | | | | | | Implement cpu unplug interfaces including virt_cpu_unplug_request() and virt_cpu_unplug(). Co-developed-by: Xianglai Li <lixianglai@loongson.cn> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
| * | hw/loongarch/virt: Add basic cpu plug interface frameworkBibo Mao2025-03-053-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | Add basic cpu hotplug interface framework, cpu hotplug interface is stub function and only framework is added here. Co-developed-by: Xianglai Li <lixianglai@loongson.cn> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
| * | hw/loongarch/virt: Add topo properties on CPU objectBibo Mao2025-03-052-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | Add some properties such as socket_id, core_id, thread_id and node_id on LoongArch CPU object. Co-developed-by: Xianglai Li <lixianglai@loongson.cn> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
| * | hw/loongarch/virt: Add CPU topology supportBibo Mao2025-03-052-8/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add topological relationships for Loongarch VCPU and initialize topology member variables. On LoongArch system there is socket/core/thread topo information, physical CPU id is calculated from CPU topo, every topo sub-field is aligned by power of 2. So it is different from logical cpu index. Co-developed-by: Xianglai Li <lixianglai@loongson.cn> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
| * | hw/intc/loongarch_extioi: Use cpu plug notificationBibo Mao2025-03-051-10/+2
| | | | | | | | | | | | | | | | | | | | | | | | Use hotplug_handler_plug() to nofity extioi object when cold-plug cpu is created, so that extioi can set and configure irq routing to new cpu. Signed-off-by: Bibo Mao <maobibo@loongson.cn>
| * | hw/intc/loongarch_extioi: Implment cpu hotplug interfaceBibo Mao2025-03-051-0/+45
| | | | | | | | | | | | | | | | | | When cpu is added, connect extioi gpio irq to CPU irq pin. Signed-off-by: Bibo Mao <maobibo@loongson.cn>
| * | hw/intc/loongarch_extioi: Add basic hotplug frameworkBibo Mao2025-03-051-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LoongArch extioi interrupt controller routes peripheral interrupt to multiple CPUs, physical cpu id is used in interrupt routing table. Here hotplug interface is added for extioi object, so that parent irq line can be connected, and routing table can be added for new created cpu. Here only basic hotplug framework is added, it is stub function. Signed-off-by: Bibo Mao <maobibo@loongson.cn>
| * | hw/intc/loongarch_extioi: Move gpio irq initial to common codeBibo Mao2025-03-052-8/+6
| | | | | | | | | | | | | | | | | | | | | | | | When cpu is added, it will connect gpio irq line to cpu irq. And cpu hot-add is put in common code, move gpio irq initial part into common code. Signed-off-by: Bibo Mao <maobibo@loongson.cn>
| * | hw/intc/loongarch_ipi: Notify ipi object when cpu is pluggedBibo Mao2025-03-051-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | Use hotplug_handler_plug() to nofity ipi object when cold-plug cpu is created, so that ipi can set and configure irq routing to new cpu. Signed-off-by: Bibo Mao <maobibo@loongson.cn>
| * | hw/intc/loongarch_ipi: Implment cpu hotplug interfaceBibo Mao2025-03-051-0/+39
| | | | | | | | | | | | | | | | | | | | | Add logic cpu allocation and cpu mapping with cpu hotplug interface. When cpu is added, connect ipi gpio irq to CPU IRQ_IPI irq pin. Signed-off-by: Bibo Mao <maobibo@loongson.cn>
| * | hw/intc/loongarch_ipi: Add basic hotplug frameworkBibo Mao2025-03-051-0/+32
| |/ | | | | | | | | | | | | | | | | | | | | LoongArch ipi can send interrupt to multiple CPUs, interrupt routing to CPU comes from destination physical cpu id. Here hotplug interface is added for IPI object, so that parent irq line can be connected, and routing table can be added for new created cpu. Here only basic hotplug framework is added, it is stub function. Signed-off-by: Bibo Mao <maobibo@loongson.cn>
* | Merge tag 'pull-riscv-to-apply-20250305-1' of ↵Stefan Hajnoczi2025-03-0550-271/+2106
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://github.com/alistair23/qemu into staging Third RISC-V PR for 10.0 * CSR coverity fixes * Fix unexpected behavior of vector reduction instructions when vl is 0 * Fix incorrect vlen comparison in prop_vlen_set * Throw debug exception before page fault * Remove redundant "hart_idx" masking from APLIC * Add support for Control Transfer Records Ext * Remove redundant struct members from the IOMMU * Remove duplicate definitions from the IOMMU * Fix tick_offset migration for Goldfish RTC * Add serial alias in virt machine DTB * Remove Bin Meng from RISC-V maintainers * Add support for Control Transfer Records Ext * Log guest errors when reserved bits are set in PTEs * Add missing Sdtrig disas CSRs * Correct the hpmevent sscofpmf mask * Mask upper sscofpmf bits during validation * Remove warnings about Smdbltrp/Smrnmi being disabled * Respect mseccfg.RLB bit for TOR mode PMP entry * Update KVM support to Linux 6.14-rc3 * IOMMU HPM support * Support Sscofpmf/Svade/Svadu/Smnpm/Ssnpm extensions in KVM * Add --ignore-family option to binfmt * Refinement for AIA with KVM acceleration * Reset time changes for KVM # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmfHrkEACgkQr3yVEwxT # gBNGTA/+N9nBPZt5cv0E/0EDZMQS8RQrQvz1yHRgAXOq8RnOdcL72v8wovGAfnVu # l0BXDoVBvw4f2Xm9Q4ptlfH8HAefCeQ4E/K9j5Lwxr8OqZHFg6e+JQIyZOt6wBWI # hJbz1/laJIbXq3cGgwcE/l0aGfb2UAAsA4dsZVt/MnjAV8GS7BF9RCkgCPxD4FZA # 0PLiq9dF+4o4q7PxnxAbUVz/uhLzqmcnQemQFHbf9Wms3tZEDKmPSoKP/v+01Rkw # tm+cgy7OocpgygbMc0nykYG50P+raUBSesk/jFGeKj8cU4IeMuzDsVPWcd4rG+0X # Z+nENfOY7vOqMCXgaQCW2r4vEQx2Gj0yQG6xmVAemRWzFHJdz5W01/uUSHzJSB+L # +VbAH55HYKr6sbgecqInQ/rsHKyw6D5QFcj/guz+kvhsH9rJ5q60uywrWL5OEuaK # vKv7cSZghlf9bwy6soassXxk8z+j4psJ7WnnVpynNKMew9yFFDhayuIFbo9952gH # 3+NCm2cQrkTYJOXAJwkxBD+I4AXxNSuxNjaVANk9q80uqbT9JiHM7pcvbJI00Fji # OutJSPYtVXEin9Ev3sJ05YQHsIcZ/Noi3O5IdaRI0AMk/8gyGyhFCVgSpV52dH59 # HguPK05e5cW/xgElGUPHrU+UtzE05p18HnSoVPclF/B5rc8QXN0= # =dobk # -----END PGP SIGNATURE----- # gpg: Signature made Wed 05 Mar 2025 09:52:01 HKT # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20250305-1' of https://github.com/alistair23/qemu: (59 commits) target/riscv/kvm: add missing KVM CSRs target/riscv/kvm: add kvm_riscv_reset_regs_csr() target/riscv/cpu: remove unneeded !kvm_enabled() check hw/intc/aplic: refine kvm_msicfgaddr hw/intc/aplic: refine the APLIC realize hw/intc/imsic: refine the IMSIC realize binfmt: Add --ignore-family option binfmt: Normalize host CPU architecture binfmt: Shuffle things around target/riscv/kvm: Add some exts support docs/specs/riscv-iommu.rst: add HPM support info hw/riscv: add IOMMU HPM trace events hw/riscv/riscv-iommu.c: add RISCV_IOMMU_CAP_HPM cap hw/riscv/riscv-iommu: add hpm events mmio write hw/riscv/riscv-iommu: add IOHPMCYCLES mmio write hw/riscv/riscv-iommu: add IOCOUNTINH mmio writes hw/riscv/riscv-iommu: instantiate hpm_timer hw/riscv/riscv-iommu: add riscv_iommu_hpm_incr_ctr() hw/riscv/riscv-iommu: add riscv-iommu-hpm file hw/riscv/riscv-iommu-bits.h: HPM bits ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * | target/riscv/kvm: add missing KVM CSRsDaniel Henrique Barboza2025-03-041-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We're missing scounteren and senvcfg CSRs, both already present in the KVM UAPI. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250224123120.1644186-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | target/riscv/kvm: add kvm_riscv_reset_regs_csr()Daniel Henrique Barboza2025-03-041-8/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We're setting reset vals for KVM csrs during kvm_riscv_reset_vcpu(), but in no particular order and missing some of them (like env->mstatus). Create a helper to do that, unclogging reset_vcpu(), and initialize env->mstatus as well. Keep the regs in the same order they appear in struct kvm_riscv_csr from the KVM UAPI, similar to what kvm_riscv_(get|put)_regs_csr are doing. This will make a bit easier to add new KVM CSRs and to verify which values we're writing back to KVM during vcpu reset. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250224123120.1644186-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | target/riscv/cpu: remove unneeded !kvm_enabled() checkDaniel Henrique Barboza2025-03-041-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the !kvm_enabled() check in kvm_riscv_reset_vcpu() since the function is already being gated by kvm_enabled() in riscv_cpu_reset_hold(). Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250224123120.1644186-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | hw/intc/aplic: refine kvm_msicfgaddrYong-Xuan Wang2025-03-041-11/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | Let kvm_msicfgaddr use the same format with mmsicfgaddr and smsicfgaddr. Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20250224025722.3999-4-yongxuan.wang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | hw/intc/aplic: refine the APLIC realizeYong-Xuan Wang2025-03-041-23/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the APLIC is emulated in the kernel, the GPIO output lines to CPUs can be remove. In this case the APLIC trigger CPU interrupts by KVM APIs. This patch also move the code that claim the CPU interrupts to the beginning of APLIC realization. This can avoid the unnecessary resource allocation before checking failed. Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20250224025722.3999-3-yongxuan.wang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | hw/intc/imsic: refine the IMSIC realizeYong-Xuan Wang2025-03-041-21/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the IMSIC is emulated in the kernel, the GPIO output lines to CPUs and aia_ireg_rmw_fn setting can be remove. In this case the IMSIC trigger CPU interrupts by KVM APIs, and the RMW of IREG is handled in kernel. This patch also move the code that claim the CPU interrupts to the beginning of IMSIC realization. This can avoid the unnecessary resource allocation before checking failed. Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20250224025722.3999-2-yongxuan.wang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | binfmt: Add --ignore-family optionAndrea Bolognani2025-03-041-3/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Until now, the script has worked under the assumption that a host CPU can run binaries targeting any CPU in the same family. That's a fair enough assumption when it comes to running i386 binaries on x86_64, but it doesn't quite apply in the general case. For example, while riscv64 CPUs could theoretically run riscv32 applications natively, in practice there exist few (if any?) CPUs that implement the necessary silicon; moreover, even if you had one such CPU, your host OS would most likely not have enabled the necessary kernel bits. This new option gives distro packagers the ability to opt out of the assumption, likely on a per-architecture basis, and make things work out of the box for a larger fraction of their user base. As an interesting side effect, this makes it possible to enable execution of 64-bit binaries on 32-bit CPUs of the same family, which is a perfectly valid use case that apparently hadn't been considered until now. Link: https://src.fedoraproject.org/rpms/qemu/pull-request/72 Thanks: David Abdurachmanov <davidlt@rivosinc.com> Thanks: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Andrea Bolognani <abologna@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-ID: <20250127182924.103510-4-abologna@redhat.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | binfmt: Normalize host CPU architectureAndrea Bolognani2025-03-041-19/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Right now information regarding the family each CPU type belongs to is recorded in two places: the large data table at the top of the script, and the qemu_host_family() function. We can make things better by mapping host CPU architecture to QEMU target in the few cases where the two don't already match and then using the data table to look up the family, same as we're already doing for the guest CPU architecture. Being able to reason in terms of QEMU target regardless of whether we're looking at the host or guest CPU architecture will come in handy to implement upcoming changes. A couple of entries are dropped in the process: BePC and Power Macintosh. I'm quite certain neither of those have ever been reported as CPU architectures by Linux. I believe many more of the entries that are carried forward could be dropped as well, but I don't have the same level of confidence there so I decided to play it safe just in case. Signed-off-by: Andrea Bolognani <abologna@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-ID: <20250127182924.103510-3-abologna@redhat.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | binfmt: Shuffle things aroundAndrea Bolognani2025-03-041-7/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This should make no difference from the functional point of view and it's just preparation for upcoming changes. Signed-off-by: Andrea Bolognani <abologna@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-ID: <20250127182924.103510-2-abologna@redhat.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | target/riscv/kvm: Add some exts supportQuan Zhou2025-03-041-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the Sscofpmf/Svade/Svadu/Smnpm/Ssnpm exts is available expose it to the guest so that guest can use it. Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <303616ccad2b5309768157b50d93b3e89fecc9cb.1740371468.git.zhouquan@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | docs/specs/riscv-iommu.rst: add HPM support infoDaniel Henrique Barboza2025-03-041-0/+2
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250224190826.1858473-12-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | hw/riscv: add IOMMU HPM trace eventsDaniel Henrique Barboza2025-03-042-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a handful of trace events to allow for an easier time debugging the HPM feature. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250224190826.1858473-11-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | hw/riscv/riscv-iommu.c: add RISCV_IOMMU_CAP_HPM capTomasz Jeznach2025-03-041-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have every piece in place we can advertise CAP_HTM to software, allowing any HPM aware driver to make use of the counters. HPM is enabled/disabled via the 'hpm-counters' attribute. Default value is 31, max value is also 31. Setting it to zero will disable HPM support. Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250224190826.1858473-10-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | hw/riscv/riscv-iommu: add hpm events mmio writeTomasz Jeznach2025-03-044-1/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To support hpm events mmio writes, done via riscv_iommu_process_hpmevt_write(), we're also adding the 'hpm-counters' IOMMU property that are used to determine the amount of counters available in the IOMMU. Note that everything we did so far didn't change any IOMMU behavior because we're still not advertising HPM capability to software. This will be done in the next patch. Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250224190826.1858473-9-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | hw/riscv/riscv-iommu: add IOHPMCYCLES mmio writeTomasz Jeznach2025-03-043-1/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RISCV_IOMMU_REG_IOHPMCYCLES writes are done by riscv_iommu_process_hpmcycle_write(), called by the mmio write callback via riscv_iommu_process_hpm_writes(). Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250224190826.1858473-8-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | hw/riscv/riscv-iommu: add IOCOUNTINH mmio writesTomasz Jeznach2025-03-043-0/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RISCV_IOMMU_REG_IOCOUNTINH is done by riscv_iommu_process_iocntinh_cy(), which is called during riscv_iommu_mmio_write() callback via a new riscv_iommu_pricess_hpm_writes() helper. Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250224190826.1858473-7-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | hw/riscv/riscv-iommu: instantiate hpm_timerTomasz Jeznach2025-03-044-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The next HPM related changes requires the HPM overflow timer to be initialized by the riscv-iommu base emulation. Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250224190826.1858473-6-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | hw/riscv/riscv-iommu: add riscv_iommu_hpm_incr_ctr()Tomasz Jeznach2025-03-044-15/+162
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function will increment a specific counter, generating an interrupt when an overflow occurs. Some extra changes in riscv-iommu.c were required to add this new helper in riscv-iommu-hpm.c: - RISCVIOMMUContext was moved to riscv-iommu.h, making it visible in riscv-iommu-hpm.c; - riscv_iommu_notify() is now public. No behavior change is made since HPM support is not being advertised yet. Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250224190826.1858473-5-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | hw/riscv/riscv-iommu: add riscv-iommu-hpm fileTomasz Jeznach2025-03-045-2/+110
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The HPM (Hardware Performance Monitor) support consists of almost 7 hundred lines that would be put on top of the base riscv-iommu emulation. To avoid clogging riscv-iommu.c, add a separated riscv-iommu-hpm file that will contain HPM specific code. We'll start by adding riscv_iommu_hpmcycle_read(), a helper that will be called during the riscv_iommu_mmio_read() callback. This change will have no effect on the existing emulation since we're not declaring HPM feature support. Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250224190826.1858473-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | hw/riscv/riscv-iommu-bits.h: HPM bitsTomasz Jeznach2025-03-041-0/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the relevant HPM (High Performance Monitor) bits that we'll be using in the next patches. Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250224190826.1858473-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | hw/riscv/riscv-iommu.h: add missing headersDaniel Henrique Barboza2025-03-041-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This header is incomplete, i.e. it is using definitions that are being supplied by the .c files that are including it. Adding this header into a fresh .c file will result in errors: /home/danielhb/work/qemu/hw/riscv/riscv-iommu.h:30:17: error: field ‘parent_obj’ has incomplete type 30 | DeviceState parent_obj; | ^~~~~~~~~~ /home/danielhb/work/qemu/hw/riscv/riscv-iommu.h:50:5: error: unknown type name ‘dma_addr_t’; did you mean ‘in_addr_t’? 50 | dma_addr_t cq_addr; /* Command queue base physical address */ | ^~~~~~~~~~ | in_addr_t (...) /home/danielhb/work/qemu/hw/riscv/riscv-iommu.h:62:5: error: unknown type name ‘QemuThread’; did you mean ‘GThread’? 62 | QemuThread core_proc; /* Background processing thread */ | ^~~~~~~~~~ | GThread /home/danielhb/work/qemu/hw/riscv/riscv-iommu.h:63:5: error: unknown type name ‘QemuCond’ 63 | QemuCond core_cond; /* Background processing wake up signal */ | ^~~~~~~~ /home/danielhb/work/qemu/hw/riscv/riscv-iommu.h:71:18: error: field ‘trap_as’ has incomplete type 71 | AddressSpace trap_as; | ^~~~~~~ /home/danielhb/work/qemu/hw/riscv/riscv-iommu.h:72:18: error: field ‘trap_mr’ has incomplete type 72 | MemoryRegion trap_mr; | ^~~~~~~ /home/danielhb/work/qemu/hw/riscv/riscv-iommu.h:80:18: error: field ‘regs_mr’ has incomplete type 80 | MemoryRegion regs_mr; | ^~~~~~~ Fix it by adding the missing headers for these definitions. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250224190826.1858473-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | target/riscv/kvm: add extensions after 6.14-rc3 updateDaniel Henrique Barboza2025-03-041-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Expose ziccrse, zabha and svvptc. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20250221153758.652078-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>