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* block/rbd: workaround for ceph issue #53784Peter Lieven2022-02-011-2/+40
| | | | | | | | | | | | | | | | | librbd had a bug until early 2022 that affected all versions of ceph that supported fast-diff. This bug results in reporting of incorrect offsets if the offset parameter to rbd_diff_iterate2 is not object aligned. This patch works around this bug for pre Quincy versions of librbd. Fixes: 0347a8fd4c3faaedf119be04c197804be40a384b Cc: qemu-stable@nongnu.org Signed-off-by: Peter Lieven <pl@kamp.de> Message-Id: <20220113144426.4036493-3-pl@kamp.de> Reviewed-by: Ilya Dryomov <idryomov@gmail.com> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Tested-by: Stefano Garzarella <sgarzare@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* block/rbd: fix handling of holes in .bdrv_co_block_statusPeter Lieven2022-02-011-5/+5
| | | | | | | | | | | | | | | | | | | the assumption that we can't hit a hole if we do not diff against a snapshot was wrong. We can see a hole in an image if we diff against base if there exists an older snapshot of the image and we have discarded blocks in the image where the snapshot has data. Fix this by simply handling a hole like an unallocated area. There are no callbacks for unallocated areas so just bail out if we hit a hole. Fixes: 0347a8fd4c3faaedf119be04c197804be40a384b Suggested-by: Ilya Dryomov <idryomov@gmail.com> Cc: qemu-stable@nongnu.org Signed-off-by: Peter Lieven <pl@kamp.de> Message-Id: <20220113144426.4036493-2-pl@kamp.de> Reviewed-by: Ilya Dryomov <idryomov@gmail.com> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* qemu-img: Unify [-b [-F]] documentationHanna Reitz2022-02-012-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | qemu-img convert documents the backing file and backing format options as follows: [-B backing_file [-F backing_fmt]] whereas qemu-img create has this: [-b backing_file] [-F backing_fmt] That is, for convert, we document that -F cannot be given without -B, while for create, way say that they are independent. Indeed, it is technically possible to give -F without -b, because it is left to the block driver to decide whether this is an error or not, so sometimes it is: $ qemu-img create -f qed -F qed test.qed 64M Formatting 'test.qed', fmt=qed size=67108864 backing_fmt=qed [...] And sometimes it is not: $ qemu-img create -f qcow2 -F qcow2 test.qcow2 64M Formatting 'test.qcow2', fmt=qcow2 cluster_size=65536 [...] qemu-img: test.qcow2: Backing format cannot be used without backing file Generally, it does not make much sense, though, and users should only give -F with -b, so document it that way, as we have already done for qemu-img convert (commit 1899bf47375ad40555dcdff12ba49b4b8b82df38). Reported-by: Tingting Mao <timao@redhat.com> Signed-off-by: Hanna Reitz <hreitz@redhat.com> Message-Id: <20220131135908.32393-1-hreitz@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* qsd: Document fuse's allow-other optionHanna Reitz2022-02-012-3/+8
| | | | | | | | | | | We did not add documentation to the storage daemon's man page for fuse's allow-other option when it was introduced, so do that now. Fixes: 8fc54f9428b9763f800 ("export/fuse: Add allow-other option") Signed-off-by: Hanna Reitz <hreitz@redhat.com> Message-Id: <20220131103124.20325-1-hreitz@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* block.h: remove outdated commentEmanuele Giuseppe Esposito2022-02-011-1/+0
| | | | | | | | | | | | | The comment "disk I/O throttling" doesn't make any sense at all any more. It was added in commit 0563e191516 to describe bdrv_io_limits_enable()/disable(), which were removed in commit 97148076, so the comment is just a forgotten leftover. Suggested-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Emanuele Giuseppe Esposito <eesposit@redhat.com> Message-Id: <20220131125615.74612-1-eesposit@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* block/export/fuse: Fix build failure on FreeBSDPhilippe Mathieu-Daudé2022-02-011-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When building on FreeBSD we get: [816/6851] Compiling C object libblockdev.fa.p/block_export_fuse.c.o ../block/export/fuse.c:628:16: error: use of undeclared identifier 'FALLOC_FL_KEEP_SIZE' if (mode & FALLOC_FL_KEEP_SIZE) { ^ ../block/export/fuse.c:651:16: error: use of undeclared identifier 'FALLOC_FL_PUNCH_HOLE' if (mode & FALLOC_FL_PUNCH_HOLE) { ^ ../block/export/fuse.c:652:22: error: use of undeclared identifier 'FALLOC_FL_KEEP_SIZE' if (!(mode & FALLOC_FL_KEEP_SIZE)) { ^ 3 errors generated. FAILED: libblockdev.fa.p/block_export_fuse.c.o Meson indeed reported FALLOC_FL_PUNCH_HOLE is not available: C compiler for the host machine: cc (clang 10.0.1 "FreeBSD clang version 10.0.1") Checking for function "fallocate" : NO Checking for function "posix_fallocate" : YES Header <linux/falloc.h> has symbol "FALLOC_FL_PUNCH_HOLE" : NO Header <linux/falloc.h> has symbol "FALLOC_FL_ZERO_RANGE" : NO ... Similarly to commit 304332039 ("block/export/fuse.c: fix musl build"), guard the code requiring FALLOC_FL_KEEP_SIZE / FALLOC_FL_PUNCH_HOLE definitions under CONFIG_FALLOCATE_PUNCH_HOLE #ifdef'ry. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220201112655.344373-3-f4bug@amsat.org> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* block/export/fuse: Rearrange if-else-if ladder in fuse_fallocate()Philippe Mathieu-Daudé2022-02-011-20/+21
| | | | | | | | | | | | | In order to safely maintain a mixture of #ifdef'ry with if-else-if ladder, rearrange the last statement (!mode) first. Since it is mutually exclusive with the other conditions, checking it first doesn't make any logical difference, but allows to add #ifdef'ry around in a more cleanly way. Suggested-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220201112655.344373-2-f4bug@amsat.org> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* block/export: Fix vhost-user-blk shutdown with requests in flightKevin Wolf2022-02-013-0/+32
| | | | | | | | | | | | | | | | The vhost-user-blk export runs requests asynchronously in their own coroutine. When the vhost connection goes away and we want to stop the vhost-user server, we need to wait for these coroutines to stop before we can unmap the shared memory. Otherwise, they would still access the unmapped memory and crash. This introduces a refcount to VuServer which is increased when spawning a new request coroutine and decreased before the coroutine exits. The memory is only unmapped when the refcount reaches zero. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Message-Id: <20220125151435.48792-1-kwolf@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* block: bdrv_set_backing_hd(): use drained sectionVladimir Sementsov-Ogievskiy2022-02-011-0/+4
| | | | | | | | | | | | | | | | Graph modifications should be done in drained section. stream_prepare() handler of block stream job call bdrv_set_backing_hd() without using drained section and it's theoretically possible that some IO request will interleave with graph modification and will use outdated pointers to removed block nodes. Some other callers use bdrv_set_backing_hd() not caring about drained sections too. So it seems good to make a drained section exactly in bdrv_set_backing_hd(). Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-Id: <20220124173741.2984056-1-vsementsov@virtuozzo.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* qemu-storage-daemon: Fix typo in vhost-user-blk helpKevin Wolf2022-02-011-1/+1
| | | | | | | | | The syntax of the fd passing case misses the "addr.type=" key. Add it. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Message-Id: <20220125151514.49035-1-kwolf@redhat.com> Reviewed-by: Hanna Reitz <hreitz@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220130' into ↵Peter Maydell2022-01-3121-355/+761
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging ppc 7.0 queue: * Exception and TLB fixes for the 405 CPU (Fabiano and Cedric) * spapr fixes (Alexey and Daniel) * PowerNV PHB3/4 fixes (Frederic and Daniel) * PowerNV XIVE improvements (Cedric) * 603 CPUs fixes (Christophe) * Book-E exception fixes (Vitaly) * Misc compile issues (Philippe and Fabiano) * Exception model rework for the BookS CPUs (Fabiano) * Exception model rework for the 74xx CPUs (Fabiano) * Removal of 602 CPUs # gpg: Signature made Sun 30 Jan 2022 17:42:23 GMT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * remotes/legoater/tags/pull-ppc-20220130: (41 commits) target/ppc: Remove support for the PowerPC 602 CPU target/ppc: 74xx: Set SRRs directly in exception code target/ppc: 74xx: System Reset interrupt cleanup target/ppc: 74xx: System Call exception cleanup target/ppc: 74xx: Program exception cleanup target/ppc: 74xx: External interrupt cleanup target/ppc: 74xx: Machine Check exception cleanup target/ppc: Simplify powerpc_excp_74xx target/ppc: Introduce powerpc_excp_74xx target/ppc: books: Program exception cleanup target/ppc: books: External interrupt cleanup target/ppc: books: Machine Check exception cleanup target/ppc: Simplify powerpc_excp_books target/ppc: Introduce powerpc_excp_books target/ppc: 405: Watchdog timer exception cleanup target/ppc: 405: Program exception cleanup target/ppc: 405: Instruction storage interrupt cleanup target/ppc: 405: Data Storage exception cleanup target/ppc: 405: Debug exception cleanup target/ppc: 405: Alignment exception cleanup ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/ppc: Remove support for the PowerPC 602 CPUCédric Le Goater2022-01-2810-322/+1
| | | | | | | | | | | | | | | | The 602 was derived from the PowerPC 603, for the gaming market it seems. It was hardly used and no firmware supporting the CPU could be found. Drop support. Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * target/ppc: 74xx: Set SRRs directly in exception codeFabiano Rosas2022-01-281-11/+2
| | | | | | | | | | | | | | | | | | The 74xx does not have alternate/hypervisor Save and Restore Registers, so we can set SRR0 and SRR1 directly. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220127201116.1154733-9-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * target/ppc: 74xx: System Reset interrupt cleanupFabiano Rosas2022-01-281-16/+2
| | | | | | | | | | | | | | | | | | | | The whole power saving states logic seems to be dependent on HV mode, which don't exist for 74xx so I'm removing it all and leaving the abort message. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220127201116.1154733-8-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * target/ppc: 74xx: System Call exception cleanupFabiano Rosas2022-01-281-6/+11
| | | | | | | | | | | | | | | | | | | | Remove the BookE code and add a comment explaining why we need to keep hypercall support even though this CPU does not have a hypervisor mode. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220127201116.1154733-7-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * target/ppc: 74xx: Program exception cleanupFabiano Rosas2022-01-281-4/+0
| | | | | | | | | | | | | | | | Remove the BookE ESR setting. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220127201116.1154733-6-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * target/ppc: 74xx: External interrupt cleanupFabiano Rosas2022-01-281-38/+0
| | | | | | | | | | | | | | | | | | | | The 74xx don't have MSR_HV so all the LPES0 logic can be removed. Also remove the BookE IRQ code. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220127201116.1154733-5-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * target/ppc: 74xx: Machine Check exception cleanupFabiano Rosas2022-01-281-24/+0
| | | | | | | | | | | | | | | | | | | | The 74xx don't have an MSR_HV. Also remove 40x and BookE code. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220127201116.1154733-4-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * target/ppc: Simplify powerpc_excp_74xxFabiano Rosas2022-01-281-202/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Differences from the generic powerpc_excp code: - Not BookE, so some MSR bits are cleared at interrupt dispatch; - No MSR_HV; - No power saving states; - No Hypervisor Emulation Assistance; - Not 64 bits; - No System call vectored; - No Alternate Interrupt Location. Exceptions used: POWERPC_EXCP_ALIGN POWERPC_EXCP_DECR POWERPC_EXCP_DSI POWERPC_EXCP_EXTERNAL POWERPC_EXCP_FPU POWERPC_EXCP_IABR POWERPC_EXCP_ISI POWERPC_EXCP_MCHECK POWERPC_EXCP_PERFM POWERPC_EXCP_PROGRAM POWERPC_EXCP_RESET POWERPC_EXCP_SMI POWERPC_EXCP_SYSCALL POWERPC_EXCP_THERM POWERPC_EXCP_TRACE POWERPC_EXCP_VPU POWERPC_EXCP_VPUA Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220127201116.1154733-3-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * target/ppc: Introduce powerpc_excp_74xxFabiano Rosas2022-01-281-0/+474
| | | | | | | | | | | | | | | | | | | | Introduce a new powerpc_excp function specific for PowerPC 74xx CPUs. This commit copies powerpc_excp_legacy verbatim so the next one has a clean diff. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220127201116.1154733-2-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * target/ppc: books: Program exception cleanupFabiano Rosas2022-01-281-4/+0
| | | | | | | | | | | | | | | | | | Remove setting of BookE registers. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220124184605.999353-6-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * target/ppc: books: External interrupt cleanupFabiano Rosas2022-01-281-23/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Since this is now BookS only, we can simplify the code a bit and check has_hv_mode instead of enumerating the exception models. LPES0 does not make sense if there is no MSR_HV. Note that QEMU does not support HV mode on 970 and POWER5+ so we don't set MSR_HV in msr_mask. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220124184605.999353-5-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * target/ppc: books: Machine Check exception cleanupFabiano Rosas2022-01-281-17/+0
| | | | | | | | | | | | | | | | | | powerpc_excp_books is BookS only, so remove 40x and BookE code. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220124184605.999353-4-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * target/ppc: Simplify powerpc_excp_booksFabiano Rosas2022-01-281-147/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Differences from the generic powerpc_excp code: - Not BookE, so some MSR bits are cleared at interrupt dispatch; - Always uses HV_EMU if the CPU has MSR_HV; - Exceptions always delivered in 64 bit. Exceptions used: POWERPC_EXCP_ALIGN POWERPC_EXCP_DECR POWERPC_EXCP_DSEG POWERPC_EXCP_DSI POWERPC_EXCP_EXTERNAL POWERPC_EXCP_FPU POWERPC_EXCP_FU POWERPC_EXCP_HDECR POWERPC_EXCP_HDSI POWERPC_EXCP_HISI POWERPC_EXCP_HVIRT POWERPC_EXCP_HV_EMU POWERPC_EXCP_HV_FU POWERPC_EXCP_ISEG POWERPC_EXCP_ISI POWERPC_EXCP_MAINT POWERPC_EXCP_MCHECK POWERPC_EXCP_PERFM POWERPC_EXCP_PROGRAM POWERPC_EXCP_RESET POWERPC_EXCP_SDOOR_HV POWERPC_EXCP_SYSCALL POWERPC_EXCP_SYSCALL_VECTORED POWERPC_EXCP_THERM POWERPC_EXCP_TRACE POWERPC_EXCP_VPU POWERPC_EXCP_VPUA POWERPC_EXCP_VSXU POWERPC_EXCP_HV_MAINT POWERPC_EXCP_SDOOR (I added the two above that were not being considered. They used to be "Invalid exception". Now they become "Unimplemented exception" which is more accurate.) Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220124184605.999353-3-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * target/ppc: Introduce powerpc_excp_booksFabiano Rosas2022-01-281-0/+478
| | | | | | | | | | | | | | | | | | | | | | Introduce a new powerpc_excp function specific for BookS CPUs. This commit copies powerpc_excp_legacy verbatim so the next one has a clean diff. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220124184605.999353-2-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * target/ppc: 405: Watchdog timer exception cleanupFabiano Rosas2022-01-281-9/+0
| | | | | | | | | | | | | | | | | | Remove references to BookE. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220118184448.852996-15-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * target/ppc: 405: Program exception cleanupFabiano Rosas2022-01-281-15/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The 405 Program Interrupt does not set SRR1 with any diagnostic bits, just a clean copy of the MSR. We're using the BookE Exception Syndrome Register which is different from the 405. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> [ clg: restored SPR_40x_ESR settings ] Message-Id: <20220118184448.852996-14-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * target/ppc: 405: Instruction storage interrupt cleanupFabiano Rosas2022-01-281-1/+0
| | | | | | | | | | | | | | | | | | | | | | The 405 ISI does not set SRR1 with any exception syndrome bits, only a clean copy of the MSR. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> [ clg : Fixed removal which was done in the wrong routine ] Message-Id: <20220118184448.852996-13-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * target/ppc: 405: Data Storage exception cleanupFabiano Rosas2022-01-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The 405 has no DSISR or DAR, so convert the trace entry to use ESR and DEAR instead. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> [ clg : - changed registers to ESR and DEAR. - updated commit log ] Message-Id: <20220118184448.852996-12-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * target/ppc: 405: Debug exception cleanupFabiano Rosas2022-01-281-14/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current Debug exception dispatch is the BookE one, so it is different from the 405. We effectively don't support the 405 Debug exception. This patch removes the BookE code and moves the DEBUG into the "not implemented" block. Note that there is in theory a functional change here since we now abort when a Debug exception happens. However, given how it was never implemented, I don't believe this to have ever been dispatched for the 405. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220118184448.852996-11-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * target/ppc: 405: Alignment exception cleanupFabiano Rosas2022-01-281-7/+0
| | | | | | | | | | | | | | | | | | | | There is no DSISR in the 405. It uses DEAR which we already set earlier at ppc_cpu_do_unaligned_access. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au Message-Id: <20220118184448.852996-10-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * target/ppc: 405: System call exception cleanupFabiano Rosas2022-01-281-19/+2
| | | | | | | | | | | | | | | | | | | | There's no sc 1. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220118184448.852996-9-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * target/ppc: 405: External exception cleanupFabiano Rosas2022-01-281-37/+0
| | | | | | | | | | | | | | | | | | 405 has no MSR_HV and EPR is BookE only so we can remove it all. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220118184448.852996-8-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * target/ppc: 405: Machine check exception cleanupFabiano Rosas2022-01-281-24/+2
| | | | | | | | | | | | | | | | | | | | powerpc_excp_40x applies only to the 405, so remove HV code and references to BookE. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220118184448.852996-7-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * target/ppc: 405: Critical exceptions cleanupFabiano Rosas2022-01-281-15/+2
| | | | | | | | | | | | | | | | | | | | | | In powerpc_excp_40x the Critical exception is now for 405 only, so we can remove the BookE and G2 blocks. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220118184448.852996-6-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * target/ppc: Simplify powerpc_excp_40xFabiano Rosas2022-01-281-195/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Differences from the generic powerpc_excp code: - Not BookE, so some MSR bits are cleared at interrupt dispatch; - No MSR_HV or MSR_LE; - No power saving states; - No Hypervisor Emulation Assistance; - Not 64 bits; - No System call vectored; - No Interrupts Little Endian; - No Alternate Interrupt Location. Exceptions used: POWERPC_EXCP_ALIGN POWERPC_EXCP_CRITICAL POWERPC_EXCP_DEBUG POWERPC_EXCP_DSI POWERPC_EXCP_DTLB POWERPC_EXCP_EXTERNAL POWERPC_EXCP_FIT POWERPC_EXCP_ISI POWERPC_EXCP_ITLB POWERPC_EXCP_MCHECK POWERPC_EXCP_PIT POWERPC_EXCP_PROGRAM POWERPC_EXCP_SYSCALL POWERPC_EXCP_WDT Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220118184448.852996-5-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * target/ppc: Introduce powerpc_excp_40xFabiano Rosas2022-01-281-0/+474
| | | | | | | | | | | | | | | | | | | | | | | | Introduce a new powerpc_excp function specific for 40x CPUs. This commit copies powerpc_excp_legacy verbatim so the next one has a clean diff. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220118184448.852996-4-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * target/ppc: 405: Add missing MSR_ME bitFabiano Rosas2022-01-281-0/+1
| | | | | | | | | | | | | | | | | | | | The 405 MSR has the Machine Check Enable bit. We're making use of it when dispatching Machine Check, so add the bit to the msr_mask. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220118184448.852996-3-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * target/ppc: 405: Rename MSR_POW to MSR_WEFabiano Rosas2022-01-282-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Bit 13 is the Wait State Enable bit. Give it its proper name. As far as I can see we don't do anything with MSR_POW for the 405, so this change has no effect. Suggested-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220118184448.852996-2-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * ppc/ppc405: Fix TLB flushingCédric Le Goater2022-01-283-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit cd0c6f473532 did not take into account 405 CPUs when adding support to batching of TCG tlb flushes. Set the TLB_NEED_LOCAL_FLUSH flag when the SPR_40x_PID is set or a TLB updated. Cc: Thomas Huth <thuth@redhat.com> Cc: Christophe Leroy <christophe.leroy@csgroup.eu> Cc: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> Fixes: cd0c6f473532 ("ppc: Do some batching of TCG tlb flushes") Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220113180352.1234512-1-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * hw/ppc/vof: Add missing includesPhilippe Mathieu-Daudé2022-01-282-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | vof.h requires "qom/object.h" for DECLARE_CLASS_CHECKERS(), "exec/memory.h" for address_space_read/write(), "exec/address-spaces.h" for address_space_memory and more importantly "cpu.h" for target_ulong. vof.c doesn't need "exec/ram_addr.h". Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220122003104.84391-1-f4bug@amsat.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * target/ppc: Put do_rfi under a TCG-only blockFabiano Rosas2022-01-281-2/+0
| | | | | | | | | | | | | | | | | | | | | | The --disable-tcg build broke when do_rfi stopped being inlined. Fixes: 62e79ef914 ("target/ppc: Remove static inline") Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220124191547.1008391-1-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * target/ppc: Fix test on mmu_model in hreg_compute_hflags_value()Cédric Le Goater2022-01-281-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | POWERPC_MMU_BOOKE is not a mask and should not be tested with a bitwise AND operator. It went unnoticed because it only impacts the 601 CPU implementation for which we don't have a known firmware image. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220124081609.3672341-1-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * spapr.c: check bus != NULL in spapr_get_fw_dev_path()Daniel Henrique Barboza2022-01-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | spapr_get_fw_dev_path() is an impl of FWPathProviderClass::get_dev_path(). This interface is used by hw/core/qdev-fw.c via fw_path_provider_try_get_dev_path() in two functions: - static char *qdev_get_fw_dev_path_from_handler(), which is used only in qdev_get_fw_dev_path_helper() and it's guarded by "if (dev && dev->parent_bus)"; - char *qdev_get_own_fw_dev_path_from_handler(), which is used in softmmu/bootdevice.c in get_boot_device_path() like this: if (dev) { d = qdev_get_own_fw_dev_path_from_handler(dev->parent_bus, dev); This means that, when called via softmmu/bootdevice.c, there's no check of 'dev->parent_bus' being not NULL. The result is that the "BusState *bus" arg of spapr_get_fw_dev_path() can potentially be NULL and if, at the same time, "SCSIDevice *d" is not NULL, we'll hit this line: void *spapr = CAST(void, bus->parent, "spapr-vscsi"); And we'll SIGINT because 'bus' is NULL and we're accessing bus->parent. Adding a simple 'bus != NULL' check to guard the instances where we access 'bus->parent' can avoid this altogether. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220121213852.30243-1-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * target/ppc: fix 'skip KVM' cond in cpu_interrupt_exittb()Daniel Henrique Barboza2022-01-281-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cpu_interrupt_exittb() was introduced by commit 044897ef4a22 ("target/ppc: Fix system lockups caused by interrupt_request state corruption") as a way to wrap cpu_interrupt() helper in BQL. After that, commit 6d38666a8931 ("ppc: Ignore the CPU_INTERRUPT_EXITTB interrupt with KVM") added a condition to skip this interrupt if we're running with KVM. Problem is that the change made by the above commit, testing for !kvm_enabled() at the start of cpu_interrupt_exittb(): static inline void cpu_interrupt_exittb(CPUState *cs) { if (!kvm_enabled()) { return; } (... do cpu_interrupt(cs, CPU_INTERRUPT_EXITTB) ...) is doing the opposite of what it intended to do. This will return immediately if not kvm_enabled(), i.e. it's a emulated CPU, and if kvm_enabled() it will proceed to fire CPU_INTERRUPT_EXITTB. Fix the 'skip KVM' condition so the function is a no-op when kvm_enabled(). CC: Greg Kurz <groug@kaod.org> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/809 Fixes: 6d38666a8931 ("ppc: Ignore the CPU_INTERRUPT_EXITTB interrupt with KVM") Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Greg Kurz <groug@kaod.org> Message-Id: <20220121160841.9102-1-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * ppc/xive: check return value of ldq_be_dma()Cédric Le Goater2022-01-281-4/+18
| | | | | | | | | | | | | | | | | | | | | | The ldq_be_dma() routine was recently changed to return a result of the transaction. Use it when loading the virtual structure descriptors in the XIVE PowerNV model. Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220124081635.3672439-1-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * ppc/pnv: use a do-while() loop in pnv_phb4_translate_tve()Daniel Henrique Barboza2022-01-281-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pnv_phb4_translate_tve() is quite similar to pnv_phb3_translate_tve(), and that includes the fact that 'taddr' can be considered uninitialized when throwing the "TCE access fault" error because, in theory, the loop that sets 'taddr' can be skippable due to 'lev' being an signed int. No one complained about this specific case yet, but since we took the time to handle the same situtation in pnv_phb3_translate_tve(), let's replicate it here as well. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220127122234.842145-3-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * ppc/pnv: use a do-while() loop in pnv_phb3_translate_tve()Daniel Henrique Barboza2022-01-281-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'taddr' variable is left unintialized, being set only inside the "while ((lev--) >= 0)" loop where we get the TCE address. The 'lev' var is an int32_t that is being initiliazed by the GETFIELD() macro, which returns an uint64_t. For a human reader this means that 'lev' will always be positive or zero. But some compilers may beg to differ. 'lev' being an int32_t can in theory be set as negative, and the "while ((lev--) >= 0)" loop might never be reached, and 'taddr' will be left unitialized. This can cause phb3_error() to use 'taddr' uninitialized down below: if ((is_write & !(tce & 2)) || ((!is_write) && !(tce & 1))) { phb3_error(phb, "TCE access fault at 0x%"PRIx64, taddr); A quick way of fixing it is to use a do/while() loop. This will keep the same semanting as the existing while() loop does and the compiler will understand that 'taddr' will be initialized at least once. Suggested-by: Matheus K. Ferst <matheus.ferst@eldorado.org.br> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/573 Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220127122234.842145-2-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * ppc/pnv: Fail DMA access if page permissions are not correctFrederic Barrat2022-01-282-10/+12
| | | | | | | | | | | | | | | | | | | | If an iommu page has wrong permissions, an error message is displayed, but the access is allowed, which is odd. This patch fixes it. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220121152350.381685-1-fbarrat@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * target/ppc/mmu_common: Fix SRR1/MSR error code on Book-EVitaly Cheptsov2022-01-281-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Book-E architecture does not set the error code in 31:27 bits of SRR1, but instead uses these bits for custom fields such as GS (Guest Supervisor). Wrongly setting these fields will result in QEMU crashes when attempting to execute not executable code due to the attempts to use Guest Supervisor mode. Cc: "Cédric Le Goater" <clg@kaod.org> Cc: Daniel Henrique Barboza <danielhb413@gmail.com> Cc: David Gibson <david@gibson.dropbear.id.au> Cc: Greg Kurz <groug@kaod.org> Cc: qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org Signed-off-by: Vitaly Cheptsov <cheptsov@ispras.ru> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220121093107.15478-1-cheptsov@ispras.ru> Signed-off-by: Cédric Le Goater <clg@kaod.org>