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| * loongarch: add a direct interrupt controller deviceSong Gao2025-09-285-0/+108
| | | | | | | | | | | | | | | | Add Loongarch direct interrupt controller device base Definition. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn> Message-ID: <20250916122109.749813-5-gaosong@loongson.cn>
| * hw/loongarch: add misc register support dmsiSong Gao2025-09-281-0/+11
| | | | | | | | | | | | | | | | | | Add feature register and misc register for dmsi feature checking and setting Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn> Message-ID: <20250916122109.749813-4-gaosong@loongson.cn>
| * hw/loongarch: add virt feature dmsi supportSong Gao2025-09-284-0/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dmsi feature is added in LoongArchVirtMachinState, and it is used to check whether virt machine supports the directy Message-Interrupts. and by default set dmsi with ON_OFF_AUTO_AUTO. LoongArchVirtMachineState adds misc_feature and misc_status for misc features and status. and set the default dintc feature bit. Msgint feature is added in LoongArchCPU, and it is used to check whether th cpu supports the Message-Interrupts and by default set mesgint with ON_OFF_AUTO_AUTO. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn> Message-ID: <20250916122109.749813-3-gaosong@loongson.cn>
| * target/loongarch: move some machine define to virt.hSong Gao2025-09-282-21/+19
|/ | | | | | | | move some machine define to virt.h Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn> Message-ID: <20250916122109.749813-2-gaosong@loongson.cn>
* Merge tag 'pull-target-arm-20250926' of https://gitlab.com/pm215/qemu into ↵Richard Henderson2025-09-2621-1236/+1199
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging target-arm queue: * reimplement VHE alias register handling * replace magic GIC values by proper definitions * convert power control DPRINTF() uses to trace events * better reset related tracepoints * implement ID_AA64PFR2_EL1 * hw/usb/hcd-uhci: don't assert for SETUP to non-0 endpoint * net/passt: Fix build failure due to missing GIO dependency # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmjWnkUZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3upeD/4x0k6ciiJ2wRE1PFUA2KHZ # bS12+j6Um5BNdcZtRV1aT3x3xOrW3X0JTcmhb9/UdpEPki/krQQgQX50tOiLCeU2 # U4lZke5160Gk3ThdkpELlQDnCVDuNR0wxYgy1GBgAInCa/T/qFnyWwaWBIooCCUh # +UMJ9tP4XWKvKlkzw9ONFYChxerY2enpOewEbnfSU4NPg9pU8OEZ3yeFWaLZ3Tnl # 0bei/iFFeuN8RtgJEkuqWI6oENEZZbxGtJ+J/+wvggAfOzfy0I6CmW6y9tQMmKe8 # fTnCQ837uHmlRPWQ615M2wWydbJ1ffdEIYDb5U6UsbfG8sMt5+qg38yo0AyDs6RK # qJkTceuhqFTDIoi92o2+NFnohCTfASeYaCHjODgcdjGUtbZO7LZ31fOKQrdsHc5e # chAOnzNxCu9Bt4UqpUmb+ED0fXWDahV1tmgazFS2LORYxnr2q+/WJEdwSgHXNzVy # 2rdyUx7v7U1finhRE1nAdy8XwJTCQ3gDwDbPGBrH9mhR9DnK6eotFCljI2XnDtAE # f1i0w/47cnyRW6KsBVK6dJObiOfBRrRYqe3Rt4nA4xjeCNmWcr5IcytpnL/2YT1p # 1vj+RklbcK7Ns+kWH3H2a9b44zKQrtGGXf8fcNyAqT1YrzrrLUqaiKTfesGfjWit # ekMWOulOe6UePnoC3SJHFw== # =+Aj+ # -----END PGP SIGNATURE----- # gpg: Signature made Fri 26 Sep 2025 07:08:05 AM PDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [unknown] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [unknown] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [unknown] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # gpg: WARNING: The key's User ID is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20250926' of https://gitlab.com/pm215/qemu: (44 commits) target/arm: Implement ID_AA64PFR2_EL1 target/arm: Move ID register field defs to cpu-features.h target/arm: Trace vCPU reset call target/arm: Trace emulated firmware reset call target/arm: Convert power control DPRINTF() uses to trace events target/arm: Replace magic GIC values by proper definitions target/arm: Remove define_arm_vh_e2h_redirects_aliases target/arm: Rename some cpreg to their aarch64 names target/arm: Redirect VHE FOO_EL12 to FOO_EL1 during translation target/arm: Redirect VHE FOO_EL1 -> FOO_EL2 during translation target/arm: Split out redirect_cpreg target/arm: Rename TBFLAG_A64_NV2_MEM_E20 with *_E2H target/arm: Move endianness fixup for 32-bit registers target/arm: Move writeback of CP_ANY fields target/arm: Move alias setting for wildcards target/arm: Remove name argument to alloc_cpreg target/arm: Hoist the allocation of ARMCPRegInfo target/arm: Split out alloc_cpreg target/arm: Add key parameter to add_cpreg_to_hashtable target/arm: Move cpreg elimination to define_one_arm_cp_reg ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * target/arm: Implement ID_AA64PFR2_EL1Peter Maydell2025-09-266-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently we define the ID_AA64PFR2_EL1 encoding as reserved (with the required RAZ behaviour for unassigned system registers in the ID register encoding space). Newer architecture versions start to define fields in this ID register, so define the appropriate constants and implement it as an ID register backed by a field in cpu->isar. Since none of our CPUs set that isar field to non-zero, there is no behavioural change here (other than the name exposed to the user via the gdbstub), but this paves the way for implementing the new features that use fields in this register. The fields here are the ones documented in rev L.b of the Arm ARM. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
| * target/arm: Move ID register field defs to cpu-features.hPeter Maydell2025-09-263-410/+412
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently we define constants for the ID register fields in cpu.h. This means they're defined for a lot more code in QEMU than actually needs them. Move them to cpu-features.h, which is where we define the feature functions that test fields in these registers. There's only one place where we need to use some of these macro definitions that we weren't already including cpu-features.h: linux-user/arm/target_proc.h. Otherwise this patch is a pure movement of code from one file to the other. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
| * target/arm: Trace vCPU reset callPhilippe Mathieu-Daudé2025-09-262-0/+3
| | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Trace emulated firmware reset callPhilippe Mathieu-Daudé2025-09-262-0/+7
| | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Convert power control DPRINTF() uses to trace eventsPhilippe Mathieu-Daudé2025-09-262-18/+14
| | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Replace magic GIC values by proper definitionsPhilippe Mathieu-Daudé2025-09-261-2/+2
| | | | | | | | | | | | | | | | | | Prefer the FIELD_DP64() macro and self-describing GIC definitions over magic values. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Remove define_arm_vh_e2h_redirects_aliasesRichard Henderson2025-09-252-142/+107
| | | | | | | | | | | | | | | | | | | | | | | | Populate vhe_redir_to_{el2,el01} on each ARMCPRegInfo. Clear the fields within add_cpreg_to_hashtable_aa32. Create the FOO_EL12 cpreg within add_cpreg_to_hashtable_aa64; add ARM_CP_NO_RAW. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Rename some cpreg to their aarch64 namesRichard Henderson2025-09-251-11/+11
| | | | | | | | | | | | | | | | | | | | Rename those registers which will have FOO_EL12 aliases. Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Redirect VHE FOO_EL12 to FOO_EL1 during translationRichard Henderson2025-09-254-68/+25
| | | | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> [PMM: expanded a comment slightly] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Redirect VHE FOO_EL1 -> FOO_EL2 during translationRichard Henderson2025-09-254-52/+21
| | | | | | | | | | | | | | | | Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Split out redirect_cpregRichard Henderson2025-09-251-3/+14
| | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Rename TBFLAG_A64_NV2_MEM_E20 with *_E2HRichard Henderson2025-09-254-6/+10
| | | | | | | | | | | | | | | | | | | | Install e2h in tbflags and compute nv2_mem_e20 from that in aarch64_tr_init_disas_context. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Move endianness fixup for 32-bit registersRichard Henderson2025-09-251-5/+12
| | | | | | | | | | | | | | | | | | | | Move the test outside of the banked register block, and repeat the AA32 test. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Move writeback of CP_ANY fieldsRichard Henderson2025-09-251-26/+26
| | | | | | | | | | | | | | | | | | | | | | Move the writeback of cp, crm, opc1, opc2 to define_one_arm_cp_reg, which means we don't have to pass all those parameters down to subroutines. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Move alias setting for wildcardsRichard Henderson2025-09-251-10/+12
| | | | | | | | | | | | | | | | | | | | | | | | Move this test from add_cpreg_to_hashtable to define_one_arm_cp_reg_with_opaque, where we can also simplify it based on the loop variables. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> [PMM: adjusted placement of comma in a comment] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Remove name argument to alloc_cpregRichard Henderson2025-09-251-6/+6
| | | | | | | | | | | | | | | | | | All callers now pass in->name, so take the value from there. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Hoist the allocation of ARMCPRegInfoRichard Henderson2025-09-251-49/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Pass in a newly allocated structure, rather than having to dance around allocation of the name and the structure. Since we no longer have two copies of the structure handy within add_cpreg_to_hashtable, delay the writeback of concrete values over wildcards until we're done querying the wildcards. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Split out alloc_cpregRichard Henderson2025-09-251-6/+23
| | | | | | | | | | | | | | | | | | Include provision for a name suffix. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Add key parameter to add_cpreg_to_hashtableRichard Henderson2025-09-251-20/+20
| | | | | | | | | | | | | | | | | | | | | | Hoist the computation of key into the caller, where state is a known constant. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> [PMM: added comment about CRN key field increment] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Move cpreg elimination to define_one_arm_cp_regRichard Henderson2025-09-251-59/+64
| | | | | | | | | | | | | | | | | | | | Eliminate unused registers earlier, so that by the time we arrive in add_cpreg_to_hashtable we never skip. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Move cp processing to define_one_arm_cp_regRichard Henderson2025-09-251-31/+22
| | | | | | | | | | | | | | | | | | | | Processing of cp was split between add_cpreg_to_hashtable and define_one_arm_cp_reg. Unify it all to the top-level function. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Improve asserts in define_one_arm_cp_regRichard Henderson2025-09-251-5/+10
| | | | | | | | | | | | | | | | | | | | | | Reject ARM_CP_64BIT with ARM_CP_STATE_BOTH, because encoding constrains prevent it from working. Remove some extra parens; distribute ! across && to simplify. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Split out add_cpreg_to_hashtable_aa{32, 64}Richard Henderson2025-09-251-71/+76
| | | | | | | | | | | | | | | | | | | | | | | | The nesting level for the inner loop of define_one_arm_cp_reg was overly deep. Split out that code into two functions, for the AArch32 and AArch64 paths separately. Simplify the innermost loop to a switch statement over r->state. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Reorder ENCODE_AA64_CP_REG argumentsRichard Henderson2025-09-254-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The order of the parameters in the Arm ARM is op0, op1, crn, crm, op2 Reorder the arguments of ENCODE_AA64_CP_REG to match. Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Remove cp argument to ENCODE_AA64_CP_REGRichard Henderson2025-09-255-18/+10
| | | | | | | | | | | | | | | | | | | | | | | | All invocations were required to pass the same value, CP_REG_ARM64_SYSREG_CP. Bake that in to the result directly. Remove CP_REG_ARM64_SYSREG_CP as unused. Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Convert init_cpreg_list to g_hash_table_foreachRichard Henderson2025-09-251-33/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adjust count_cpreg and add_cpreg_to_list to be used with g_hash_table_foreach instead of g_list_foreach. In this way we have the ARMCPRegInfo pointer directly rather than having to look it up from the key. Delay the sorting of the cpreg_indexes until after add_cpreg_to_list. This allows us to sort the data that we actually care about, the kvm id, as computed within add_cpreg_to_list, instead of having to repeatedly compute the kvm id within cpreg_key_compare. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Rename CP_REG_AA32_NS_{SHIFT,MASK}Richard Henderson2025-09-251-4/+4
| | | | | | | | | | | | | | | | | | | | Rename from CP_REG_NS_* to emphasize this is specific to AArch32. Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Add CP_REG_AA32_64BIT_{SHIFT,MASK}Richard Henderson2025-09-251-5/+10
| | | | | | | | | | | | | | | | | | | | Give a name to the bit we're already using. Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Replace cpreg_field_is_64bit with cpreg_field_typeRichard Henderson2025-09-253-11/+24
| | | | | | | | | | | | | | | | | | | | Prepare for 128-bit fields by using a better query api. Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Restrict the scope of CPREG_FIELD32, CPREG_FIELD64Richard Henderson2025-09-252-9/+12
| | | | | | | | | | | | | | | | Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Drop define_one_arm_cp_reg_with_opaqueRichard Henderson2025-09-253-51/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | The last use of this interface was removed in 603bc048a27f ("hw/arm: Remove pxa2xx_pic"). As the comment in gicv3 stated, keeping pointer references to cpregs has SMP issues, so avoid future temptation by removing the interface. Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Rename all ARMCPRegInfo from opaque to riRichard Henderson2025-09-252-8/+8
| | | | | | | | | | | | | | | | | | | | These pointers are no opaque, they have a specific type. Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Use raw_write in cp_reg_resetRichard Henderson2025-09-251-8/+2
| | | | | | | | | | | | | | | | | | | | Reduce the places that know about field types by 1. Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm/hvf: Use raw_read, raw_write to accessRichard Henderson2025-09-251-2/+2
| | | | | | | | | | | | | | | | | | Reduce the places that know about field types by 2. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm/hvf: Sort the cpreg_indexes arrayRichard Henderson2025-09-251-0/+3
| | | | | | | | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm/hvf: Replace hvf_sreg_match with hvf_sreg_listRichard Henderson2025-09-251-30/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change hvf_get_registers and hvf_put_registers to iterate over cpregs_indexes instead of hvf_sreg_match. This lets us drop the cp_idx member of hvf_sreg_match, which leaves only one member in the struct. Replace the struct with a const array. Instead of int, use the proper enum type: hv_sys_reg_t. Rename from hvf_sreg_match to hvf_sreg_list because there is no longer any matching going on. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm/hvf: Remove hvf_sreg_match.keyRichard Henderson2025-09-251-16/+19
| | | | | | | | | | | | | | | | | | Use conversion functions instead of table lookup. Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm/hvf: Add KVMID_TO_HVF, HVF_TO_KVMIDRichard Henderson2025-09-251-0/+20
| | | | | | | | | | | | | | | | | | | | | | Conversion between KVM system registers ids and the HVF system register ids is trivial. Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm/hvf: Reorder DEF_SYSREG argumentsRichard Henderson2025-09-252-130/+130
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The order of the parameters in the Arm ARM is op0, op1, crn, crm, op2 Reorder the arguments of DEF_SYSREG to match. Mechanical change to sysreg.c.inc using sed 's/\([^,]*\),\([^,]*\),\([^,]*\),\([^,]*\),\([^,]*\)/\1,\4,\5,\2,\3/' Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm/hvf: Split out sysreg.c.incRichard Henderson2025-09-252-141/+152
| | | | | | | | | | | | | | | | | | | | Move the list of supported sysregs to a reuseable file. Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Move compare_u64 to helper.cRichard Henderson2025-09-253-11/+14
| | | | | | | | | | | | | | | | | | | | We will use this function beyond kvm.c. Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/arm: Introduce KVMID_AA64_SYS_REG64Richard Henderson2025-09-251-0/+11
| | | | | | | | | | | | | | | | | | | | Allow us to create kvm ids directly, rather than going through ENCODE_AA64_CP_REG + cpreg_to_kvm_id. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * net/passt: Fix build failure due to missing GIO dependencyLaurent Vivier2025-09-251-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The passt networking backend uses functions from the GIO library, such as g_subprocess_launcher_new(), to manage its daemon process. So, building with passt enabled requires GIO to be available. If we enable passt and disable gio the build fails during linkage with undefined reference errors: /usr/bin/ld: libsystem.a.p/net_passt.c.o: in function `net_passt_start_daemon': net/passt.c:250: undefined reference to `g_subprocess_launcher_new' /usr/bin/ld: net/passt.c:251: undefined reference to `g_subprocess_launcher_take_fd' /usr/bin/ld: net/passt.c:253: undefined reference to `g_subprocess_launcher_spawnv' /usr/bin/ld: net/passt.c:256: undefined reference to `g_object_unref' /usr/bin/ld: net/passt.c:263: undefined reference to `g_subprocess_wait' /usr/bin/ld: net/passt.c:268: undefined reference to `g_subprocess_get_if_exited' /usr/bin/ld: libsystem.a.p/net_passt.c.o: in function `glib_autoptr_clear_GSubprocess': /usr/include/glib-2.0/gio/gio-autocleanups.h:132: undefined reference to `g_object_unref' /usr/bin/ld: libsystem.a.p/net_passt.c.o: in function `net_passt_start_daemon': net/passt.c:269: undefined reference to `g_subprocess_get_exit_status' Fix this by adding an explicit weson dependency on GIO for the passt option. The existing dependency on linux is kept because passt is only available on this OS. Cc: qemu-stable@nongnu.org Fixes: 854ee02b222 ("net: Add passt network backend") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3121 Reported-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Laurent Vivier <lvivier@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/usb/hcd-uhci: don't assert for SETUP to non-0 endpointPeter Maydell2025-09-251-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the guest feeds invalid data to the UHCI controller, we can assert: qemu-system-x86_64: ../../hw/usb/core.c:744: usb_ep_get: Assertion `pid == USB_TOKEN_IN || pid == USB_TOKEN_OUT' failed. (see issue 2548 for the repro case). This happens because the guest attempts USB_TOKEN_SETUP to an endpoint other than 0, which is not valid. The controller code doesn't catch this guest error, so instead we hit the assertion in the USB core code. Catch the case of SETUP to non-zero endpoint, and treat it as a fatal error in the TD, in the same way we do for an invalid PID value in the TD. This is the UHCI equivalent of the same bug in OHCI that we fixed in commit 3c3c233677 ("hw/usb/hcd-ohci: Fix #1510, #303: pid not IN or OUT"). This bug has been tracked as CVE-2024-8354. Cc: qemu-stable@nongnu.org Fixes: https://gitlab.com/qemu-project/qemu/-/issues/2548 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru>
* | Merge tag 'pull-10.2-maintainer-260925-1' of https://gitlab.com/stsquad/qemu ↵Richard Henderson2025-09-2620-148/+1538
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging September maintainer updates (scripts, semihosting, plugins) - new gitlab-failure-analysis script - tweak checkpath to ignore license in removed lines - refactor semihosting to build once - add explicit assert to execlog for coverity - new uftrace plugin # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEEZoWumedRZ7yvyN81+9DbCVqeKkQFAmjWWJYACgkQ+9DbCVqe # KkS1sgf+LsP0jsc1wKhzBhO4WarXXacWCDxK22riJ3aolm+gJ+b0WI4ds18A0e3R # z/J8VJVxBZ+6Hid+tOCQwfZ+Hb1p9IofzBdZryGUvwguviNdlpEChhXXnoZkicym # aGcC/jYRkhTx42dKRdZrSzPd3ccipqop9RvGx57bjCSBAEHYNz679p4z91kNR5a9 # UfcCzIQHbBUPZo0F9gQkNnBrjsJQhvF+gXPmmsmBI1pby6gNRQvFshrTQ1C32VpL # VgXNc9cZ6vaREWlgb6izNjsMP7cYTMH2Ppxty/FyEMg7GTfWRjI6Ec8fJKjPFtKr # ZbCNNAeJ9uLK6pJfTk2YxYabxx3JuQ== # =cR9e # -----END PGP SIGNATURE----- # gpg: Signature made Fri 26 Sep 2025 02:10:46 AM PDT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * tag 'pull-10.2-maintainer-260925-1' of https://gitlab.com/stsquad/qemu: (24 commits) contrib/plugins/uftrace: add documentation contrib/plugins/uftrace_symbols.py contrib/plugins/uftrace: implement x64 support contrib/plugins/uftrace: generate additional files for uftrace contrib/plugins/uftrace: implement privilege level tracing contrib/plugins/uftrace: implement tracing contrib/plugins/uftrace: track callstack contrib/plugins/uftrace: define cpu operations and implement aarch64 contrib/plugins/uftrace: skeleton file contrib/plugins/execlog: Explicitly check for qemu_plugin_read_register() failure semihosting/arm-compat-semi: compile once in system and per target for user mode semihosting/arm-compat-semi: remove dependency on cpu.h semihosting/arm-compat-semi: eradicate target_long semihosting/arm-compat-semi: replace target_ulong semihosting/arm-compat-semi: eradicate sizeof(target_ulong) include/semihosting/common-semi: extract common_semi API target/{arm, riscv}/common-semi-target: eradicate target_ulong target/riscv/common-semi-target: remove sizeof(target_ulong) semihosting/arm-compat-semi: change common_semi_sys_exit_extended semihosting/guestfd: compile once for system/user ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>