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2025-07-11target/s390x: Expose s390_count_running_cpus() methodPhilippe Mathieu-Daudé2-1/+2
In order to simplify the next commit where s390_count_running_cpus() is split out of s390_cpu_halt(), make its prototype public as a preliminary step. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250708095746.12697-3-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-07-11target/s390x: Remove unused s390_cpu_[un]halt() user stubsPhilippe Mathieu-Daudé1-10/+0
Since commit da944885469 ("target/s390x: make helper.c sysemu-only") target/s390x/helper.c is only built for system mode, so s390_cpu_halt() and s390_cpu_unhalt() are never called from user mode. Fixes: da944885469 ("target/s390x: make helper.c sysemu-only") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250708095746.12697-2-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-07-11tests/functional/test_ppc_bamboo: Replace broken link with working assetsThomas Huth1-15/+19
The old image that we used for testing the bamboo machine has disappeared from the internet. Fortunately there is another kernel + initrd provided by Cédric that can be used for testing this machine, too. Reported-by: Stefan Hajnoczi <stefanha@gmail.com> Suggested-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-ID: <20250707184736.88660-1-thuth@redhat.com>
2025-07-11tests/functional: Add dependency to the keymap_targetsThomas Huth1-1/+1
When doing a "configure" in a an empty build directory, followed by a "make check" without a normal build in between, the vnc functional test currently fails since the keymaps have not been built yet. Thus add a dependency to the keymap_targets here to make sure that the keymaps are built before running the functional tests. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-ID: <20250701104827.363904-1-thuth@redhat.com>
2025-07-11pc-bios: Update the s390 bios images with the pxelinux.cfg loadparm changesThomas Huth1-0/+0
This new s390-ccw.img binary contains the addition of the loadparm feature to the pxelinux.cfg network booting code. Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-07-11pc-bios/s390-ccw: link staticallySertonix1-1/+1
Adding -pie to LDFLAGS caused s390-ccw.img to become dynamically linked. By using -static-pie it will be linked statically like other bios. This ensures that the build output doesn't change depending on the default dynamic loader path of the toolchain. Fixes: d884c86dcd3b ("s390/bios: Make the s390-ccw.img relocatable") Signed-off-by: Sertonix <sertonix@posteo.net> Message-ID: <DAJ1QOSAP9LS.342SQSM0UZU80@posteo.net> Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-07-11tests/functional: Add a test for s390x pxelinux.cfg network bootingThomas Huth3-0/+121
Check the various ways of booting a kernel via pxelinux.cfg file, e.g. by specifying the config file name via the MAC address or the UUID of the guest. Also check whether we can successfully load an alternate kernel via the "loadparm" parameter here and whether the boot menu shows up with "-boot menu=on". Reviewed-by: Jared Rossi <jrossi@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-ID: <20250709083443.41574-6-thuth@redhat.com>
2025-07-11pc-bios/s390-ccw: Add a boot menu for booting via pxelinux.cfgThomas Huth1-0/+26
Show a simple boot menu for pxelinux.cfg, too, if the user requested it. Reviewed-by: Jared Rossi <jrossi@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-ID: <20250709083443.41574-5-thuth@redhat.com>
2025-07-11pc-bios/s390-ccw: Make get_boot_index() from menu.c globalThomas Huth2-3/+4
We are going to reuse this function for selecting an entry from the pxelinux.cfg menu, so rename this function with a "menu_" prefix and make it available globally. Reviewed-by: Jared Rossi <jrossi@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-ID: <20250709083443.41574-4-thuth@redhat.com>
2025-07-11pc-bios/s390-ccw: Allow up to 31 entries for pxelinux.cfgThomas Huth1-6/+4
We're going to support a menu for the pxelinux.cfg code, and to be able to reuse some functionality from menu.c, we should align the maximum amount of possible entries with the MAX_BOOT_ENTRIES constant that is used there. Thus replace MAX_PXELINUX_ENTRIES with MAX_BOOT_ENTRIES. Reviewed-by: Jared Rossi <jrossi@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-ID: <20250709083443.41574-3-thuth@redhat.com>
2025-07-11pc-bios/s390-ccw: Allow to select a different pxelinux.cfg entry via loadparmThomas Huth1-8/+24
Since we're linking the network booting code into the main firmware binary nowadays, we can support the "loadparm" parameter now quite easily for pxelinux.cfg config files that contain multiple entries. Reviewed-by: Jared Rossi <jrossi@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-ID: <20250709083443.41574-2-thuth@redhat.com>
2025-07-11hw/s390x/s390-pci-bus.c: Use g_assert_not_reached() in functions taking an ettPeter Maydell1-12/+14
The s390-pci-bus.c code, Coverity complains about a possible overflow because get_table_index() can return -1 if the ett value passed in is not one of the three permitted ZPCI_ETT_PT, ZPCI_ETT_ST, ZPCI_ETT_RT, but the caller in table_translate() doesn't check this and instead uses the return value directly in a calculation of the guest address to read from. In fact this case cannot happen, because: * get_table_index() is called only from table_translate() * the only caller of table_translate() loops through the ett values in the order RT, ST, PT until table_translate() returns 0 * table_translate() will return 0 for the error cases and when translate_iscomplete() returns true * translate_iscomplete() is always true for ZPCI_ETT_PT So table_translate() is always called with a valid ett value. Instead of having the various functions called from table_translate() return a default or dummy value when the ett argument is out of range, use g_assert_not_reached() to indicate that this is impossible. Coverity: CID 1547609 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Matthew Rosato <mjrosato@linux.ibm.com> Reviewed-by: Halil Pasic <pasic@linux.ibm.com> Message-ID: <20250710161552.1287399-1-peter.maydell@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-07-11target/s390x/tcg: Use vaddr in s390_probe_access()Philippe Mathieu-Daudé1-5/+5
Commit 70ebd9ce1cb ("s390x/tcg: Fault-safe memset") passed vaddr type to access_prepare(), and commit b6c636f2cd6 ("s390x/tcg: Fault-safe memmove") to do_access_get_byte(), but declared S390Access::vaddr[1,2] as target_ulong. Directly declare these as vaddr type, and have s390_probe_access() use that type as argument. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250707171059.3064-3-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-07-11target/s390x/kvm: Use vaddr in find/insert_hw_breakpoint()Philippe Mathieu-Daudé1-2/+2
Since commit b8a6eb1862a both kvm_arch_insert_hw_breakpoint() and kvm_arch_remove_hw_breakpoint() use a vaddr type. Use the same type for the callees. Fixes: b8a6eb1862a ("sysemu/kvm: Use vaddr for kvm_arch_[insert|remove]_hw_breakpoint") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250707171059.3064-2-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-07-11target/loongarch: Remove unnecessary page size validity checkingBibo Mao1-17/+10
Page size of TLB entry comes from CSR STLBPS and pwcl register. With huge page, it is dir_base + dir_width from pwcl register. With normal page, it is field of PTBASE from pwcl register. So it is ok to check validity in function helper_ldpte() and function helper_csrwr_stlbps(). And it is unnecessary in tlb entry fill path. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
2025-07-11target/loongarch: Fix CSR STLBPS register write emulationBibo Mao1-0/+4
Function helper_csrwr_stlbps() is emulation with CSR STLBPS register write operation. However there is only parameter checking action, and no register updating action. Here update value of CSR_STLBPS when parameter passes to check. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
2025-07-11target/loongarch: Correct spelling in helper_csrwr_pwcl()Bibo Mao1-2/+2
There is small typo issue in function helper_csrwr_pwcl(), this patch corrects this issue. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
2025-07-11hw/intc/loongarch_extioi: Move unrealize function to common codeBibo Mao4-10/+10
Memory about LoongArchExtIOICommonState::cpu is allocated in common code, it had better be freed in common code also. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
2025-07-04linux-user/aarch64: Set hwcap bits for SME2p1/SVE2p1Richard Henderson1-0/+8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250704142112.1018902-108-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-04target/arm: Enable FEAT_SME2p1 on -cpu maxRichard Henderson2-2/+14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250704142112.1018902-107-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-04target/arm: Implement SME2 BFMOPA (non-widening)Peter Maydell4-0/+64
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250704142112.1018902-106-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-04target/arm: Implement FMOPA (non-widening) for fp16Peter Maydell4-0/+63
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250704142112.1018902-105-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-04target/arm: Support FPCR.AH in SME FMOPS, BFMOPSRichard Henderson4-33/+161
For non-widening, we can use float_muladd_negate_product, For widening, which uses dot-product, we need to handle the negation explicitly. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250704142112.1018902-104-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-04target/arm: Rename BFMOPA to BFMOPA_wPeter Maydell4-5/+5
Our current BFMOPA opcode pattern is the widening version of the insn. Rename it to BFMOPA_w, to make way for the non-widening version added in SME2. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250704142112.1018902-103-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-04target/arm: Rename FMOPA_h to FMOPA_w_hPeter Maydell4-6/+6
The pattern we currently have as FMOPA_h is the "widening" insn that takes fp16 inputs and produces single-precision outputs. This is unlike FMOPA_s and FMOPA_d, which are non-widening produce outputs the same size as their inputs. SME2 introduces a non-widening fp16 FMOPA operation; rename FMOPA_h to FMOPA_w_h (for 'widening'), so we can use FMOPA_h for the non-widening version, giving it a name in line with the other non-widening ops FMOPA_s and FMOPA_d. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250704142112.1018902-102-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-04target/arm: Implement LUTI2, LUTI4 for SME2/SME2p1Richard Henderson4-0/+210
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250704142112.1018902-101-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-04target/arm: Implement MOVAZ for SME2p1Richard Henderson4-11/+137
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250704142112.1018902-100-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-04target/arm: Implement LD1Q, ST1Q for SVE2p1Richard Henderson4-2/+62
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250704142112.1018902-99-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-04target/arm: Implement {LD, ST}[234]Q for SME2p1/SVE2p1Richard Henderson4-31/+156
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250704142112.1018902-98-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-04target/arm: Move ld1qq and st1qq primitives to sve_ldst_internal.hRichard Henderson2-38/+69
Move from sme_helper.c to the shared header. Add a comment noting the lack of atomicity. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250704142112.1018902-97-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-04target/arm: Implement {LD1, ST1}{W, D} (128-bit element) for SVE2p1Richard Henderson5-27/+183
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250704142112.1018902-96-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-04target/arm: Split the ST_zpri and ST_zprr patternsRichard Henderson1-8/+18
The msz > esz encodings are reserved, and some of them are about to be reused. Split these patterns so that the new insns do not overlap. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250704142112.1018902-95-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-04target/arm: Implement SME2 counted predicate register load/storeRichard Henderson4-0/+662
Implement the SVE2p1 consecutive register LD1/ST1, and the SME2 strided register LD1/ST1. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250704142112.1018902-94-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-04target/arm: Implement TBLQ, TBXQ for SME2p1/SVE2p1Richard Henderson4-0/+37
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250704142112.1018902-93-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-04target/arm: Implement ZIPQ, UZPQ for SME2p1/SVE2p1Richard Henderson4-1/+63
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250704142112.1018902-92-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-04target/arm: Implement PMOV for SME2p1/SVE2p1Richard Henderson5-0/+207
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250704142112.1018902-91-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-04target/arm: Implement EXTQ for SME2p1/SVE2p1Richard Henderson2-0/+51
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250704142112.1018902-90-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-04target/arm: Implement DUPQ for SME2p1/SVE2p1Richard Henderson2-0/+27
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250704142112.1018902-89-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-04target/arm: Implement CNTP (predicate as counter) for SME2/SVE2p1Richard Henderson4-1/+54
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250704142112.1018902-88-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-04target/arm: Implement BFMLSLB{L, T} for SME2/SVE2p1Richard Henderson2-0/+36
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250704142112.1018902-87-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-04target/arm: Implement FADDQV, F{MIN, MAX}{NM}QV for SVE2p1Richard Henderson4-27/+148
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250704142112.1018902-86-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-04target/arm: Implement ANDQV, ORQV, EORQV for SVE2p1Richard Henderson4-0/+65
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250704142112.1018902-85-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-04target/arm: Implement SME2 SELRichard Henderson4-0/+362
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250704142112.1018902-84-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-04target/arm: Implement SVE2p1 PEXTRichard Henderson5-0/+146
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250704142112.1018902-83-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-04target/arm: Implement {ADD, SMIN, SMAX, UMIN, UMAX}QV for SVE2p1Richard Henderson4-0/+113
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250704142112.1018902-82-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-04target/arm: Implement SVE2p1 PTRUE (predicate as counter)Richard Henderson2-0/+17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250704142112.1018902-81-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-04target/arm: Implement SVE2p1 WHILE (predicate as counter)Richard Henderson4-5/+84
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250704142112.1018902-80-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-04target/arm: Implement SVE2p1 WHILE (predicate pair)Richard Henderson4-4/+61
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250704142112.1018902-79-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-04target/arm: Enable PSEL for SVE2p1Richard Henderson1-1/+1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250704142112.1018902-78-richard.henderson@linaro.org This instruction is present in both SME(1) and SVE2.1 extensions. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-04target/arm: Split trans_WHILE to lt and gtRichard Henderson2-15/+12
Use TRANS_FEAT to select the correct predicate. Pass the helper and a boolean to do_WHILE. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250704142112.1018902-77-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>