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* target/arm: Enable FEAT_RME_GPC2 for -cpu max with x-rmeRichard Henderson2025-10-071-0/+1
| | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250926001134.295547-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/xlnx-versal-virt: add the xlnx-versal2-virt machineLuc Michel2025-10-071-7/+42
| | | | | | | | | | | | | | | | Add the Versal Gen 2 Virtual development machine embedding a versal2 SoC. This machine follows the same principle than the xlnx-versal-virt machine. It creates its own DTB and feeds it to the software payload. This way only implemented devices are exposed to the guest and the user does not need to provide a DTB. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-47-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* docs/system/arm/xlnx-versal-virt: add a note about dumpdtbLuc Michel2025-10-071-1/+7
| | | | | | | | | | | | Add a note in the DTB section explaining how to dump the generated DTB using the dumpdtb machine option. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-46-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* docs/system/arm/xlnx-versal-virt: update supported devicesLuc Michel2025-10-071-2/+5
| | | | | | | | | | | Update the list of supported devices in the Versal SoCs. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-45-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/xlnx-versal-virt: rename the machine to amd-versal-virtLuc Michel2025-10-071-11/+15
| | | | | | | | | | | | | | | To align with current branding and ensure coherency with the upcoming versal2 machine, rename the xlnx-versal-virt machine to amd-versal-virt. Keep an alias of the old name to the new one for command-line backward compatibility. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-42-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu ↵Richard Henderson2025-10-061-13/+7
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging virtio,pci,pc: features, fixes users can now control VM bit in smbios. vhost-user-device is now user-createable. intel_iommu now supports PRI virtio-net now supports GSO over UDP tunnel ghes now supports error injection amd iommu now supports dma remapping for vfio better error messages for virtio small fixes all over the place. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCgAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmji0s0PHG1zdEByZWRo # YXQuY29tAAoJECgfDbjSjVRpuH4H/09h70IqAWZGHIWKGmmGGtdKOj3g54KuI0Ss # mGECEsHvvBexOy670Qy8jdgXfaW4UuNui8BiOnJnGsBX8Y0dy+/yZori3KhkXkaY # D57Ap9agkpHem7Vw0zgNsAF2bzDdlzTiQ6ns5oDnSq8yt82onCb5WGkWTGkPs/jL # Gf8Jv+Ddcpt5SU4/hHPYC8pUhl7z4xPOOyl0Qp1GG21Pxf5v4sGFcWuGGB7UEPSQ # MjZeoM0rSnLDtNg18sGwD5RPLQs13TbtgsVwijI79c3w3rcSpPNhGR5OWkdRCIYF # 8A0Nhq0Yfo0ogTht7yt1QNPf/ktJkuoBuGVirvpDaix2tCBECes= # =Zvq/ # -----END PGP SIGNATURE----- # gpg: Signature made Sun 05 Oct 2025 01:19:25 PM PDT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [unknown] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [unknown] # gpg: WARNING: The key's User ID is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (75 commits) virtio: improve virtqueue mapping error messages pci: Fix wrong parameter passing to pci_device_get_iommu_bus_devfn() intel_iommu: Simplify caching mode check with VFIO device intel_iommu: Enable Enhanced Set Root Table Pointer Support (ESRTPS) vdpa-dev: add get_vhost() callback for vhost-vdpa device amd_iommu: HATDis/HATS=11 support intel-iommu: Move dma_translation to x86-iommu amd_iommu: Refactor amdvi_page_walk() to use common code for page walk amd_iommu: Do not assume passthrough translation when DTE[TV]=0 amd_iommu: Toggle address translation mode on devtab entry invalidation amd_iommu: Add dma-remap property to AMD vIOMMU device amd_iommu: Set all address spaces to use passthrough mode on reset amd_iommu: Toggle memory regions based on address translation mode amd_iommu: Invalidate address translations on INVALIDATE_IOMMU_ALL amd_iommu: Add replay callback amd_iommu: Unmap all address spaces under the AMD IOMMU on reset amd_iommu: Use iova_tree records to determine large page size on UNMAP amd_iommu: Sync shadow page tables on page invalidation amd_iommu: Add basic structure to support IOMMU notifier updates amd_iommu: Add a page walker to sync shadow page tables on invalidation ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * hw/virtio: rename vhost-user-device and make user creatableAlex Bennée2025-10-051-13/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We didn't make the device user creatable in the first place because we were worried users might get confused. Rename the device to make its nature as a test device even more explicit. While we are at it add a Kconfig variable so it can be skipped for those that want to thin out their build configuration even further. Acked-by: Stefano Garzarella <sgarzare@redhat.com> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-ID: <20250820195632.1956795-1-alex.bennee@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-ID: <20250901105948.982583-1-alex.bennee@linaro.org> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* | Add a feature for mapping a host unix socket to a guest tcp socketViktor Kurilko2025-10-051-1/+1
|/ | | | | | | | | | | This patch adds the ability to map a host unix socket to a guest tcp socket when using the slirp backend. This feature was added in libslirp version 4.7.0. A new syntax for unix socket: -hostfwd=unix:hostpath-[guestaddr]:guestport Signed-off-by: Viktor Kurilko <murlockkinght@gmail.com> Signed-off-by: Samuel Thibault <samuel.thibault@ens-lyon.org> Message-ID: <20250808143904.363907-1-murlockkinght@gmail.com>
* Merge tag 'pull-aspeed-20250929' of https://github.com/legoater/qemu into ↵Richard Henderson2025-09-291-0/+31
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging aspeed queue: * Introduce a new ASPEED OTP memory device model integrated with the Secure Boot Controller. It includes a new block device backend ('drive' property), is enabled for AST2600 SoCs and AST1030 SoCs. Functional tests are included * Changed "ast2700-evb" alias to point to the "ast2700a1-evb" machine * Introduce support for Aspeed PCIe host controller, including models for the PCIe Root Complex, Root Port, and PHY. Enabled for the AST2600 and AST2700 SoCs, and functional tests are included * Refactor Boot ROM support to improve code reuse across the different Aspeed machine. This is in preparation of vbootrom support in the ast2700fc machine * Improved Error Handling in the AST27x0-fc machine init functions # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmjauRoACgkQUaNDx8/7 # 7KGAxA//YdPPGf8vKhPeblUt0/3760GGhI17TBWJFVZP/aZYcIiE0oRxo5zH0Lne # YjwFKTtx7GXzbE2wqVCLSt/VPDAEMk6wZGwGvMbmeydssyNjbPuF79+EVYnFsUrQ # Zkm8YPf/qFcKYFxp8O5GTKedAu70AFDMkFwy2xuBRqE5v0RQJe20+EHaiEC8S+3a # z5PIZJ74J3m4d+h+BlIHoiPe7hwTiyQ8V4rrWKWupwqDBExZfgNGX0zGPZDOlwOo # bpV38gb0ugyG93/FJSXyXQqiiH5h+10CaSzc1QuytYtQXAM2qj60Kh86YruTsbLu # g3TUz+jOgDatTk/MhH8q/gtwDjmqcygGeybbMJZeCzhq1qLIFgJW2KwPNwj8eHCd # 7jZp6NT9GekVMB+FghApWjc63EozKveJ3wzyHE481GGF7TgvuVF1Km+dVHNPjpBz # pjXgIeKmDl0hmgGp3Se9S8B1ryWK3+KvuNoKe63UK/NMCkSXF3xTerkU1evJjIrp # B9Tus7kLRqbDGWPyprp1d7Jv6MKJ6sELKvGHlalMcnzo4vAvQu1RB5s1kYqsCGlY # 414Bc2v/YdkLxQGU6hCp1rABq3sIdWVzxRJ4c0XalRNZBkOmlsy1p5FaG5RXQdhz # Gm27nzDAWBeNmWD6Jjjj6VwWmqBbSO4M4mYVTMnTfEaO7y/l1d4= # =7BzG # -----END PGP SIGNATURE----- # gpg: Signature made Mon 29 Sep 2025 09:51:38 AM PDT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@redhat.com>" [full] # gpg: aka "Cédric Le Goater <clg@kaod.org>" [full] * tag 'pull-aspeed-20250929' of https://github.com/legoater/qemu: (32 commits) hw/arm/aspeed_ast27x0-fc: Make sub-init functions return bool with errp hw/arm/aspeed_ast27x0-fc: Drop dead return checks hw/arm/aspeed: Move aspeed_load_vbootrom to common SoC code hw/arm/aspeed: Move aspeed_install_boot_rom to common SoC code hw/arm/aspeed: Move write_boot_rom to common SoC code hw/arm/aspeed: Move aspeed_board_init_flashes() to common SoC code tests/functional/arm/test_aspeed_ast2600: Add PCIe and network test hw/arm/aspeed_ast27x0: Introduce 3 PCIe RCs for AST2700 hw/pci-host/aspeed: Disable Root Device and place Root Port at 00:00.0 to AST2700 hw/pci-host/aspeed: Add AST2700 PCIe config with dedicated H2X blocks hw/pci-host/aspeed: Add AST2700 PCIe PHY hw/arm/aspeed_ast2600: Add PCIe RC support (RC_H only) hw/arm/aspeed: Wire up PCIe devices in SoC model hw/pci-host/aspeed: Add MSI support and per-RC IOMMU address space hw/pci-host/aspeed: Add AST2600 PCIe Root Port and make address configurable hw/pci-host/aspeed: Add AST2600 PCIe Root Device support hw/pci-host/aspeed: Add AST2600 PCIe config space and host bridge hw/pci-host/aspeed: Add AST2600 PCIe PHY model hw/pci/pci_ids: Add PCI vendor ID for ASPEED tests/functional/arm: Add AST2600 boot test with generated OTP image ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * docs/system/arm/aspeed: Document OTP memory optionsKane-Chen-AS2025-09-291-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | Add documentation for the OTP memory module used by AST2600 and AST1030 SoCs, and describe options for using a pre-generated image or an internal buffer. Include example commands for configuration and image generation. Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250812094011.2617526-11-kane_chen@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
* | ppc/pnv: Introduce Power11 PowerNV machineAditya Gupta2025-09-281-4/+5
|/ | | | | | | | | | | | | | | | | | | | | | | The Powernv11 machine doesn't have XIVE & PHBs as of now XIVE2 interface and PHB5 added in later patches to Powernv11 machine Also add mention of Power11 to powernv documentation Note: A difference from P10's and P11's machine_class_init is, in P11 different number of PHBs cannot be used on the command line, ie. the following line does NOT exist in pnv_machine_power11_class_init, which existed in case of Power10: machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com> Tested-by: Amit Machhiwal <amachhiw@linux.ibm.com> Tested-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20250925173049.891406-3-adityag@linux.ibm.com Message-ID: <20250925173049.891406-3-adityag@linux.ibm.com>
* docs: use the pyvenv version of MesonPaolo Bonzini2025-09-221-1/+1
| | | | | | | | | | | The version in the system might be too old for QEMU; this will be especially true if Rust is going to be enabled by default. Adjust the docs to suggest using pyvenv/bin/meson, which is in fact what the "make" wrappers will be running internally. Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target/arm: Implement FEAT_ATS1ARichard Henderson2025-09-161-0/+1
| | | | | | | | | Implement FEAT_ATS1A and enable for -cpu max. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250830054128.448363-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/mips: Remove mipssim machinePhilippe Mathieu-Daudé2025-09-021-11/+0
| | | | | | | | | | | | The "mipssim" machine is deprecated since commit facfc943cb9 ("hw/mips: Mark the "mipssim" machine as deprecated"), released in v10.0; time to remove. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Ján Tomko <jtomko@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20250828143800.49842-2-philmd@linaro.org>
* target/arm: Enable FEAT_LSE128 for -cpu maxRichard Henderson2025-08-301-0/+1
| | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20250815122653.701782-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Enable FEAT_CSSC for -cpu maxRichard Henderson2025-08-301-0/+1
| | | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20250803014019.416797-7-richard.henderson@linaro.org [PMM: rebased to handle linux-user elfload.c refactor] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Implement FEAT_TCR2 and enable with -cpu maxGustavo Romero2025-08-301-0/+1
| | | | | | | | | | | | | | | | Add FEAT_TCR2, which introduces the TCR2_EL1 and TCR2_EL2 registers. These registers are extensions of the TCR_ELx registers and provide top-level control of the EL10 and EL20 translation regimes. Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250727074202.83141-5-richard.henderson@linaro.org Message-ID: <20250711140828.1714666-5-gustavo.romero@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [rth: Remove FEAT_MEC code; handle SCR and HCRX enable bits.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Implement FEAT_SCTLR2 and enable with -cpu maxGustavo Romero2025-08-301-0/+1
| | | | | | | | | | | | | | | Add FEAT_SCTLR2, which introduces the SCTLR2_EL1, SCTLR2_EL2, and SCTLR2_EL3 registers. These registers are extensions of the SCTLR_ELx ones. Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250727074202.83141-4-richard.henderson@linaro.org Message-ID: <20250711140828.1714666-4-gustavo.romero@linaro.org> [rth: Remove FEAT_MEC code; handle SCR and HCRX enable bits.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* docs/system: reword the TAP notes to remove tarball refAlex Bennée2025-07-261-5/+11
| | | | | | | | | | We don't ship the tarball and users should generally look to the distribution specific packaging. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/560 Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-ID: <20250725154517.3523095-3-alex.bennee@linaro.org>
* docs: Fix Aspeed titleCédric Le Goater2025-07-211-0/+1
| | | | | | | | | | | | | | commit ad8e0e8a0088 removed the "======" underlining the file title which broke documentation rendering. Add it back. Fixes: ad8e0e8a0088 ("docs: add support for gb200-bmc") Cc: Ed Tanous <etanous@nvidia.com> Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Ed Tanous <etanous@nvidia.com> Message-id: 20250715061904.97540-1-clg@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Merge tag 'pull-10.1-rc0-maintainer-140725-1' of ↵Stefan Hajnoczi2025-07-155-65/+77
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.com/stsquad/qemu into staging maintainer updates (gitlab, plugins, gdbstub, docs) - update check-units script to take -n <top> argument - fix execlog plugin to handle tab separators - add gdb XML file for alpha - add gdb XML file for sparc64 - use :kbd: in docs to highlight key sequences - clean up rst formatting in virtio-net-failover docs # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEEZoWumedRZ7yvyN81+9DbCVqeKkQFAmh0374ACgkQ+9DbCVqe # KkR0gQf/a9Au455+OWEhG3uLGkMZZaFM6QJv8W3wBBZoRg59LMXkUIhEtyVfdmt5 # SDyA79nw1G0iP2qlKQV02R++CrBHMJILtYOMoLTbkWV9Lft4h+uPC27SE17DkNPS # 4b4TchlJ3DpOFi0XmYZuIwH/8CPpTdVCLcA5zEXT0Q8nKjk0JsGiOQxoHH+p3ad5 # +mgvlmITDpU88OCilDYgmrD5iSe/WLzwszV9D6JTfQakfM7J9G87sj4iMK+En+iu # 0rsRBk2gwahy4cfqaiaELTtarqadM1TaNwaRvt6vun+Hp12pypDhogG1Mh5e2eCB # /nFwjcswRRk+kd26993AiK8Soomwiw== # =Md3/ # -----END PGP SIGNATURE----- # gpg: Signature made Mon 14 Jul 2025 06:45:18 EDT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * tag 'pull-10.1-rc0-maintainer-140725-1' of https://gitlab.com/stsquad/qemu: gdbstub: add the GDB register XML files for sparc64. docs/system: clean-up formatting of virtio-net-failover docs: use :kbd: role in sphinx docs plugins: fix inclusion of user-mode APIs target/alpha: Add GDB XML feature file contrib/plugins/execlog: Add tab to the separator search of insn_disas gitlab: add -n option to check-units script gitlab: use argparse in check-units script Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * docs/system: clean-up formatting of virtio-net-failoverAlex Bennée2025-07-141-23/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We didn't clean-up the rst formatting when we moved this into the docs so lets do that now: - un-indent the usage/hotplug/migration paragraphs - properly wrap the command line fragments in code-block - highlight parameters in text with ``double quotes`` No changes to the actual text. Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-ID: <20250710104531.3099313-8-alex.bennee@linaro.org>
| * docs: use :kbd: role in sphinx docsManos Pitsidianakis2025-07-144-42/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sphinx supports the :kbd: role for notating keyboard input. They get formatted as <kbd> HTML elements in the readthedocs theme we currently use for Sphinx. Besides the better visual formatting, it also helps with accessibility as screen readers can announce the semantics of the <kbd> element to the user. Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Message-ID: <20250709-docs_rst_improvements-v2-1-cb5096ad0022@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-ID: <20250710104531.3099313-7-alex.bennee@linaro.org>
* | Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingStefan Hajnoczi2025-07-143-0/+176
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * rust: miscellaneous fixes * rust: qemu-api-macros: cleanup and add unit tests for TryInto * rust: log: implement io::Write, avoid memory allocations when logging constant strings * target/i386: fix usage of properties whenever accelerators change the default (e.g. vendor) * target/i386: add support for TDVMCALL_SETUP_EVENT_NOTIFY_INTERRUPT * target/i386: add support for booting an SEV VM from an IGVM file * target/i386: unify cache model descriptions between CPUID 2, CPUID 4 and AMD specific CPUID 0x80000006 * target/i386: introduce cache models for recent Intel CPU models * target/i386: mark some 0x80000000-0x80000008 bits as reserved on Intel * target/i386: cleanups # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCgAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmh0v+sUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroOQUQf8CTsCnl2xYrnrkVfSVj6kuAE+JYD6 # oLSXsOEG4yrVknuhwIfVsqNScmleJCdz85ej7CZxy3vzzgjLfmy7nwifKEIKku7E # XO/Q3HbB898MnzqceQRmwe1AzELoj1Lave215CPhUBo60LCRPwaIZsiHprnNZgXi # TyHlmywDVRjyFLtKkx3El0dnLAhFqPWeGh81CD5lPLZZJ+Wt2FuAw2zqSOGB2ztM # FkJmunFJiaTItjyCN/uNvBSbDKecAHgCXvSCVNG3+I4U2R0gK1lcwm3TRo7yKia+ # HUHGa3UEXoIqlRfXdX6zuc8tW1/u6SPv+8WX53t204PAeSWDUrtIe9jZ4A== # =y4/a # -----END PGP SIGNATURE----- # gpg: Signature made Mon 14 Jul 2025 04:29:31 EDT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (77 commits) i386/cpu: Honor maximum value for CPUID.8000001DH.EAX[25:14] i386/cpu: Fix overflow of cache topology fields in CPUID.04H i386/cpu: Fix cpu number overflow in CPUID.01H.EBX[23:16] i386/cpu: Fix number of addressable IDs field for CPUID.01H.EBX[23:16] i386/cpu: Reorder CPUID leaves in cpu_x86_cpuid() tests/vm: bump FreeBSD image to 14.3 tests/functional: test_x86_cpu_model_versions: remove dead tests i386/cpu: Mark CPUID 0x80000008 ECX bits[0:7] & [12:15] as reserved for Intel/Zhaoxin i386/cpu: Mark CPUID 0x80000007[EBX] as reserved for Intel i386/cpu: Mark EBX/ECX/EDX in CPUID 0x80000000 leaf as reserved for Intel i386/cpu: Enable 0x1f leaf for YongFeng by default i386/cpu: Enable 0x1f leaf for SapphireRapids by default i386/cpu: Enable 0x1f leaf for GraniteRapids by default i386/cpu: Enable 0x1f leaf for SierraForest by default i386/cpu: Enable 0x1f leaf for SierraForest by default i386/cpu: Add a "x-force-cpuid-0x1f" property i386/cpu: Introduce cache model for YongFeng i386/cpu: Introduce cache model for SapphireRapids i386/cpu: Introduce cache model for GraniteRapids i386/cpu: Introduce cache model for SierraForest ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * | docs/system: Add documentation on support for IGVMRoy Hopkins2025-07-123-0/+176
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IGVM support has been implemented for Confidential Guests that support AMD SEV and AMD SEV-ES. Add some documentation that gives some background on the IGVM format and how to use it to configure a confidential guest. Signed-off-by: Roy Hopkins <roy.hopkins@randomman.co.uk> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Reviewed-by: Pankaj Gupta <pankaj.gupta@amd.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Gerd Hoffman <kraxel@redhat.com> Reviewed-by: Ani Sinha <anisinha@redhat.com> Link: https://lore.kernel.org/r/b4dc920a30717e19cd79bbbe2cc769f3b9ff3d37.1751554099.git.roy.hopkins@randomman.co.uk Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | | Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into stagingStefan Hajnoczi2025-07-141-2/+48
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCAAdFiEEIV1G9IJGaJ7HfzVi7wSWWzmNYhEFAmh0lXsACgkQ7wSWWzmN # YhGvVwf+OxTtnr84VdsEckqNVuzVkMHk3PAuSlxpvfjHXnwwo5Efto9lA4h4BUSX # As9sYpF3qXZdh95QYB/49CvVdizsI/KW1wPEx4ryVqCi7kcdOrzNB/MMMXBrrJE+ # 86xtc2a53CHHcctUIvkBr/GVzhay/gm6VHjnPEB/B0Tv+rTKpIBr/nJzVlG+8uX9 # O/XRI0aqnCPlsWDQFR2TbyE4TSSmTw5oXru0I12tPfxt2ed6b+izKubHmqgeLCyH # ne+qEy2ds40eBZ4YMDDIsxYKY8RlWIdUY0Dnz6wSjC00BNo5yLu7cirL0Ozd6AsI # pK5eqQGZGGQIGV/KD+M7WwKWVltBJg== # =rS9w # -----END PGP SIGNATURE----- # gpg: Signature made Mon 14 Jul 2025 01:28:27 EDT # gpg: using RSA key 215D46F48246689EC77F3562EF04965B398D6211 # gpg: Good signature from "Jason Wang (Jason Wang on RedHat) <jasowang@redhat.com>" [full] # Primary key fingerprint: 215D 46F4 8246 689E C77F 3562 EF04 965B 398D 6211 * tag 'net-pull-request' of https://github.com/jasowang/qemu: net/passt: Implement vhost-user backend support net: Add passt network backend net: Add is_vhost_user flag to vhost_net struct net: Allow network backends to advertise max TX queue size net: Add save_acked_features callback to vhost_net net: Add get_acked_features callback to VhostNetOptions net: Consolidate vhost feature bits into vhost_net structure net: Add get_vhost_net callback to NetClientInfo vhost_net: Rename vhost_set_vring_enable() for clarity net: Define net_client_set_link() net: Refactor stream logic for reuse in '-net passt' virtio-net: Add queues for RSS during migration net: fix buffer overflow in af_xdp_umem_create() Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * | | net/passt: Implement vhost-user backend supportLaurent Vivier2025-07-141-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds support for the vhost-user interface to the passt network backend, enabling high-performance, accelerated networking for guests using passt. The passt backend can now operate in a vhost-user mode, where it communicates with the guest's virtio-net device over a socket pair using the vhost-user protocol. This offloads the datapath from the main QEMU loop, significantly improving network performance. When the vhost-user=on option is used with -netdev passt, the new vhost initialization path is taken instead of the standard stream-based connection. Signed-off-by: Laurent Vivier <lvivier@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
| * | | net: Add passt network backendLaurent Vivier2025-07-141-2/+38
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit introduces support for passt as a new network backend. passt is an unprivileged, user-mode networking solution that provides connectivity for virtual machines by launching an external helper process. The implementation reuses the generic stream data handling logic. It launches the passt binary using GSubprocess, passing it a file descriptor from a socketpair() for communication. QEMU connects to the other end of the socket pair to establish the network data stream. The PID of the passt daemon is tracked via a temporary file to ensure it is terminated when QEMU exits. Signed-off-by: Laurent Vivier <lvivier@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
* | | docs/system/target-i386: Remove the sentence about RHEL 7 being supportedThomas Huth2025-07-131-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to our "Supported build platforms" policy, RHEL 7 is not supported anymore, so let's remove the related sentence from the x86 documentation. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* | | docs: remove repeated wordAndrew Kreimer2025-07-131-1/+1
|/ / | | | | | | | | | | | | | | | | The word 'find' appears twice, remove the extra one. Signed-off-by: Andrew Kreimer <algonell@gmail.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* | docs/system: arm: Add max78000 board descriptionJackson Donaldson2025-07-112-0/+38
| | | | | | | | | | | | | | | | | | | | | | This adds the target guide for the max78000FTHR Signed-off-by: Jackson Donaldson <jcksn@duck.com> Message-id: 20250711110626.624534-2-jcksn@duck.com [PMM: Moved doc to correct place in index; made underlines correct length; added missing trailing newline; added SPDX] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | docs/cxl: Add an arm/virt example.Jonathan Cameron2025-07-101-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Only add one very simple example as all the i386/pc examples will work for arm/virt with a change to appropriate executable and appropriate standard launch line for arm/virt. Note that max cpu is used to ensure we have plenty of physical address space. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Tested-by: Itaru Kitayama <itaru.kitayama@fujitsu.com> Tested-by: Li Zhijian <lizhijian@fujitsu.com> Message-id: 20250703104110.992379-5-Jonathan.Cameron@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxlJonathan Cameron2025-07-081-0/+9
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Code based on i386/pc enablement. The memory layout places space for 16 host bridge register regions after the GIC_REDIST2 in the extended memmap. This is a hole in the current map so adding them here has no impact on placement of other memory regions (tested with enough CPUs for GIC_REDIST2 to be in use.) The high memory map is GiB aligned so the hole is there whatever the size of memory or device_memory below this point. The CFMWs are placed above the extended memmap. Note the existing variable highest_gpa is the highest GPA that has been allocated at a particular point in setting up the memory map. Whilst this caused some confusion in review there are existing comments explaining this so nothing is added. The cxl_devices_state.host_mr provides a small space in which to place the individual host bridge register regions for whatever host bridges are allocated via -device pxb-cxl on the command line. The existing dynamic sysbus infrastructure is not reused because pxb-cxl is a PCI device not a sysbus one but these registers are directly in the main memory map, not the PCI address space. Only create the CEDT table if cxl=on set for the machine. Default to off. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Tested-by: Itaru Kitayama <itaru.kitayama@fujitsu.com> Tested-by: Li Zhijian <lizhijian@fujitsu.com> Message-id: 20250703104110.992379-4-Jonathan.Cameron@huawei.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Merge tag 'pull-target-arm-20250704' of https://gitlab.com/pm215/qemu into ↵Stefan Hajnoczi2025-07-071-0/+6
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging target-arm queue: * Implement emulation of SME2p1 and SVE2p1 * Correctly enforce alignment checks for v8M loads and stores done via helper functions * Mark the "highbank" and the "midway" machine as deprecated # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmhoABMZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3n5CD/9esli7dCvutRUv0YCDR0ca # HyFgZT5Z+rnjdUgIBWk3qPIdmQ+dCvK8gci8Du8mY7WWPvJFc+x2wE9b0trxaARZ # ckjPo/dPq18FPRqppbNo5LGeBImwVqMYioJtuLIDw6vdMlm6eYvyyJWoFo6pXXPY # 3FlW0vBWZ78/KlQ8dYVK8TQryT2qswjXqvhz96/wCFQWRyWCXNosgETGQQH2z/20 # y5qAMkmI3NATaSSnkVox88RipFSnqotKSpczG5MBXs/n4hZvMHHNfrNxgZ17lygP # WI4R5j/M3cRHnglRzxVm5xzz0Vy8gWV+Zn97YMN2syJhze2nFQDcD6dWGNEYdCgT # R83/FF2yVn7v4ZompmyL97eUtfiFR/t40M+ojdhrfwADNelAU0JbeLahJuJjXfBm # ptdiTnDXYD8Ts6X+FTCafWO9ciPmPJ+SyXOcDnRpy8NpNstL6e7Um5BU8Tcw41nV # cAP5K5LooQO6yDkrVf2sjFCU9QxamPhCck+xQsT85njy3br3OA2MTGA/ZdD5noet # i2EIcdovQjMZqRv/P8c/+WzDhUw27fPbMzLOvl+nUHQM29Mx7hdTvbdvj/CiQtpV # wXprWqdG6jeAXeIkhwFs6/8Uc+7mn3guPi8RQZ5uwX5e1pYNSVOKMjGpooVekNbL # qjb+ZLPXIpkCV3N5Vbg9Uw== # =onnF # -----END PGP SIGNATURE----- # gpg: Signature made Fri 04 Jul 2025 12:23:47 EDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20250704' of https://gitlab.com/pm215/qemu: (119 commits) linux-user/aarch64: Set hwcap bits for SME2p1/SVE2p1 target/arm: Enable FEAT_SME2p1 on -cpu max target/arm: Implement SME2 BFMOPA (non-widening) target/arm: Implement FMOPA (non-widening) for fp16 target/arm: Support FPCR.AH in SME FMOPS, BFMOPS target/arm: Rename BFMOPA to BFMOPA_w target/arm: Rename FMOPA_h to FMOPA_w_h target/arm: Implement LUTI2, LUTI4 for SME2/SME2p1 target/arm: Implement MOVAZ for SME2p1 target/arm: Implement LD1Q, ST1Q for SVE2p1 target/arm: Implement {LD, ST}[234]Q for SME2p1/SVE2p1 target/arm: Move ld1qq and st1qq primitives to sve_ldst_internal.h target/arm: Implement {LD1, ST1}{W, D} (128-bit element) for SVE2p1 target/arm: Split the ST_zpri and ST_zprr patterns target/arm: Implement SME2 counted predicate register load/store target/arm: Implement TBLQ, TBXQ for SME2p1/SVE2p1 target/arm: Implement ZIPQ, UZPQ for SME2p1/SVE2p1 target/arm: Implement PMOV for SME2p1/SVE2p1 target/arm: Implement EXTQ for SME2p1/SVE2p1 target/arm: Implement DUPQ for SME2p1/SVE2p1 ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * target/arm: Enable FEAT_SME2p1 on -cpu maxRichard Henderson2025-07-041-0/+6
| | | | | | | | | | | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250704142112.1018902-107-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | Merge tag 'pull-riscv-to-apply-20250704' of ↵Stefan Hajnoczi2025-07-042-0/+40
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://github.com/alistair23/qemu into staging Second RISC-V PR for 10.1 * sstc extension fixes * Fix zama16b order in isa_edata_arr * Profile handling fixes * Extend PMP region up to 64 * Remove capital 'Z' CPU properties * Add missing named features * Support atomic instruction fetch (Ziccif) * Add max_satp_mode from host cpu * Extend and configure PMP region count * Fix PPN field of Translation-reponse register * Use qemu_chr_fe_write_all() in DBCN_CONSOLE_WRITE_BYTE * Fix fcvt.s.bf16 NaN box checking * Avoid infinite delay of async xmit function * Device tree reg cleanups * Add Kunminghu CPU and platform * Fix missing exit TB flow for ldff_trans * Fix migration failure when aia is configured as aplic-imsic * Fix MEPC/SEPC bit masking for IALIGN * Add a property to set vill bit on reserved usage of vsetvli instruction * Add Svrsw60t59b extension support # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmhntt4ACgkQr3yVEwxT # gBMaCQ/9E+LeRY59nz3K3XXUw6XLBfaDECXbKzIn0GM1yXeWTX4dB2h2hoGWdu3R # CRPxWHECN7CeJhd2J23eLfOi+fTUeppJBeR7TcGyoXVC+y0knZv/clQ3OvMFYcgV # xjzzu1yipQlXwY+kmDZ6qL5up/Q+faw7tRaePZaJheRGYpVRnjoKUZq5fe4Ug4RU # Xg6Di86eYyk+Jo0g2exvtzy1rX2eBp7Hz200wWiH5Z1B+3NzgMUHrHuJfNAz8zAt # n8uvruvaLGGtWcQJauRXlAELR6k9tmkfq1Mbqf3FK6muaQCtFD7PXXnjL/rU/z20 # hhxj0psOhBJLd0W5wQ3vLnDf6Wve9zmUdTR9kI0Kt3xUUdfeBuzKcU06F/G8wEsZ # 2sIYQqt0mxoJboY2lpje7TO4H9gvAf76WBOV10FV2gWsqWu2rZQ6herdq3YZYkHX # purUTgyjHn4jl2Y3Kzj0Gq1SHo0yaA/sD6xNR8X+JqljSruDxtOFU7wkKBbewoIg # OSfwemjRUVsPQZ958042ntwJt81v1604Oky8JSFr5eCFx/aoLJ1vDYh7BKZAogNH # uB/YigGq9+/MVzqJpZI+kZkd+1nzaizeL0FUPRTq0jFA2u+vc3J3svQ/jNXDH2c+ # 5nGuhbkvT0ptmVMBqFV2vjPh6+ScR8t03wHdQ4PmDoXC3o9zbbU= # =CfRy # -----END PGP SIGNATURE----- # gpg: Signature made Fri 04 Jul 2025 07:11:26 EDT # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20250704' of https://github.com/alistair23/qemu: (40 commits) target: riscv: Add Svrsw60t59b extension support target/riscv: Add a property to set vill bit on reserved usage of vsetvli instruction tests/tcg/riscv64: Add test for MEPC bit masking target/riscv: Fix MEPC/SEPC bit masking for IALIGN migration: Fix migration failure when aia is configured as aplic-imsic target/riscv: rvv: Fix missing exit TB flow for ldff_trans hw/riscv: Initial support for BOSC's Xiangshan Kunminghu FPGA prototype target/riscv: Add BOSC's Xiangshan Kunminghu CPU hw/riscv/virt: Use setprop_sized_cells for pcie hw/riscv/virt: Use setprop_sized_cells for iommu hw/riscv/virt: Use setprop_sized_cells for rtc hw/riscv/virt: Use setprop_sized_cells for uart hw/riscv/virt: Use setprop_sized_cells for reset hw/riscv/virt: Use setprop_sized_cells for virtio hw/riscv/virt: Use setprop_sized_cells for plic hw/riscv/virt: Use setprop_sized_cells for aclint hw/riscv/virt: Use setprop_sized_cells for aplic hw/riscv/virt: Use setprop_sized_cells for memory hw/riscv/virt: Use setprop_sized_cells for clint hw/riscv/virt: Fix clint base address type ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * | hw/riscv: Initial support for BOSC's Xiangshan Kunminghu FPGA prototypeHuang Borong2025-07-042-0/+40
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This implementation provides emulation for the Xiangshan Kunminghu FPGA prototype platform, including support for UART, CLINT, IMSIC, and APLIC devices. More details can be found at https://github.com/OpenXiangShan/XiangShan Signed-off-by: qinshaoqing <qinshaoqing@bosc.ac.cn> Signed-off-by: Yang Wang <wangyang@bosc.ac.cn> Signed-off-by: Yu Hu <819258943@qq.com> Signed-off-by: Ran Wang <wangran@bosc.ac.cn> Signed-off-by: Borong Huang <3543977024@qq.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20250617074222.17618-1-wangran@bosc.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* / docs: add support for gb200-bmcEd Tanous2025-07-031-2/+2
|/ | | | | | | | | This patch updates the docs for support of gb200-bmc. Signed-off-by: Ed Tanous <etanous@nvidia.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250703144249.3348879-3-etanous@nvidia.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
* docs: add vfio-user documentationJohn Levon2025-06-262-0/+27
| | | | | | | | | Add some basic documentation on vfio-user usage. Signed-off-by: John Levon <john.levon@nutanix.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250625193012.2316242-19-john.levon@nutanix.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
* Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingStefan Hajnoczi2025-05-303-0/+163
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * target/i386/kvm: Intel TDX support * target/i386/emulate: more lflags cleanups * meson: remove need for explicit listing of dependencies in hw_common_arch and target_common_arch * rust: small fixes * hpet: Reorganize register decoding to be more similar to Rust code * target/i386: fixes for AMD models * target/i386: new EPYC-Turin CPU model # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCgAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmg4BxwUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroP67gf+PEP4EDQP0AJUfxXYVsczGf5snGjz # ro8jYmKG+huBZcrS6uPK5zHYxtOI9bHr4ipTHJyHd61lyzN6Ys9amPbs/CRE2Q4x # Ky4AojPhCuaL2wHcYNcu41L+hweVQ3myj97vP3hWvkatulXYeMqW3/4JZgr4WZ69 # A9LGLtLabobTz5yLc8x6oHLn/BZ2y7gjd2LzTz8bqxx7C/kamjoDrF2ZHbX9DLQW # BKWQ3edSO6rorSNHWGZsy9BE20AEkW2LgJdlV9eXglFEuEs6cdPKwGEZepade4bQ # Rdt2gHTlQdUDTFmAbz8pttPxFGMC9Zpmb3nnicKJpKQAmkT/x4k9ncjyAQ== # =XmkU # -----END PGP SIGNATURE----- # gpg: Signature made Thu 29 May 2025 03:05:00 EDT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (77 commits) target/i386/tcg/helper-tcg: fix file references in comments target/i386: Add support for EPYC-Turin model target/i386: Update EPYC-Genoa for Cache property, perfmon-v2, RAS and SVM feature bits target/i386: Add couple of feature bits in CPUID_Fn80000021_EAX target/i386: Update EPYC-Milan CPU model for Cache property, RAS, SVM feature bits target/i386: Update EPYC-Rome CPU model for Cache property, RAS, SVM feature bits target/i386: Update EPYC CPU model for Cache property, RAS, SVM feature bits rust: make declaration of dependent crates more consistent docs: Add TDX documentation i386/tdx: Validate phys_bits against host value i386/tdx: Make invtsc default on i386/tdx: Don't treat SYSCALL as unavailable i386/tdx: Fetch and validate CPUID of TD guest target/i386: Print CPUID subleaf info for unsupported feature i386: Remove unused parameter "uint32_t bit" in feature_word_description() i386/cgs: Introduce x86_confidential_guest_check_features() i386/tdx: Define supported KVM features for TDX i386/tdx: Add XFD to supported bit of TDX i386/tdx: Add supported CPUID bits relates to XFAM i386/tdx: Add supported CPUID bits related to TD Attributes ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * docs: Add TDX documentationXiaoyao Li2025-05-283-0/+163
| | | | | | | | | | | | | | | | | | Add docs/system/i386/tdx.rst for TDX support, and add tdx in confidential-guest-support.rst Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com> Link: https://lore.kernel.org/r/20250508150002.689633-56-xiaoyao.li@intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | docs: Remove ast2700fc from Aspeed family boardsSteven Lee2025-05-251-1/+1
|/ | | | | | | | | | | The ast2700fc machine is now covered in the dedicated ast2700-evb section. Listing it in the general Aspeed board family list is redundant. Signed-off-by: Steven Lee <steven_lee@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250523093144.991408-7-steven_lee@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
* hw/riscv: microchip_pfsoc: Rework documentationSebastian Huber2025-05-191-81/+43
| | | | | | | | | | Mention that running the HSS no longer works. Document the changed boot options. Reorder documentation blocks. Update URLs. Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250319061342.26435-7-sebastian.huber@embedded-brains.de> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu ↵Stefan Hajnoczi2025-05-153-9/+47
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging virtio,pci,pc: fixes, features vhost-scsi now supports scsi hotplug cxl gained a bag of new operations, motably media operations virtio-net now supports SR-IOV emulation pci-testdev now supports backing memory bar with host memory amd iommu now supports migration fixes all over the place Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCgAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmgkg0UPHG1zdEByZWRo # YXQuY29tAAoJECgfDbjSjVRpcDIH+wbrq7DzG+BVOraYtmD69BQCzYszby1mAWry # 2OUYuAx9Oh+DsAwbzwbBdh9+SmJoi1oJ/d8rzSK328hdDrpCaPmc7bcBdAWJ3YcB # bGNPyJ+9eJLRXtlceGIhfAOMLIB0ugXGkHLQ61zlVCTg4Xwnj7/dQp2tAQ1BkTwW # Azc7ujBoJOBF3WVpa1Pqw0t1m3K74bwanOlkIg/JUWXk27sgP2YMnyrcpOu9Iz1T # VazgobyHo5y15V0wvd05w4Bk7cJSHwgW+y3DtgTtIffetIaAbSRgl3Pl5Ic1yKcX # ofg9aDFN6m0S8tv4WgFc+rT3Xaa/aPue9awjD5sEEldRasWKKNo= # =847R # -----END PGP SIGNATURE----- # gpg: Signature made Wed 14 May 2025 07:49:25 EDT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (27 commits) hw/i386/amd_iommu: Allow migration when explicitly create the AMDVI-PCI device hw/i386/amd_iommu: Isolate AMDVI-PCI from amd-iommu device to allow full control over the PCI device creation intel_iommu: Take locks when looking for and creating address spaces intel_iommu: Use BQL_LOCK_GUARD to manage cleanup automatically virtio: Move virtio_reset() virtio: Call set_features during reset vhost-scsi: support VIRTIO_SCSI_F_HOTPLUG vhost-user: return failure if backend crash when live migration vhost: return failure if stop virtqueue failed in vhost_dev_stop system/runstate: add VM state change cb with return value pci-testdev.c: Add membar-backed option for backing membar pcie_sriov: Make a PCI device with user-created VF ARI-capable docs: Document composable SR-IOV device virtio-net: Implement SR-IOV VF virtio-pci: Implement SR-IOV PF pcie_sriov: Allow user to create SR-IOV device pcie_sriov: Check PCI Express for SR-IOV PF pcie_sriov: Ensure PF and VF are mutually exclusive hw/pci: Fix SR-IOV VF number calculation hw/pci: Do not add ROM BAR for SR-IOV VF ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * pcie_sriov: Make a PCI device with user-created VF ARI-capableAkihiko Odaki2025-05-141-1/+2
| | | | | | | | | | | | | | | | | | Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20250314-sriov-v9-9-57dae8ae3ab5@daynix.com> Tested-by: Yui Washizu <yui.washidu@gmail.com> Tested-by: Pasha Tatashin <pasha.tatashin@soleen.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * docs: Document composable SR-IOV deviceAkihiko Odaki2025-05-142-0/+37
| | | | | | | | | | | | | | | | | | Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20250314-sriov-v9-8-57dae8ae3ab5@daynix.com> Tested-by: Yui Washizu <yui.washidu@gmail.com> Tested-by: Pasha Tatashin <pasha.tatashin@soleen.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * docs/cxl: Add serial number for persistent-memdevYuquan Wang2025-05-141-9/+9
| | | | | | | | | | | | | | | | | | | | Add serial number parameter in the cxl persistent examples. Signed-off-by: Yuquan Wang <wangyuquan1236@phytium.com.cn> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20250305092501.191929-9-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* | Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into stagingStefan Hajnoczi2025-05-123-5/+5
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | trivial patches for 2025-05-09 # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEZKoqtTHVaQM2a/75gqpKJDselHgFAmgeawQACgkQgqpKJDse # lHgRcg/+LmwJJvMViRD/OJFRqp60zBnPyuXFyJJQ3q7lBsE5Vr8xdZUkrGUrQ0p+ # ef6KRnqesaYFH6lEZIJIYXLPalHDIJg6NCHnOphXYoexYQ61e8Y07lmTJlCXK+T8 # rTf230ZC0Jzuy6BM5cmk7cMnNtVp8gPgK5SOK4u5OJSQTBMDb/XZZkLdnjj5ChGJ # aX4qZ9fDLOWJoteXA4QWx6F8K1ONvooS5IMYB6AFJI2xMASq8nVETPXIuSComBDY # 2+krw8hLu6PoPd9yWjlnsE8y4NvNWyRAc2CVm3SI30PEIchvDiQuVJpUD5Q3xZy5 # 2OLD9nv9PqezERbD2ZdSa08VlbEeoyrRinBtZJv7m9qkiU8B4TGDn7hx23MAu6Zx # POF+P1Bc4kixL46pDMll5ETcRr6k184anTvpPWhOynJZBZusc4rX3UHSrVJMsfTx # DPjToUwRw50prtHyuYWWyoxZ+i9BOHAgiT/zOor2tte3xT/mvc8my9m2+YgDHnqE # u8wTnH3zYqexOwLctC3aslSbR1sqqrCsKOA8ZXQ33Ac6kV1q2T4Om4stmRbewjMG # ROsNky2iiKbPsSJsmZHVuv0vy3sHRVWyyp8ClSP5S+gNysEVu/Oka3E0KQ/vg72y # lDA3kNKS2t7ZSPXoLFaSWI6aOnSpKZgNW09wSVDh/AjKV+LbC6c= # =EoxT # -----END PGP SIGNATURE----- # gpg: Signature made Fri 09 May 2025 16:52:20 EDT # gpg: using RSA key 64AA2AB531D56903366BFEF982AA4A243B1E9478 # gpg: Good signature from "Michael Tokarev <mjt@debian.org>" [unknown] # gpg: aka "Michael Tokarev <mjt@corpit.ru>" [unknown] # gpg: aka "Michael Tokarev <mjt@tls.msk.ru>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 9D8B E14E 3F2A 9DD7 9199 28F1 61AD 3D98 ECDF 2C8E # Subkey fingerprint: 64AA 2AB5 31D5 6903 366B FEF9 82AA 4A24 3B1E 9478 * tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu: (21 commits) docs/devel/testing/functional: Fix typo docs: replace `-hda` with `-drive` & update `root=` kernel parameter qapi/machine-target.json: fix "in in" typo in comment hw/display/apple-gfx.m: fix "in in" typo in comment qapi/qom.json: fix "the the" typo in comment include/hw/xen/interface/io/blkif.h: fix "the the" typo in comment include/exec/cpu-common.h: fix "the the" typo in comment hw/xen/xen-hvm-common.c: fix "the the" typo in comment block.c: fix "the the" typo in comment linux-user/mmap.c: fix "of of" typo in comment hw/acpi/pcihp: Fix typo in function name hw/pci-host/gpex-acpi: Fix typo in comment hw/net/e1000: Remove stray empty comment in header qom/object: Fix typo in comment hw/core/machine: Fix indentation hw/i386/acpi-build: Fix typo in function name hw/acpi/ich9: Remove ICH9_DEBUG macro hw/i386/acpi-build: Update document reference hw/i386/acpi-build: Fix typo and grammar in comment hw/isa/ich9: Remove stray empty comment ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * docs: replace `-hda` with `-drive` & update `root=` kernel parameterIntegral2025-05-093-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | According to QEMU manual: Older options like `-hda` are essentially macros which expand into `-drive` options for various drive interfaces. The original forms bake in a lot of assumptions from the days when QEMU was emulating a legacy PC, they are not recommended for modern configurations. Signed-off-by: Integral <integral@archlinuxcn.org> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* | docs: Don't define duplicate label in qemu-block-drivers.rst.incPeter Maydell2025-05-061-2/+0
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sphinx requires that labels within documents are unique across the whole manual. This is because the "create a hyperlink" directive specifies only the name of the label, not a filename+label. Some Sphinx versions will warn about duplicate labels, but even if there is no warning there is still an ambiguity and no guarantee that the hyperlink will be created to the right target. For QEMU this is awkward, because we have various .rst.inc fragments which we include into multiple .rst files. If you define a label in the .rst.inc file then it will be a duplicate label. We have mostly worked around this by not putting labels into those .rst.inc files, or by adding "insert a label" functionality into the hxtool extension (see commit 1eeb432a953b0 "doc/sphinx/hxtool.py: add optional label argument to SRST directive"). Unfortunately in commit 7f6314427e78 ("docs/devel: add a codebase section") we accidentally added a duplicate label, because not all Sphinx versions warn about the mistake. In this case the link was only from the developer docs codebase summary, so as the simplest fix for the stable branch, we drop the link entirely. Cc: qemu-stable@nongnu.org Fixes: 1eeb432a953b0 "doc/sphinx/hxtool.py: add optional label argument to SRST directive" Reported-by: Dario Faggioli <dfaggioli@suse.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Eric Blake <eblake@redhat.com> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250501093126.716667-1-peter.maydell@linaro.org