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* hw/arm: xlnx-versal-virt: Add AMD/Xilinx TRNG deviceTong Ho2023-11-022-0/+17
| | | | | | | | | | | | | | | | Connect the support for Versal True Random Number Generator (TRNG) device. Warning: unlike the TRNG component in a real device from the Versal device familiy, the connected TRNG model is not of cryptographic grade and is not intended for use cases when cryptograpically strong TRNG is needed. Signed-off-by: Tong Ho <tong.ho@amd.com> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20231031184611.3029156-3-tong.ho@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/pxa2xx_gpio: Pass CPU using QOM link propertyPhilippe Mathieu-Daudé2023-11-021-6/+2
| | | | | | | | | | Instead of passing the CPU index and resolving it, use a QOM link to directly pass the CPU. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20231030083706.63685-1-philmd@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/input/stellaris_gamepad: Convert to qemu_input_handler_register()Peter Maydell2023-11-021-1/+5
| | | | | | | | | | | | | | | | | | | Now that we have converted to qdev, we can use the newer qemu_input_handler_register() API rather than the legacy qemu_add_kbd_event_handler(). Since we only have one user, take the opportunity to convert from scancodes to QCodes, rather than using qemu_input_key_value_to_scancode() (which adds an 0xe0 prefix and encodes up/down indication in the scancode, which our old handler function then had to reverse). That lets us drop the old state field which was tracking whether we were halfway through a two-byte scancode. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20231030114802.3671871-7-peter.maydell@linaro.org
* hw/input/stellaris_input: Convert to qdevPeter Maydell2023-11-021-8/+20
| | | | | | | | | | | | | Convert the hw/input/stellaris_input device to qdev. The interface uses an array property for the board to specify the keycodes to use, so the s->keycodes memory is now allocated by the array-property machinery. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20231030114802.3671871-6-peter.maydell@linaro.org
* hw/input/stellaris_input: Rename to stellaris_gamepadPeter Maydell2023-11-022-2/+2
| | | | | | | | | | This source file implements a stellaris gamepad device; rename it so that it is a closer match to the device name. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20231030114802.3671871-2-peter.maydell@linaro.org
* hw/arm: Avoid using 'first_cpu' when first ARM CPU is reachablePhilippe Mathieu-Daudé2023-10-275-7/+8
| | | | | | | | | Prefer using a well known local first CPU rather than a global one. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231025065909.57344-1-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/pxa2xx: Realize PXA2XX_I2C device before accessing itPhilippe Mathieu-Daudé2023-10-271-2/+3
| | | | | | | | | | | qbus_new(), called in i2c_init_bus(), should not be called on unrealized device. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-id: 20231020130331.50048-10-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/intc/pxa2xx: Factor pxa2xx_pic_realize() out of pxa2xx_pic_init()Philippe Mathieu-Daudé2023-10-271-6/+10
| | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-id: 20231020130331.50048-9-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/intc/pxa2xx: Pass CPU reference using QOM link propertyPhilippe Mathieu-Daudé2023-10-271-1/+10
| | | | | | | | | | | QOM objects shouldn't access each other internals fields except using the QOM API. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-id: 20231020130331.50048-8-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/intc/pxa2xx: Convert to Resettable interfacePhilippe Mathieu-Daudé2023-10-271-5/+12
| | | | | | | | | | Factor reset code out of the DeviceRealize() handler. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-id: 20231020130331.50048-7-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/pcmcia/pxa2xx: Inline pxa2xx_pcmcia_init()Philippe Mathieu-Daudé2023-10-271-4/+8
| | | | | | | | Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231020130331.50048-6-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/xlnx-zynqmp: Remove 'hw/arm/boot.h' from headerPhilippe Mathieu-Daudé2023-10-271-0/+1
| | | | | | | | | | "hw/arm/boot.h" is only required on the source file. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Message-id: 20231025065316.56817-11-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/xlnx-versal: Remove 'hw/arm/boot.h' from headerPhilippe Mathieu-Daudé2023-10-271-0/+1
| | | | | | | | | | "hw/arm/boot.h" is only required on the source file. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Message-id: 20231025065316.56817-10-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/fsl-imx7: Remove 'hw/arm/boot.h' from headerPhilippe Mathieu-Daudé2023-10-271-0/+1
| | | | | | | | | | "hw/arm/boot.h" is only required on the source file. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Message-id: 20231025065316.56817-9-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/fsl-imx6ul: Remove 'hw/arm/boot.h' from headerPhilippe Mathieu-Daudé2023-10-271-0/+1
| | | | | | | | | | "hw/arm/boot.h" is only required on the source file. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Message-id: 20231025065316.56817-8-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/fsl-imx6: Remove 'hw/arm/boot.h' from headerPhilippe Mathieu-Daudé2023-10-271-0/+1
| | | | | | | | | | "hw/arm/boot.h" is only required on the source file. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Message-id: 20231025065316.56817-7-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/fsl-imx31: Remove 'hw/arm/boot.h' from headerPhilippe Mathieu-Daudé2023-10-271-0/+1
| | | | | | | | | | "hw/arm/boot.h" is only required on the source file. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Message-id: 20231025065316.56817-6-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/fsl-imx25: Remove 'hw/arm/boot.h' from headerPhilippe Mathieu-Daudé2023-10-271-0/+1
| | | | | | | | | | "hw/arm/boot.h" is only required on the source file. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Message-id: 20231025065316.56817-5-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/allwinner-r40: Remove 'hw/arm/boot.h' from headerPhilippe Mathieu-Daudé2023-10-271-0/+1
| | | | | | | | | | "hw/arm/boot.h" is only required on the source file. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Message-id: 20231025065316.56817-4-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/allwinner-h3: Remove 'hw/arm/boot.h' from headerPhilippe Mathieu-Daudé2023-10-271-0/+1
| | | | | | | | | | "hw/arm/boot.h" is only required on the source file. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Message-id: 20231025065316.56817-3-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/allwinner-a10: Remove 'hw/arm/boot.h' from headerPhilippe Mathieu-Daudé2023-10-271-0/+1
| | | | | | | | | | "hw/arm/boot.h" is only required on the source file. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Message-id: 20231025065316.56817-2-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Move feature test functions to their own headerPeter Maydell2023-10-271-0/+1
| | | | | | | | | | | | The feature test functions isar_feature_*() now take up nearly a thousand lines in target/arm/cpu.h. This header file is included by a lot of source files, most of which don't need these functions. Move the feature test functions to their own header file. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231024163510.2972081-2-peter.maydell@linaro.org
* target/arm: Implement Neoverse N2 CPU modelPeter Maydell2023-10-272-0/+2
| | | | | | | | | | | | | | | | | | | | Implement a model of the Neoverse N2 CPU. This is an Armv9.0-A processor very similar to the Cortex-A710. The differences are: * no FEAT_EVT * FEAT_DGH (data gathering hint) * FEAT_NV (not yet implemented in QEMU) * Statistical Profiling Extension (not implemented in QEMU) * 48 bit physical address range, not 40 * CTR_EL0.DIC = 1 (no explicit icache cleaning needed) * PMCR_EL0.N = 6 (always 6 PMU counters, not 20) Because it has 48-bit physical address support, we can use this CPU in the sbsa-ref board as well as the virt board. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20230915185453.1871167-3-peter.maydell@linaro.org
* hw/arm/aspeed: Move AspeedSoCState::cpu/vic to Aspeed2400SoCStatePhilippe Mathieu-Daudé2023-10-252-13/+16
| | | | | | | | | The ARM array and VIC peripheral are only used by the 2400 series, remove them from the common AspeedSoCState. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* hw/arm/aspeed: Move AspeedSoCState::a7mpcore to Aspeed2600SoCStatePhilippe Mathieu-Daudé2023-10-252-29/+34
| | | | | | | | | | | | | The v7-A cluster is specific to the Aspeed 2600 series, remove it from the common AspeedSoCState. The ARM cores belong to the MP cluster, but the array is currently used by TYPE_ASPEED2600_SOC. We'll clean that soon, but for now keep it in Aspeed2600SoCState. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* hw/arm/aspeed: Move AspeedSoCState::armv7m to Aspeed10x0SoCStatePhilippe Mathieu-Daudé2023-10-252-17/+23
| | | | | | | | | The v7-M core is specific to the Aspeed 10x0 series, remove it from the common AspeedSoCState. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* hw/arm/aspeed: Check 'memory' link is set in common aspeed_soc_realizePhilippe Mathieu-Daudé2023-10-251-0/+11
| | | | | | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* hw/arm/aspeed: Introduce TYPE_ASPEED2400_SOCPhilippe Mathieu-Daudé2023-10-252-44/+46
| | | | | | | | | | | | | TYPE_ASPEED2400_SOC inherits from TYPE_ASPEED_SOC. In few commits we'll add more fields, but to keep review process simple, don't add any yet. TYPE_ASPEED_SOC is common to various Aspeed SoCs, define it in aspeed_soc_common.c. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* hw/arm/aspeed: Introduce TYPE_ASPEED2600_SOCPhilippe Mathieu-Daudé2023-10-251-13/+13
| | | | | | | | | | TYPE_ASPEED2600_SOC inherits from TYPE_ASPEED_SOC. In few commits we'll add more fields, but to keep review process simple, don't add any yet. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* hw/arm/aspeed: Introduce TYPE_ASPEED10X0_SOCPhilippe Mathieu-Daudé2023-10-251-13/+13
| | | | | | | | | | TYPE_ASPEED10X0_SOC inherits from TYPE_ASPEED_SOC. In few commits we'll add more fields, but to keep review process simple, don't add any yet. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* hw/arm/aspeed: Dynamically allocate AspeedMachineState::soc fieldPhilippe Mathieu-Daudé2023-10-251-49/+52
| | | | | | | | | | We want to derivate the big AspeedSoCState object in some more SoC-specific ones. Since the object size will vary, allocate it dynamically. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* hw/arm/aspeed: Rename aspeed_soc_realize() as AST2400/2500 specificPhilippe Mathieu-Daudé2023-10-251-4/+11
| | | | | | | | | Keep aspeed_soc_class_init() generic, set the realize handler to aspeed_ast2400_soc_realize() in each 2400/2500 class_init. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* hw/arm/aspeed: Rename aspeed_soc_init() as AST2400/2500 specificPhilippe Mathieu-Daudé2023-10-251-3/+3
| | | | | | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* hw/arm/aspeed: Extract code common to all boards to a common filePhilippe Mathieu-Daudé2023-10-253-96/+115
| | | | | | | | | | aspeed_soc.c contains definitions specific to the AST2400 and AST2500 SoCs, but also some definitions for other AST SoCs: move them to a common file. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* Merge tag 'hw-misc-20231019' of https://github.com/philmd/qemu into stagingStefan Hajnoczi2023-10-201-3/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Misc hardware patch queue - MAINTAINERS updates (Zoltan, Thomas) - Fix cutils::get_relocated_path on Windows host (Akihiko) - Housekeeping in Memory APIs (Marc-André) - SDHCI fix for SDMA transfer (Lu, Jianxian) - Various QOM/QDev/SysBus cleanups (Philippe) - Constify QemuInputHandler structure (Philippe) # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmUxnKAACgkQ4+MsLN6t # wN6UPw//abFZgckpxDYow4UfMu7esvkhICBvXjqDEdX2U/PBYmef049T5RVW8oDm # NWnxRA9XydzTeToH56tU2tjXbjWKF5LcJVwrCNl6XFRdLYaR3hzejm96hX99C89J # PB/2ineeAwidBoFfgjkvz0FLRr1ePaN74YXedPSHzywG+0dAOvpNUubbsggn3i5k # 1wTlgfDvL6iz8NMEOSBp6cv5D4Ix0WshkqlCac0gQ74lYSM1tk/EeRiSy2IHWQQB # 4FHd9Wo9brzLQCbhbb4FapTK0POScy0LebzRWOWfLtyWS+FRBC3kxO126I67CwMb # XRS4YgBqC3U7IGsbzV+fWP01pVeJRzZ1vrv4vdiIYvqTdgNlmFbGjJUwEmPmrokt # q5UreAjMUNLMEXiY6QHFq3N5I+UMY1jslcf7K/ZwDqSlqaquAe+gbnQOAMXDYgb6 # GWsBrLM2WA5E9ObbxsHdxgZqW1NxcWJpSBvjNiOV9t/jqoqpxYwHr5HAvR1xUwm+ # qRKRayRpLlX/Yad4NlvJaH5jvsMrI4bnxTYWVevLvYzc07Xo3dVxW1c+P+WCdjfM # O3bLAvwO7Mw7GRiSNpU8zTbRJu/dS4NWDWZ24u606Cy7qD/qouz89JjkKVYYSFkX # vNp7YOenPf4K6pak/lC3NOLIPlYmnnCLv3RCiaO6wHi4bk1yEBU= # =9dZy # -----END PGP SIGNATURE----- # gpg: Signature made Thu 19 Oct 2023 14:16:16 PDT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'hw-misc-20231019' of https://github.com/philmd/qemu: (46 commits) ui/input: Constify QemuInputHandler structure hw/net: Declare link using static DEFINE_PROP_LINK() macro hw/dma: Declare link using static DEFINE_PROP_LINK() macro hw/scsi/virtio-scsi: Use VIRTIO_SCSI_COMMON() macro hw/display/virtio-gpu: Use VIRTIO_DEVICE() macro hw/block/vhost-user-blk: Use DEVICE() / VIRTIO_DEVICE() macros hw/virtio/virtio-pmem: Replace impossible check by assertion hw/s390x/css-bridge: Realize sysbus device before accessing it hw/isa: Realize ISA bridge device before accessing it hw/arm/virt: Realize ARM_GICV2M sysbus device before accessing it hw/acpi: Realize ACPI_GED sysbus device before accessing it hw/pci-host/bonito: Do not use SysBus API to map local MMIO region hw/misc/allwinner-dramc: Do not use SysBus API to map local MMIO region hw/misc/allwinner-dramc: Move sysbus_mmio_map call from init -> realize hw/i386/intel_iommu: Do not use SysBus API to map local MMIO region hw/i386/amd_iommu: Do not use SysBus API to map local MMIO region hw/audio/pcspk: Inline pcspk_init() hw/intc/spapr_xive: Do not use SysBus API to map local MMIO region hw/intc/spapr_xive: Move sysbus_init_mmio() calls around hw/ppc/pnv: Do not use SysBus API to map local MMIO region ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * hw/arm/virt: Realize ARM_GICV2M sysbus device before accessing itPhilippe Mathieu-Daudé2023-10-191-1/+1
| | | | | | | | | | | | | | | | sysbus_mmio_map() should not be called on unrealized device. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20231018141151.87466-8-philmd@linaro.org>
| * hw/acpi: Realize ACPI_GED sysbus device before accessing itPhilippe Mathieu-Daudé2023-10-191-2/+1
| | | | | | | | | | | | | | | | | | sysbus_mmio_map() should not be called on unrealized device. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231018141151.87466-7-philmd@linaro.org>
* | target/arm/arm-powerctl: Correctly init CPUs when powered on to lower ELPeter Maydell2023-10-191-72/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code for powering on a CPU in arm-powerctl.c has two separate use cases: * emulation of a real hardware power controller * emulation of firmware interfaces (primarily PSCI) with CPU on/off APIs For the first case, we only need to reset the CPU and set its starting PC and X0. For the second case, because we're emulating the firmware we need to ensure that it's in the state that the firmware provides. In particular, when we reset to a lower EL than the highest one we are emulating, we need to put the CPU into a state that permits correct running at that lower EL. We already do a little of this in arm-powerctl.c (for instance we set SCR_HCE to enable the HVC insn) but we don't do enough of it. This means that in the case where we are emulating EL3 but also providing emulated PSCI the guest will crash when a secondary core tries to use a feature that needs an SCR_EL3 bit to be set, such as MTE or PAuth. The hw/arm/boot.c code also has to support this "start guest code in an EL that's lower than the highest emulated EL" case in order to do direct guest kernel booting; it has all the necessary initialization code to set the SCR_EL3 bits. Pull the relevant boot.c code out into a separate function so we can share it between there and arm-powerctl.c. This refactoring has a few code changes that look like they might be behaviour changes but aren't: * if info->secure_boot is false and info->secure_board_setup is true, then the old code would start the first CPU in Hyp mode but without changing SCR.NS and NSACR.{CP11,CP10}. This was wrong behaviour because there's no such thing as Secure Hyp mode. The new code will leave the CPU in SVC. (There is no board which sets secure_boot to false and secure_board_setup to true, so this isn't a behaviour change for any of our boards.) * we don't explicitly clear SCR.NS when arm-powerctl.c does a CPU-on to EL3. This was a no-op because CPU reset will reset to NS == 0. And some real behaviour changes: * we no longer set HCR_EL2.RW when booting into EL2: the guest can and should do that themselves before dropping into their EL1 code. (arm-powerctl and boot did this differently; I opted to use the logic from arm-powerctl, which only sets HCR_EL2.RW when it's directly starting the guest in EL1, because it's more correct, and I don't expect guests to be accidentally depending on our having set the RW bit for them.) * if we are booting a CPU into AArch32 Secure SVC then we won't set SCR.HCE any more. This affects only the vexpress-a15 and raspi2b machine types. Guests booting in this case will either: - be able to set SCR.HCE themselves as part of moving from Secure SVC into NS Hyp mode - will move from Secure SVC to NS SVC, and won't care about behaviour of the HVC insn - will stay in Secure SVC, and won't care about HVC * on an arm-powerctl CPU-on we will now set the SCR bits for pauth/mte/sve/sme/hcx/fgt features The first two of these are very minor and I don't expect guest code to trip over them, so I didn't judge it worth convoluting the code in an attempt to keep exactly the same boot.c behaviour. The third change fixes issue 1899. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1899 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230926155619.4028618-1-peter.maydell@linaro.org
* | hw/arm/smmuv3: Advertise SMMUv3.1-XNX featurePeter Maydell2023-10-191-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SMMUv3.1-XNX feature is mandatory for an SMMUv3.1 if S2P is supported, so we should theoretically have implemented it as part of the recent S2P work. Fortunately, for us the implementation is a no-op. This feature is about interpretation of the stage 2 page table descriptor XN bits, which control execute permissions. For QEMU, the permission bits passed to an IOMMU (via MemTxAttrs and IOMMUAccessFlags) only indicate read and write; we do not distinguish data reads from instruction reads outside the CPU proper. In the SMMU architecture's terms, our interconnect between the client device and the SMMU doesn't have the ability to convey the INST attribute, and we therefore use the default value of "data" for this attribute. We also do not support the bits in the Stream Table Entry that can override the on-the-bus transaction attribute permissions (we do not set SMMU_IDR1.ATTR_PERMS_OVR=1). These two things together mean that for our implementation, it never has to deal with transactions with the INST attribute, and so it can correctly ignore the XN bits entirely. So we already implement FEAT_XNX's "XN field is now 2 bits, not 1" behaviour to the extent that we need to. Advertise the presence of the feature in SMMU_IDR3.XNX. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Mostafa Saleh <smostafa@google.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20230914145705.1648377-4-peter.maydell@linaro.org
* | hw/arm/smmuv3: Sort ID register setting into field orderPeter Maydell2023-10-191-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | In smmuv3_init_regs() when we set the various bits in the ID registers, we do this almost in order of the fields in the registers, but not quite. Move the initialization of SMMU_IDR3.RIL and SMMU_IDR5.OAS into their correct places. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Mostafa Saleh <smostafa@google.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20230914145705.1648377-3-peter.maydell@linaro.org
* | hw/arm/smmuv3: Update ID register bit field definitionsPeter Maydell2023-10-191-0/+38
| | | | | | | | | | | | | | | | | | | | | | Update the SMMUv3 ID register bit field definitions to the set in the most recent specification (IHI0700 F.a). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Mostafa Saleh <smostafa@google.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20230914145705.1648377-2-peter.maydell@linaro.org
* | hw/arm/sbsa-ref: use bsa.h for PPI definitionsLeif Lindholm2023-10-191-12/+9
| | | | | | | | | | | | | | | | | | | | | | Use the private peripheral interrupt definitions from bsa.h instead of defining them locally. Refactor to use the INTIDs defined there instead of the PPI# used previously. Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> Message-id: 20230919090229.188092-4-quic_llindhol@quicinc.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | {include/}hw/arm: refactor virt PPI logicLeif Lindholm2023-10-192-16/+20
|/ | | | | | | | | | | | | | | | | | | | GIC Private Peripheral Interrupts (PPI) are defined as GIC INTID 16-31. As in, PPI0 is INTID16 .. PPI15 is INTID31. Arm's Base System Architecture specification (BSA) lists the mandated and recommended private interrupt IDs by INTID, not by PPI index. But current definitions in virt define them by PPI index, complicating cross referencing. Meanwhile, the PPI(x) macro counterintuitively adds 16 to the input value, converting a PPI index to an INTID. Resolve this by redefining the BSA-allocated PPIs by their INTIDs, and replacing the PPI(x) macro with an INTID_TO_PPI(x) one where required. Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> Message-id: 20230919090229.188092-2-quic_llindhol@quicinc.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/xen: cleanup sourcesetsPaolo Bonzini2023-10-181-1/+0
| | | | | | | | | | | | xen_ss is added unconditionally to arm_ss and i386_ss (the only targets that can have CONFIG_XEN enabled) and its contents are gated by CONFIG_XEN; xen_specific_ss has no condition for its constituent files but is gated on CONFIG_XEN when its added to specific_ss. So xen_ss is a duplicate of xen_specific_ss, though defined in a different way. Merge the two by eliminating xen_ss. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingStefan Hajnoczi2023-10-0311-10/+88
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * fix from optionrom build * fix for KVM on Apple M2 * introduce machine property "audiodev" * ui/vnc: Require audiodev= to enable audio * audio: remove QEMU_AUDIO_* and -audio-help support * audio: forbid using default audiodev backend with -audiodev and -nodefaults * remove compatibility code for old machine types * make-release: do not ship dtc sources * build system cleanups # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmUb0QgUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroOpnAf9EFXfGkXpqQ5Q8ZbVlVc5GQKofMHW # OZwamTBlp/c07+QcQiMxwLhIW0iyDhrfdCjoFSUaTA8O10FM1YrFv4SkUryYb9B3 # bmoTl4NeLvmkxpC47GEeaaBfjyM0G/9Ip9Zsuqx3u+gSzwTbkEstA2u7gcsN0tL9 # VlhMSiV82uHhRC/DJYLxr+8bRYSIm1AeuI8K/O1yags85Kztf3UiQUhePIKLznMH # BdORjD+i46xM1dE8ifpdsunm462cDWz/faAnIH0YVKBlshnQHXKTO+GDA/Fbfl51 # wFfupZXo93wwgawS7elAUzI+gwaKCPRHA8NDcukeO91hTzk6i14y04u5SQ== # =nv64 # -----END PGP SIGNATURE----- # gpg: Signature made Tue 03 Oct 2023 04:30:00 EDT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (24 commits) audio: forbid default audiodev backend with -nodefaults audio: propagate Error * out of audio_init vt82c686 machines: Support machine-default audiodev with fallback hw/ppc: Support machine-default audiodev with fallback hw/arm: Support machine-default audiodev with fallback Introduce machine property "audiodev" audio: remove QEMU_AUDIO_* and -audio-help support audio: simplify flow in audio_init audio: commonize voice initialization audio: return Error ** from audio_state_by_name audio: allow returning an error from the driver init audio: Require AudioState in AUD_add_capture ui/vnc: Require audiodev= to enable audio crypto: only include tls-cipher-suites in emulators scsi-disk: ensure that FORMAT UNIT commands are terminated esp: restrict non-DMA transfer length to that of available data esp: use correct type for esp_dma_enable() in sysbus_esp_gpio_demux() Makefile: build plugins before running TCG tests meson: clean up static_library keyword arguments make-release: do not ship dtc sources ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * audio: propagate Error * out of audio_initMartin Kletzander2023-10-031-1/+1
| | | | | | | | | | | | | | | | | | | | Starting from audio_driver_init, propagate errors via Error ** so that audio_init_audiodevs can simply pass &error_fatal, and AUD_register_card can signal faiure. Signed-off-by: Martin Kletzander <mkletzan@redhat.com> [Reworked the audio/audio.c parts, while keeping Martin's hw/ changes. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * hw/arm: Support machine-default audiodev with fallbackMartin Kletzander2023-10-0311-9/+87
| | | | | | | | | | Signed-off-by: Martin Kletzander <mkletzan@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | aspeed: Clean up local variable shadowingCédric Le Goater2023-09-291-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove superfluous local 'irq' variables and use the one define at the top of the routine. This fixes warnings in aspeed_soc_ast2600_realize() such as : ../hw/arm/aspeed_ast2600.c: In function ‘aspeed_soc_ast2600_realize’: ../hw/arm/aspeed_ast2600.c:420:18: warning: declaration of ‘irq’ shadows a previous local [-Wshadow=compatible-local] 420 | qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); | ^~~ ../hw/arm/aspeed_ast2600.c:312:14: note: shadowed declaration is here 312 | qemu_irq irq; | ^~~ Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-ID: <20230922155924.1172019-3-clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Markus Armbruster <armbru@redhat.com>
* | hw/arm/smmuv3-internal.h: Don't use locals in statement macrosPeter Maydell2023-09-291-29/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The STE_CTXPTR() and STE_S2TTB() macros both extract two halves of an address from fields in the STE and combine them into a single value to return. The current code for this uses a GCC statement expression. There are two problems with this: (1) The type chosen for the variable in the statement expr is 'unsigned long', which might not be 64 bits (2) the name chosen for the variable causes -Wshadow warnings because it's the same as a variable in use at the callsite: In file included from ../../hw/arm/smmuv3.c:34: ../../hw/arm/smmuv3.c: In function ‘smmu_get_cd’: ../../hw/arm/smmuv3-internal.h:538:23: warning: declaration of ‘addr’ shadows a previous local [-Wshadow=compatible-local] 538 | unsigned long addr; \ | ^~~~ ../../hw/arm/smmuv3.c:339:23: note: in expansion of macro ‘STE_CTXPTR’ 339 | dma_addr_t addr = STE_CTXPTR(ste); | ^~~~~~~~~~ ../../hw/arm/smmuv3.c:339:16: note: shadowed declaration is here 339 | dma_addr_t addr = STE_CTXPTR(ste); | ^~~~ Sidestep both of these problems by just using a single expression rather than a statement expr. For CMD_ADDR, we got the type of the variable right but still run into -Wshadow problems: In file included from ../../hw/arm/smmuv3.c:34: ../../hw/arm/smmuv3.c: In function ‘smmuv3_range_inval’: ../../hw/arm/smmuv3-internal.h:334:22: warning: declaration of ‘addr’ shadows a previous local [-Wshadow=compatible-local] 334 | uint64_t addr = high << 32 | (low << 12); \ | ^~~~ ../../hw/arm/smmuv3.c:1104:28: note: in expansion of macro ‘CMD_ADDR’ 1104 | dma_addr_t end, addr = CMD_ADDR(cmd); | ^~~~~~~~ ../../hw/arm/smmuv3.c:1104:21: note: shadowed declaration is here 1104 | dma_addr_t end, addr = CMD_ADDR(cmd); | ^~~~ so convert it too. CD_TTB has neither problem, but it is the only other macro in the file that uses this pattern, so we convert it also for consistency's sake. We use extract64() rather than extract32() to avoid having to explicitly cast the result to uint64_t. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-ID: <20230922152944.3583438-5-peter.maydell@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
* | hw/arm/smmuv3.c: Avoid shadowing variablePeter Maydell2023-09-291-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Avoid shadowing a variable in smmuv3_notify_iova(): ../../hw/arm/smmuv3.c: In function ‘smmuv3_notify_iova’: ../../hw/arm/smmuv3.c:1043:23: warning: declaration of ‘event’ shadows a previous local [-Wshadow=local] 1043 | SMMUEventInfo event = {.inval_ste_allowed = true}; | ^~~~~ ../../hw/arm/smmuv3.c:1038:19: note: shadowed declaration is here 1038 | IOMMUTLBEvent event; | ^~~~~ Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-ID: <20230922152944.3583438-4-peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>