| Commit message (Expand) | Author | Files | Lines |
|---|
| 2024-07-16 | Revert "qemu-char: do not operate on sources from finalize callbacks" | Sergey Dyasli | 1 | -14/+5 |
| 2024-07-16 | i386/sev: Don't allow automatic fallback to legacy KVM_SEV*_INIT | Michael Roth | 3 | -22/+83 |
| 2024-07-14 | hw/ufs: Fix mcq register range check logic | Jeuk Kim | 1 | -2/+14 |
| 2024-07-12 | docs: remove Sphinx 1.x compatibility code | John Snow | 4 | -101/+19 |
| 2024-07-12 | Python: bump minimum sphinx version to 3.4.3 | John Snow | 2 | -5/+4 |
| 2024-07-12 | python: enable testing for 3.13 | John Snow | 2 | -1/+3 |
| 2024-07-12 | iotests: Change imports for Python 3.13 | John Snow | 2 | -4/+12 |
| 2024-07-12 | python: Do not use pylint 3.2.4 with python 3.8 | John Snow | 1 | -0/+1 |
| 2024-07-12 | python: linter changes for pylint 3.x | John Snow | 2 | -1/+2 |
| 2024-07-12 | target/loongarch: Fix cpu_reset set wrong CSR_CRMD | Song Gao | 1 | -3/+3 |
| 2024-07-12 | target/loongarch: Set CSR_PRCFG1 and CSR_PRCFG2 values | Song Gao | 1 | -5/+12 |
| 2024-07-12 | target/loongarch: Remove avail_64 in trans_srai_w() and simplify it | Feiyang Chen | 1 | -12/+3 |
| 2024-07-12 | target/loongarch/kvm: Add software breakpoint support | Bibo Mao | 2 | -0/+77 |
| 2024-07-12 | MAINTAINERS: Add myself as a reviewer of LoongArch virt machine | Jiaxun Yang | 1 | -0/+1 |
| 2024-07-12 | hw/loongarch/virt: Remove unused assignment | Bibo Mao | 1 | -8/+7 |
| 2024-07-12 | hw/loongarch: Change the tpm support by default | Xianglai Li | 2 | -0/+4 |
| 2024-07-12 | hw/loongarch/boot.c: fix out-of-bound reading | Dmitry Frolov | 1 | -1/+1 |
| 2024-07-12 | xen: mapcache: Fix unmapping of first entries in buckets | Edgar E. Iglesias | 1 | -1/+11 |
| 2024-07-12 | physmem: Bail out qemu_ram_block_from_host() for invalid ram addrs | Edgar E. Iglesias | 1 | -0/+4 |
| 2024-07-12 | MAINTAINERS: add Edgar as Xen maintainer | Stefano Stabellini | 1 | -0/+1 |
| 2024-07-11 | hw/nvme: Expand VI/VQ resource to uint32 | Minwoo Im | 2 | -6/+6 |
| 2024-07-11 | hw/nvme: Allocate sec-ctrl-list as a dynamic array | Minwoo Im | 3 | -10/+5 |
| 2024-07-11 | hw/nvme: separate identify data for sec. ctrl list | Minwoo Im | 3 | -21/+22 |
| 2024-07-11 | hw/nvme: add Identify Endurance Group List | Minwoo Im | 2 | -0/+23 |
| 2024-07-11 | hw/nvme: fix BAR size mismatch of SR-IOV VF | Minwoo Im | 1 | -4/+15 |
| 2024-07-11 | hw/nvme: fix number of PIDs for FDP RUH update | Vincent Fu | 1 | -1/+1 |
| 2024-07-11 | hw/nvme: Add support for setting the MQES for the NVMe emulation | John Berg | 2 | -1/+8 |
| 2024-07-11 | target/arm: Convert PMULL to decodetree | Richard Henderson | 2 | -82/+15 |
| 2024-07-11 | target/arm: Convert ADDHN, SUBHN, RADDHN, RSUBHN to decodetree | Richard Henderson | 2 | -71/+61 |
| 2024-07-11 | target/arm: Convert SADDW, SSUBW, UADDW, USUBW to decodetree | Richard Henderson | 2 | -43/+48 |
| 2024-07-11 | target/arm: Convert SQDMULL, SQDMLAL, SQDMLSL to decodetree | Richard Henderson | 2 | -499/+138 |
| 2024-07-11 | target/arm: Convert SADDL, SSUBL, SABDL, SABAL, and unsigned to decodetree | Richard Henderson | 2 | -72/+87 |
| 2024-07-11 | target/arm: Convert SMULL, UMULL, SMLAL, UMLAL, SMLSL, UMLSL to decodetree | Richard Henderson | 2 | -50/+156 |
| 2024-07-11 | hw/arm: In STM32L4x5 SOC, connect USART devices to EXTI | Inès Varhol | 1 | -13/+11 |
| 2024-07-11 | hw/misc: In STM32L4x5 EXTI, handle direct interrupts | Inès Varhol | 1 | -0/+7 |
| 2024-07-11 | hw/misc: In STM32L4x5 EXTI, consolidate 2 constants | Inès Varhol | 2 | -6/+4 |
| 2024-07-11 | accel/tcg: Make TCGCPUOps::cpu_exec_halt mandatory | Peter Maydell | 2 | -9/+11 |
| 2024-07-11 | target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation | Peter Maydell | 19 | -1/+24 |
| 2024-07-11 | target/arm: Set arm_v7m_tcg_ops cpu_exec_halt to arm_cpu_exec_halt() | Peter Maydell | 3 | -1/+5 |
| 2024-07-11 | target/arm: Use cpu_env in cpu_untagged_addr | Richard Henderson | 1 | -2/+2 |
| 2024-07-11 | hw/misc/bcm2835_thermal: Fix access size handling in bcm2835_thermal_ops | Zheyu Ma | 1 | -0/+2 |
| 2024-07-11 | hw/char/pl011: Avoid division-by-zero in pl011_get_baudrate() | Zheyu Ma | 1 | -2/+11 |
| 2024-07-11 | target/arm: Allow FPCR bits that aren't in FPSCR | Peter Maydell | 1 | -21/+35 |
| 2024-07-11 | target/arm: Rename FPSR_MASK and FPCR_MASK and define them symbolically | Peter Maydell | 3 | -11/+40 |
| 2024-07-11 | target/arm: Rename FPCR_ QC, NZCV macros to FPSR_ | Peter Maydell | 5 | -24/+27 |
| 2024-07-11 | target/arm: Store FPSR and FPCR in separate CPU state fields | Peter Maydell | 6 | -27/+28 |
| 2024-07-11 | target/arm: Implement store_cpu_field_low32() macro | Peter Maydell | 1 | -0/+7 |
| 2024-07-11 | target/arm: Support migration when FPSR/FPCR won't fit in the FPSCR | Peter Maydell | 1 | -2/+132 |
| 2024-07-11 | target/arm: Make vfp_set_fpscr() call vfp_set_{fpcr, fpsr} | Peter Maydell | 2 | -44/+78 |
| 2024-07-11 | target/arm: Make vfp_get_fpscr() call vfp_get_{fpcr, fpsr} | Peter Maydell | 2 | -21/+37 |