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2023-11-06mc146818rtc: rtc_set_time(): initialize tm to zeroesVladimir Sementsov-Ogievskiy1-1/+1
set_time() function doesn't set all the fields, so it's better to initialize tm structure. And Coverity will be happier about it. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Maksim Davydov <davydov-max@yandex-team.ru> Message-id: 20231017125941.810461-4-vsementsov@yandex-team.ru Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-11-06util/filemonitor-inotify: qemu_file_monitor_watch(): assert no overflowVladimir Sementsov-Ogievskiy1-8/+17
Prefer clear assertions instead of [im]possible array overflow. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Maksim Davydov <davydov-max@yandex-team.ru> Message-id: 20231017125941.810461-3-vsementsov@yandex-team.ru Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-11-06hw/i386/intel_iommu: vtd_slpte_nonzero_rsvd(): assert no overflowVladimir Sementsov-Ogievskiy1-3/+20
We support only 3- and 4-level page-tables, which is firstly checked in vtd_decide_config(), then setup in vtd_init(). Than level fields are checked by vtd_is_level_supported(). So here we can't have level out from 1..4 inclusive range. Let's assert it. That also explains Coverity that we are not going to overflow the array. CID: 1487158, 1487186 Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Maksim Davydov <davydov-max@yandex-team.ru> Message-id: 20231017125941.810461-2-vsementsov@yandex-team.ru Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-11-06tests/qtest/bios-tables-test: Update virt SPCR and DBG2 golden referencesPeter Maydell3-2/+0
Update the virt SPCR and DBG2 golden reference files to have the fix for the description of the UART. Diffs from iasl: @@ -1,57 +1,57 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/virt/SPCR, Fri Nov 3 14:12:06 2023 + * Disassembly of /tmp/aml-E6YUD2, Fri Nov 3 14:12:06 2023 * * ACPI Data Table [SPCR] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */ [000h 0000 4] Signature : "SPCR" [Serial Port Console Redirection table] [004h 0004 4] Table Length : 00000050 [008h 0008 1] Revision : 02 -[009h 0009 1] Checksum : CB +[009h 0009 1] Checksum : B1 [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 [024h 0036 1] Interface Type : 03 [025h 0037 3] Reserved : 000000 [028h 0040 12] Serial Port Register : [Generic Address Structure] [028h 0040 1] Space ID : 00 [SystemMemory] -[029h 0041 1] Bit Width : 08 +[029h 0041 1] Bit Width : 20 [02Ah 0042 1] Bit Offset : 00 -[02Bh 0043 1] Encoded Access Width : 01 [Byte Access:8] +[02Bh 0043 1] Encoded Access Width : 03 [DWord Access:32] [02Ch 0044 8] Address : 0000000009000000 [034h 0052 1] Interrupt Type : 08 [035h 0053 1] PCAT-compatible IRQ : 00 [036h 0054 4] Interrupt : 00000021 [03Ah 0058 1] Baud Rate : 03 [03Bh 0059 1] Parity : 00 [03Ch 0060 1] Stop Bits : 01 [03Dh 0061 1] Flow Control : 02 [03Eh 0062 1] Terminal Type : 00 [04Ch 0076 1] Reserved : 00 [040h 0064 2] PCI Device ID : FFFF [042h 0066 2] PCI Vendor ID : FFFF [044h 0068 1] PCI Bus : 00 [045h 0069 1] PCI Device : 00 [046h 0070 1] PCI Function : 00 [047h 0071 4] PCI Flags : 00000000 [04Bh 0075 1] PCI Segment : 00 [04Ch 0076 4] Reserved : 00000000 Raw Table Data: Length 80 (0x50) - 0000: 53 50 43 52 50 00 00 00 02 CB 42 4F 43 48 53 20 // SPCRP.....BOCHS + 0000: 53 50 43 52 50 00 00 00 02 B1 42 4F 43 48 53 20 // SPCRP.....BOCHS 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC - 0020: 01 00 00 00 03 00 00 00 00 08 00 01 00 00 00 09 // ................ + 0020: 01 00 00 00 03 00 00 00 00 20 00 03 00 00 00 09 // ......... ...... 0030: 00 00 00 00 08 00 21 00 00 00 03 00 01 02 00 00 // ......!......... 0040: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00 // ................ @@ -1,57 +1,57 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/virt/DBG2, Fri Nov 3 14:12:06 2023 + * Disassembly of /tmp/aml-V1YUD2, Fri Nov 3 14:12:06 2023 * * ACPI Data Table [DBG2] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */ [000h 0000 4] Signature : "DBG2" [Debug Port table type 2] [004h 0004 4] Table Length : 00000057 [008h 0008 1] Revision : 00 -[009h 0009 1] Checksum : CF +[009h 0009 1] Checksum : B5 [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 [024h 0036 4] Info Offset : 0000002C [028h 0040 4] Info Count : 00000001 [02Ch 0044 1] Revision : 00 [02Dh 0045 2] Length : 002B [02Fh 0047 1] Register Count : 01 [030h 0048 2] Namepath Length : 0005 [032h 0050 2] Namepath Offset : 0026 [034h 0052 2] OEM Data Length : 0000 [Optional field not present] [036h 0054 2] OEM Data Offset : 0000 [Optional field not present] [038h 0056 2] Port Type : 8000 [03Ah 0058 2] Port Subtype : 0003 [03Ch 0060 2] Reserved : 0000 [03Eh 0062 2] Base Address Offset : 0016 [040h 0064 2] Address Size Offset : 0022 [042h 0066 12] Base Address Register : [Generic Address Structure] [042h 0066 1] Space ID : 00 [SystemMemory] -[043h 0067 1] Bit Width : 08 +[043h 0067 1] Bit Width : 20 [044h 0068 1] Bit Offset : 00 -[045h 0069 1] Encoded Access Width : 01 [Byte Access:8] +[045h 0069 1] Encoded Access Width : 03 [DWord Access:32] [046h 0070 8] Address : 0000000009000000 [04Eh 0078 4] Address Size : 00001000 [052h 0082 5] Namepath : "COM0" Raw Table Data: Length 87 (0x57) - 0000: 44 42 47 32 57 00 00 00 00 CF 42 4F 43 48 53 20 // DBG2W.....BOCHS + 0000: 44 42 47 32 57 00 00 00 00 B5 42 4F 43 48 53 20 // DBG2W.....BOCHS 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC 0020: 01 00 00 00 2C 00 00 00 01 00 00 00 00 2B 00 01 // ....,........+.. 0030: 05 00 26 00 00 00 00 00 00 80 03 00 00 00 16 00 // ..&............. - 0040: 22 00 00 08 00 01 00 00 00 09 00 00 00 00 00 10 // "............... + 0040: 22 00 00 20 00 03 00 00 00 09 00 00 00 00 00 10 // ".. ............ 0050: 00 00 43 4F 4D 30 00 // ..COM0. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-11-06hw/arm/virt: Report correct register sizes in ACPI DBG2/SPCR tables.Udo Steinberg1-2/+2
Documentation for using the GAS in ACPI tables to report debug UART addresses at https://learn.microsoft.com/en-us/windows-hardware/drivers/bringup/acpi-debug-port-table states the following: - The Register Bit Width field contains the register stride and must be a power of 2 that is at least as large as the access size. On 32-bit platforms this value cannot exceed 32. On 64-bit platforms this value cannot exceed 64. - The Access Size field is used to determine whether byte, WORD, DWORD, or QWORD accesses are to be used. QWORD accesses are only valid on 64-bit architectures. Documentation for the ARM PL011 at https://developer.arm.com/documentation/ddi0183/latest/ states that the registers are: - spaced 4 bytes apart (see Table 3-2), so register stride must be 32. - 16 bits in size in some cases (see individual registers), so access size must be at least 2. Linux doesn't seem to care about this error in the table, but it does affect at least the NOVA microhypervisor. In theory we therefore have a choice between reporting the access size as 2 (16 bit accesses) or 3 (32-bit accesses). In practice, Linux does not correctly handle the case where the table reports the access size as 2: as of kernel commit 750b95887e5678, the code in acpi_parse_spcr() tries to tell the serial driver to use 16 bit accesses by passing "mmio16" in the option string, but the PL011 driver code in pl011_console_match() only recognizes "mmio" or "mmio32". The result is that unless the user has enabled 'earlycon' there is no console output from the guest kernel. We therefore choose to report the access size as 32 bits; this works for NOVA and also for Linux. It is also what the UEFI firmware on a Raspberry Pi 4 reports, so we're in line with existing real-world practice. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1938 Signed-off-by: Udo Steinberg <udo@hypervisor.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: minor commit message tweaks; use 32 bit accesses] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-11-06tests/qtest/bios-tables-test: Allow changes to virt SPCR and DBG2Peter Maydell1-0/+2
Allow changes to the virt board SPCR and DBG2 -- we are going to fix an error in the UART descriptions there. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-11-06hw/arm/virt: fix PMU IRQ registrationSebastian Ott1-1/+2
Since commit 9036e917f8 ("{include/}hw/arm: refactor virt PPI logic") PMU IRQ registration fails for arm64 guests: [ 0.563689] hw perfevents: unable to request IRQ14 for ARM PMU counters [ 0.565160] armv8-pmu: probe of pmu failed with error -22 That commit re-defined VIRTUAL_PMU_IRQ to be a INTID but missed a case where the PMU IRQ is actually referred by its PPI index. Fix that by using INTID_TO_PPI() in that case. Fixes: 9036e917f8 ("{include/}hw/arm: refactor virt PPI logic") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1960 Signed-off-by: Sebastian Ott <sebott@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 475d918d-ab0e-f717-7206-57a5beb28c7b@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-11-05target/sparc: Check for invalid cond in gen_compare_regRichard Henderson1-19/+26
Consolidate the test here; drop the "inverted logic". Fix MOVr and FMOVR, which were missing the invalid test. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05target/sparc: Implement UDIV inlineRichard Henderson2-14/+56
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05target/sparc: Implement UDIVX and SDIVX inlineRichard Henderson4-44/+97
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05target/sparc: Discard cpu_cond at the end of each insnRichard Henderson1-0/+27
If the insn raises no exceptions, there will be no path in which cpu_cond is used, and so the computation may be optimized away. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05target/sparc: Record entire jump condition in DisasContextRichard Henderson1-11/+16
Use the original condition instead of consuming cpu_cond, which will now only be live along exception paths. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05target/sparc: Merge gen_op_next_insn into only callerRichard Henderson1-7/+2
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05target/sparc: Pass displacement to advance_jump_condRichard Henderson1-7/+5
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05target/sparc: Merge advance_jump_uncond_{never,always} into advance_jump_condRichard Henderson1-44/+30
Handle these via TCG_COND_{ALWAYS,NEVER}. Allow dc->npc to be variable, using gen_mov_pc_npc. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05target/sparc: Merge gen_branch2 into advance_pcRichard Henderson1-14/+14
The function had only one caller. Canonicalize the cpu_cond test to TCG_COND_NE, the "natural" sense of its value. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05target/sparc: Do flush_cond in advance_jump_condRichard Henderson1-6/+4
Do this here instead of in each caller. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05target/sparc: Always copy conditions into a new temporaryRichard Henderson1-1/+2
This will allow the condition to live across changes to the global cc variables. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05target/sparc: Change DisasCompare.c2 to intRichard Henderson1-15/+18
We don't require c2 to be variable, so emphasize that. We don't currently require c2 to be non-zero, but that will change. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05target/sparc: Remove DisasCompare.is_boolRichard Henderson1-15/+7
Since we're going to feed cpu_cond to another comparison, we don't reqire a boolean value -- anything non-zero is sufficient. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05target/sparc: Remove CC_OP leftoversRichard Henderson10-178/+26
All instructions have been converted to generate full condition codes explicitly. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05target/sparc: Remove CC_OP_TADDTV, CC_OP_TSUBTVRichard Henderson4-200/+32
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05target/sparc: Remove CC_OP_SUB, CC_OP_SUBX, CC_OP_TSUBRichard Henderson3-261/+42
These are all related and implementable with common code. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05target/sparc: Remove CC_OP_ADD, CC_OP_ADDX, CC_OP_TADDRichard Henderson3-255/+87
These are all related and implementable with common code. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05target/sparc: Remove CC_OP_DIVRichard Henderson5-110/+93
Return both result and overflow from helper_[us]div. Compute all flags explicitly in gen_op_[us]divcc. Marginally improve the INT64_MIN special case in helper_sdiv. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05target/sparc: Remove CC_OP_LOGICRichard Henderson3-53/+28
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05target/sparc: Split psr and xcc into componentsRichard Henderson7-270/+289
Step in removing CC_OP: change the representation of CC_OP_FLAGS. The 8 bits are distributed between 6 variables, which should make it easy to keep up to date. The code within cc_helper.c is quite ugly but is only temporary. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05target/sparc: Introduce cpu_put_psr_iccRichard Henderson3-2/+8
Isolate linux-user from changes to icc representation. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-03migration: Unlock mutex in error caseJuan Quintela1-52/+52
We were not unlocking bitmap mutex on the error case. To fix it forever change to enclose the code with WITH_QEMU_LOCK_GUARD(). Coverity CID 1523750. Fixes: a2326705e5 ("migration: Stop migration immediately in RDMA error paths") Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <20231103074245.55166-1-quintela@redhat.com>
2023-11-03docs/migration: Add the dirty limit sectionHyman Huang1-0/+71
The dirty limit feature has been introduced since the 8.1 QEMU release but has not reflected in the document, add a section for that. Signed-off-by: Hyman Huang <yong.huang@smartx.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <0f2b2c63fec22ea23e4926cdeb567b7a0ebd8152.1698847223.git.yong.huang@smartx.com>
2023-11-03tests/migration: Introduce dirty-limit into guestperfHyman Huang5-4/+81
Currently, guestperf does not cover the dirty-limit migration, support this feature. Note that dirty-limit requires 'dirty-ring-size' set. To enable dirty-limit, setting x-vcpu-dirty-limit-period as 500ms and x-vcpu-dirty-limit as 10MB/s: $ ./tests/migration/guestperf.py \ --dirty-ring-size 4096 \ --dirty-limit --x-vcpu-dirty-limit-period 500 \ --vcpu-dirty-limit 10 --output output.json \ To run the entire standardized set of dirty-limit-enabled comparisons, with unix migration: $ ./tests/migration/guestperf-batch.py \ --dirty-ring-size 4096 \ --dst-host localhost --transport unix \ --filter compr-dirty-limit* --output outputdir Signed-off-by: Hyman Huang <yong.huang@smartx.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Message-Id: <516e7a55dfc6e33d33510be37eb24223de5dc072.1697815117.git.yong.huang@smartx.com> Message-ID: <e1283565b00b34b0377bbd27bee4bb8fc7c255a8.1698847223.git.yong.huang@smartx.com> Signed-off-by: Juan Quintela <quintela@redhat.com>
2023-11-03tests/migration: Introduce dirty-ring-size option into guestperfHyman Huang3-4/+16
Dirty ring size configuration is not supported by guestperf tool. Introduce dirty-ring-size (ranges in [1024, 65536]) option so developers can play with dirty-ring and dirty-limit feature easier. To set dirty ring size with 4096 during migration test: $ ./tests/migration/guestperf.py --dirty-ring-size 4096 xxx Signed-off-by: Hyman Huang <yong.huang@smartx.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <8a388cec5c1f73a34d42515bbc43837e97ee3839.1698847223.git.yong.huang@smartx.com>
2023-11-03tests: Add migration dirty-limit capability testHyman Huang1-0/+164
Add migration dirty-limit capability test if kernel support dirty ring. Migration dirty-limit capability introduce dirty limit capability, two parameters: x-vcpu-dirty-limit-period and vcpu-dirty-limit are introduced to implement the live migration with dirty limit. The test case does the following things: 1. start src, dst vm and enable dirty-limit capability 2. start migrate and set cancel it to check if dirty limit stop working. 3. restart dst vm 4. start migrate and enable dirty-limit capability 5. check if migration satisfy the convergence condition during pre-switchover phase. Note that this test case involves many passes, so it runs in slow mode only. Signed-off-by: Hyman Huang <yong.huang@smartx.com> Acked-by: Peter Xu <peterx@redhat.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <e55a302df9da7dbc00ad825f47f57c1a756d303e.1698847223.git.yong.huang@smartx.com>
2023-11-03system/dirtylimit: Drop the reduplicative checkHyman Huang1-4/+0
Checking if dirty limit is in service is done by the dirtylimit_query_all function, drop the reduplicative check in the qmp_query_vcpu_dirty_limit function. Signed-off-by: Hyman Huang <yong.huang@smartx.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <df9c3514933ff6750ef88068af18d3054bedf746.1698847223.git.yong.huang@smartx.com>
2023-11-03system/dirtylimit: Fix a race situationHyman Huang1-6/+14
Fix a race situation for global variable dirtylimit_state. Also, replace usleep by g_usleep to increase platform accessibility to the sleep function. Signed-off-by: Hyman Huang <yong.huang@smartx.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <27c86239e21eda03d11ce5a3d07da3c229f562e3.1698847223.git.yong.huang@smartx.com>
2023-11-03linux-user/loongarch64: Add LASX sigcontext save/restoreSong Gao1-6/+62
Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231101030816.2353416-7-gaosong@loongson.cn>
2023-11-03linux-user/loongarch64: Add LSX sigcontext save/restoreSong Gao1-20/+87
Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231101030816.2353416-6-gaosong@loongson.cn>
2023-11-03linux-user/loongarch64: Use abi_{ulong,uint} typesSong Gao1-12/+12
Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231101030816.2353416-5-gaosong@loongson.cn>
2023-11-03linux-user/loongarch64: setup_sigframe() set 'end' context size 0Song Gao1-1/+1
See: https://github.com/torvalds/linux/blob/master/arch/loongarch/kernel/signal.c The kernel setup_sigcontext() set end context size 0. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231101030816.2353416-4-gaosong@loongson.cn>
2023-11-03linux-user/loongarch64: Fix setup_extcontext alloc wrong fpu_context sizeSong Gao1-1/+1
See: https://github.com/torvalds/linux/blob/master/arch/loongarch/kernel/signal.c The alloc size is sizeof(struct target_fpu_context). Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231101030816.2353416-3-gaosong@loongson.cn>
2023-11-03linux-user/loongarch64: Use traps to track LSX/LASX usageRichard Henderson2-11/+13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231101030816.2353416-2-gaosong@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2023-11-03target/loongarch: Support 4K page sizeSong Gao2-6/+5
The LoongArch kernel supports 4K page size. Change TARGET_PAGE_BITS to 12. Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20231023024059.3858349-1-gaosong@loongson.cn>
2023-11-03target/loongarch: Implement query-cpu-model-expansionSong Gao2-2/+68
Add support for the query-cpu-model-expansion QMP command to LoongArch. We support query the cpu features. e.g la464 and max cpu support LSX/LASX, default enable, la132 not support LSX/LASX. 1. start with '-cpu max,lasx=off' (QEMU) query-cpu-model-expansion type=static model={"name":"max"} {"return": {"model": {"name": "max", "props": {"lasx": false, "lsx": true}}}} 2. start with '-cpu la464,lasx=off' (QEMU) query-cpu-model-expansion type=static model={"name":"la464"} {"return": {"model": {"name": "max", "props": {"lasx": false, "lsx": true}}} 3. start with '-cpu la132,lasx=off' qemu-system-loongarch64: can't apply global la132-loongarch-cpu.lasx=off: Property 'la132-loongarch-cpu.lasx' not found 4. start with '-cpu max,lasx=off' or start with '-cpu la464,lasx=off' query cpu model la132 (QEMU) query-cpu-model-expansion type=static model={"name":"la132"} {"return": {"model": {"name": "la132"}}} Acked-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231020084925.3457084-4-gaosong@loongson.cn>
2023-11-03target/loongarch: Allow user enable/disable LSX/LASX featuresSong Gao2-0/+69
Some users may not need LSX/LASX, this patch allows the user enable/disable LSX/LASX features. e.g '-cpu max,lsx=on,lasx=on' (default); '-cpu max,lsx=on,lasx=off' (enabled LSX); '-cpu max,lsx=off,lasx=on' (enabled LASX, LSX); '-cpu max,lsx=off' (disable LSX and LASX). Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231020084925.3457084-3-gaosong@loongson.cn>
2023-11-03target/loongarch: Add cpu model 'max'Song Gao1-0/+7
We use cpu la464 for the 'max' cpu. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231020084925.3457084-2-gaosong@loongson.cn>
2023-11-02tests/qtest: Introduce tests for AMD/Xilinx Versal TRNG deviceTong Ho2-1/+486
Signed-off-by: Tong Ho <tong.ho@amd.com> Message-id: 20231031184611.3029156-4-tong.ho@amd.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-11-02hw/arm: xlnx-versal-virt: Add AMD/Xilinx TRNG deviceTong Ho3-0/+22
Connect the support for Versal True Random Number Generator (TRNG) device. Warning: unlike the TRNG component in a real device from the Versal device familiy, the connected TRNG model is not of cryptographic grade and is not intended for use cases when cryptograpically strong TRNG is needed. Signed-off-by: Tong Ho <tong.ho@amd.com> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20231031184611.3029156-3-tong.ho@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-11-02hw/misc: Introduce AMD/Xilix Versal TRNG deviceTong Ho4-0/+781
This adds a non-cryptographic grade implementation of the model for the True Random Number Generator (TRNG) component in AMD/Xilinx Versal device family. This implements all 3 modes defined by the actual hardware specs, all of which selectable by guest software at will at anytime: 1) PRNG mode, in which the generated sequence is required to be reproducible after reseeded by the same 384-bit value as supplied by guest software. 2) Test mode, in which the generated sequence is required to be reproducible ater reseeded by the same 128-bit test seed supplied by guest software. 3) TRNG mode, in which non-reproducible sequence is generated based on periodic reseed by a suitable entropy source. This model is only intended for non-real world testing of guest software, where cryptographically strong PRNG or TRNG is not needed. This model supports versions 1 & 2 of the device, with default to be version 2; the 'hw-version' uint32 property can be set to 0x0100 to override the default. Other implemented properties: - 'forced-prng', uint64 When set to non-zero, mode 3's entropy source is implemented as a deterministic sequence based on the given value and other deterministic parameters. This option allows the emulation to test guest software using mode 3 and to reproduce data-dependent defects. - 'fips-fault-events', uint32, bit-mask bit 3: Triggers the SP800-90B entropy health test fault irq bit 1: Triggers the FIPS 140-2 continuous test fault irq Signed-off-by: Tong Ho <tong.ho@amd.com> Message-id: 20231031184611.3029156-2-tong.ho@amd.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-11-02dump: Drop redundant check for empty dumpMarkus Armbruster1-26/+0
dump_init() first computes the size of the dump, taking the filter area into account, and fails if its zero. It then looks for memory in the filter area, and fails if there is none. This is redundant: if the size of the dump is zero, there is no memory, and vice versa. Delete this check. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20231031104531.3169721-6-armbru@redhat.com>
2023-11-02dump: Improve some dump-guest-memory error messagesMarkus Armbruster1-11/+7
Zero @length is rejected with "Invalid parameter 'length'". Improve to "parameter 'length' expects a non-zero length". qemu_open_old() is a wrapper around qemu_open_internal() that throws away error information. Switch to the wrapper that doesn't: qemu_create(). Example improvement: (qemu) dump-guest-memory /dev/fdset/x 0 1 Error: Could not open '/dev/fdset/x': Invalid argument becomes Error: Could not parse fdset /dev/fdset/x @protocol values not starting with "fd:" or "file:" are rejected with "Invalid parameter 'protocol'". Improve to "parameter 'protocol' must start with 'file:' or 'fd:'". While there, make the conditional checking @protocol a little more obvious. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20231031104531.3169721-5-armbru@redhat.com>