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2025-10-07target/arm: GPT_Secure is reserved without FEAT_SEL2Richard Henderson1-4/+8
For GPT_Secure, if SEL2 is not enabled, raise a GPCF_Walk exception. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250926001134.295547-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07target/arm: Add cur_space to S1TranslateRichard Henderson1-18/+19
We've been updating in_space and then using hacks to access the original space. Instead, update cur_space and leave in_space unchanged. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250926001134.295547-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07target/arm: Enable FEAT_RME_GPC2 bits in gpccr_writeRichard Henderson1-0/+5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250926001134.295547-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07target/arm: Add GPCCR fields from ARM revision L.bRichard Henderson1-0/+6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250926001134.295547-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07target/arm: Add isar feature test for FEAT_RME_GPC2Richard Henderson1-0/+5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250926001134.295547-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/arm: Remove sl_bootparam_write() and 'hw/arm/sharpsl.h' headerPhilippe Mathieu-Daudé3-60/+0
When removing the spitz and tosa board, commit b62151489ae ("hw/arm: Remove deprecated akita, borzoi spitz, terrier, tosa boards") removed the last calls to sl_bootparam_write(). Remove it, along with the "hw/arm/sharpsl.h" header. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20251001084047.67423-1-philmd@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/arm/xlnx-zynqmp: wire a second GIC for the Cortex-R5Frederic Konrad2-1/+80
This wires a second GIC for the Cortex-R5, all the IRQs are split when there is an RPU instanciated. Signed-off-by: Clément Chigot <chigot@adacore.com> Acked-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-id: 20250930115718.437100-4-chigot@adacore.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/arm/xlnx-zynqmp: introduce helper to compute RPU numberClément Chigot1-3/+12
This helper will avoid repeating the MIN/MAX formula everytime the number of RPUs available is requested. Signed-off-by: Clément Chigot <chigot@adacore.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-id: 20250930115718.437100-3-chigot@adacore.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/arm/xlnx-zynqmp: move GIC_NUM_SPI_INTR define in headerClément Chigot2-6/+6
This define will be needed in a later patch in XlnxZynqMPState structure, hence move it within xlnx-zynqmp header. Add XLXN_ZYNQMP prefix as it's now public. Signed-off-by: Clément Chigot <chigot@adacore.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-id: 20250930115718.437100-2-chigot@adacore.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07tests/functional/test_aarch64_xlnx_versal: test the versal2 machineLuc Michel1-2/+8
Add a test for the amd-versal2-virt machine using the same command line, kernel, initrd than the ones used for amd-versal-virt. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-48-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/arm/xlnx-versal-virt: add the xlnx-versal2-virt machineLuc Michel2-10/+76
Add the Versal Gen 2 Virtual development machine embedding a versal2 SoC. This machine follows the same principle than the xlnx-versal-virt machine. It creates its own DTB and feeds it to the software payload. This way only implemented devices are exposed to the guest and the user does not need to provide a DTB. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-47-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07docs/system/arm/xlnx-versal-virt: add a note about dumpdtbLuc Michel1-1/+7
Add a note in the DTB section explaining how to dump the generated DTB using the dumpdtb machine option. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-46-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07docs/system/arm/xlnx-versal-virt: update supported devicesLuc Michel1-2/+5
Update the list of supported devices in the Versal SoCs. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-45-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/arm/xlnx-versal-virt: tidy upLuc Michel1-25/+0
Remove now unused clock nodes. They have been replaced by the ones created in the SoC. Remove the unused cfg.secure VersalVirt field. Remove unecessary include directives. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-44-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/arm/xlnx-versal-virt: split into base/concrete classesLuc Michel1-22/+52
Split the xlnx-versal-virt machine type into a base abstract type and a concrete type. There is no functional change. This is in preparation for the versal2 machine. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-43-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/arm/xlnx-versal-virt: rename the machine to amd-versal-virtLuc Michel3-18/+25
To align with current branding and ensure coherency with the upcoming versal2 machine, rename the xlnx-versal-virt machine to amd-versal-virt. Keep an alias of the old name to the new one for command-line backward compatibility. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-42-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/arm/xlnx-versal: add versal2 SoCLuc Michel2-15/+209
Add the Versal Gen 2 (versal2) version of the Versal SoC family. This version embeds up to 8 Cortex-A78AE cores (split into 4 clusters) and 10 Cortex-R52 cores (split into 5 clusters). The similarities between versal and versal2 in term of architecture allow to reuse the VersalMap structure to almost fully describe the implemented parts of versal2. The versal2 eFuse device differs quite a lot from the versal one and is left as future work. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-41-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07target/arm/tcg/cpu64: add the cortex-a78ae CPULuc Michel1-0/+78
Add support for the ARM Cortex-A78AE CPU. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-40-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/arm/xlnx-versal: add the target field in IRQ descriptorLuc Michel1-2/+39
Add the target field in the IRQ descriptor. This allows to target an IRQ to another IRQ controller than the GIC(s). Other supported targets are the PMC PPU1 CPU interrupt controller and the EAM (Error management) device. Those two devices are currently not implemented so IRQs targeting those will be left unconnected. This is in preparation for versal2. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-39-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/arm/xlnx-versal: add a per_cluster_gic switch to VersalCpuClusterMapLuc Michel1-2/+13
Add the per_cluster_gic switch to the VersalCpuClusterMap structure. When set, this indicates that a GIC instance should by created per-cluster instead of globally for the whole RPU or APU. This is in preparation for versal2. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-38-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/misc/xlnx-versal-crl: add the versal2 versionLuc Michel3-0/+722
Add the versal2 version of the CRL device. For the implemented part, it is similar to the versal version but drives reset line of more devices. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-37-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/arm/xlnx-versal: tidy upLuc Michel2-225/+7
Remove now unused macros in xlnx-versal.[ch]. Those macros have been replaced by the VersalMap structure that serves as a central description for the SoC. The ones still in use in the versal_unimp function are inlined. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-36-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/arm/xlnx-versal: use hw/arm/bsa.h for timer IRQ indicesLuc Michel2-17/+17
Use the bsa.h header for ARM timer and maintainance IRQ indices instead of redefining our owns. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-35-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/arm/xlnx-versal: reconnect the CRL to the other devicesLuc Michel1-1/+30
The CRL connects to various devices through link properties to be able to reset them. The connections were dropped during the SoC refactoring. Reintroduce them now. Rely on the QOM tree to retrieve the devices to connect. The component parts of the device names are chosen to match the properties on the CRL. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-34-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/misc/xlnx-versal-crl: refactor device reset logicLuc Michel2-79/+92
Refactor the device reset logic to have a common register write callback for all the devices. This uses a decode function to map the register address to the actual peripheral to reset. This refactoring changes the CPU property name from cpu_r5[*] to rpu[*] to ease with the connections in the Versal SoC. It also fixes a bug where the gem device pointer was mapped to the usb link property. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-33-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/misc/xlnx-versal-crl: split into base/concrete classesLuc Michel2-21/+58
Split the TYPE_XLNX_VERSAL_CRL type into base and concrete classes. This is in preparation for the versal2 version of the CRL. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-32-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/misc/xlnx-versal-crl: remove unnecessary include directivesLuc Michel1-4/+1
Drop unused include directives from xlnx-versal-crl.c Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-31-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/arm/xlnx-versal: add the versal_get_num_cpu accessorLuc Michel3-3/+13
Add the versal_get_num_cpu accessor to the Versal SoC to retrieve the number of CPUs in the SoC. Use it in the xlnx-versal-virt machine. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-30-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/arm/xlnx-versal: ddr: refactor creationLuc Michel3-106/+53
Refactor the DDR aperture regions creation using the VersalMap structure. Device creation and FDT node creation are split into two functions because the later must happen during ARM virtual bootloader modify_dtb callback. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-29-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/arm/xlnx-versal: ocm: refactor creationLuc Michel2-8/+16
Refactor the OCM creation using the VersalMap structure. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-28-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/arm/xlnx-versal: rpu: refactor creationLuc Michel3-46/+26
Refactor the RPU cluster creation using the VersalMap structure. This effectively instantiate the RPU GICv2 which was not instantiated before. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-27-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/arm/xlnx-versal: add support for GICv2Luc Michel1-20/+62
Add support for GICv2 instantiation in the Versal SoC. This is in preparation for the RPU refactoring. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-26-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/arm/xlnx-versal: add support for multiple GICsLuc Michel2-4/+53
The Versal SoC contains two GICs: one GICv3 in the APU and one GICv2 in the RPU (currently not instantiated). To prepare for the GICv2 instantiation, add support for multiple GICs when connecting interrupts. When a GIC is created, the first-cpu-index property is set on it, and a pointer to the GIC is stored in the intc array. When connecting an IRQ, a TYPE_SPLIT_IRQ device is created with its num-lines property set to the number of GICs in the SoC. The split device is used to fan out the IRQ to all the GICs. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-25-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/intc/arm_gicv3: Introduce a 'first-cpu-index' propertyFrancisco Iglesias4-2/+10
Introduce a 'first-cpu-index' property for specifying the first QEMU CPU connected to the GICv3. This makes it possible to have multiple instances of the GICv3 connected to different CPU clusters. For KVM, mark this property has unsupported. It probably does not make much sense as it is intented to be used to model non-SMP systems. Signed-off-by: Luc Michel <luc.michel@amd.com> Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Sai Pavan Boddu <sai.pavan.boddu@amd.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-24-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/arm/xlnx-versal: instantiate the GIC ITS in the APULuc Michel1-0/+50
Add the instance of the GIC ITS in the APU. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-23-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/arm/xlnx-versal: add the mp_affinity property to the CPU mappingLuc Michel1-0/+16
Add a way to configure the MP affinity value of the CPUs given their core and cluster IDs. For the Versal APU CPUs, the MP affinity value is given by the core ID in Aff0. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-22-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/arm/xlnx-versal: refactor CPU cluster creationLuc Michel3-170/+276
Refactor the CPU cluster creation using the VersalMap structure. There is no functional change. The clusters properties are now described in the VersalMap structure. For now only the APU is converted. The RPU will be taken care of by next commits. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-21-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/arm/xlnx-versal-virt: virtio: refactor creationLuc Michel3-19/+41
Refactor the creation of virtio devices. Use the accessors provided by the Versal SoC to retrieve the reserved MMIO and IRQ space. Those are defined in the VersalMap structure. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-20-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/arm/xlnx-versal: crl: refactor creationLuc Michel2-20/+19
Refactor the CRL device creation using the VersalMap structure. The connections to the RPU CPUs are temporarily removed and will be reintroduced with next refactoring commits. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-19-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/arm/xlnx-versal: cfu: refactor creationLuc Michel2-155/+113
Refactor the CFU device creation using the VersalMap structure. All users of the APB IRQ OR gate have now been converted. The OR gate device can be dropped. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-18-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/arm/xlnx-versal: rtc: refactor creationLuc Michel3-33/+31
Refactor the RTC device creation using the VersalMap structure. The sysbus IRQ output 0 (APB IRQ) is connected instead of the output 1 (addr error IRQ). This does not change the current behaviour since the RTC model does not implement those IRQs anyway. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-17-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/arm/xlnx-versal: trng: refactor creationLuc Michel2-10/+10
Refactor the TRNG device creation using the VersalMap structure. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-16-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/arm/xlnx-versal: bbram: refactor creationLuc Michel3-38/+33
Refactor the BBRAM device creation using the VersalMap structure. Note that the corresponding FDT node is removed. It does not correspond to any real node in standard Versal DTBs. No matching drivers exist for it. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-15-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/arm/xlnx-versal: PMC IOU SCLR: refactor creationLuc Michel2-25/+28
Refactor the PMC IOU SLCR device creation using the VersalMap structure. This is the first user of a shared IRQ using an OR gate. The OSPI controller is reconnected to the SLCR. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-14-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/arm/xlnx-versal: VersalMap: add support for OR'ed IRQsLuc Michel1-1/+62
Improve the IRQ index in the VersalMap structure to turn it into a descriptor: - the lower 16 bits still represent the IRQ index - bit 18 is used to indicate a shared IRQ connected to a OR gate - bits 19 to 22 indicate the index on the OR gate. This allows to share an IRQ among multiple devices. An OR gate is created to connect the devices to the actual IRQ pin. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-13-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/arm/xlnx-versal: ospi: refactor creationLuc Michel3-97/+98
Refactor the OSPI controller creation using the VersalMap structure. Note that the connection to the PMC IOU SLCR is removed for now and will be re-added by next commits. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-12-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/arm/xlnx-versal: efuse: refactor creationLuc Michel3-72/+54
Refactore the eFuse devices creation using the VersalMap structure. Note that the corresponding FDT nodes are removed. They do not correspond to any real node in standard Versal DTBs. No matching drivers exist for them. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-11-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/arm/xlnx-versal: usb: refactor creationLuc Michel3-73/+62
Refactor the USB controller creation using the VersalMap structure. Note that the connection to the CRL is removed for now and will be re-added by next commits. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-10-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/arm/xlnx-versal: xram: refactor creationLuc Michel2-30/+35
Refactor the XRAM devices creation using the VersalMap structure. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-9-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-10-07hw/arm/xlnx-versal: adma: refactor creationLuc Michel3-55/+49
Refactor the ADMA creation using the VersalMap structure. Note that the connection to the CRL is removed for now and will be re-added by next commits. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-8-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>