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2023-11-06hw/hppa: Turn on 64-bit CPU for C3700 machineHelge Deller1-1/+1
Signed-off-by: Helge Deller <deller@gmx.de>
2023-11-06hw/pci-host/astro: Trigger CPU irq on CPU HPA in high memoryHelge Deller1-1/+1
The CPU HPA is in the high F-region on PA2.0 CPUs, so use F_EXTEND() to trigger interrupt request at the right CPU HPA address. Note that the cpu_hpa value comes out of the IRT, which doesn't store the higher addresss bits. Signed-off-by: Helge Deller <deller@gmx.de>
2023-11-06hw/pci-host/astro: Map Astro chip into 64-bit I/O memory regionHelge Deller1-3/+6
Map Astro into high F-region and add alias for 32-bit OS in low region. Signed-off-by: Helge Deller <deller@gmx.de>
2023-11-06target/hppa: Improve interrupt loggingRichard Henderson1-8/+4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Update IIAOQ, IIASQ for pa2.0Richard Henderson2-18/+38
These registers have a different format for pa2.0. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Create raise_exception_with_iorRichard Henderson1-13/+51
Handle pa2.0 logic for filling in ISR+IOR. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Add unwind_breg to CPUHPPAStateRichard Henderson3-2/+20
Fill in the insn_start value during form_gva, and copy it out to the env field in hppa_restore_state_to_opc. The value is not yet consumed. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Clear upper bits in mtctl for pa1.xHelge Deller1-1/+7
Signed-off-by: Helge Deller <deller@gmx.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Avoid async_safe_run_on_cpu on uniprocessor systemRichard Henderson1-1/+7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Add pa2.0 cpu local tlb flushesHelge Deller5-12/+84
The previous decoding misnamed the bit it called "local". Other than the name, the implementation was correct for pa1.x. Rename this field to "tlbe". PA2.0 adds (a real) local bit to PxTLB, and also adds a range of pages to flush in GR[b]. Signed-off-by: Helge Deller <deller@gmx.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement pa2.0 data prefetch instructionsRichard Henderson1-1/+9
These are aliased onto the normal integer loads to %g0. Since we don't emulate caches, prefetch is a nop. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06linux-user/hppa: Drop EXCP_DUMP from handled exceptionsRichard Henderson1-4/+0
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06hw/hppa: Translate phys addresses for the cpuRichard Henderson1-46/+71
Hack the machine to use pa2.0 physical layout when required, using the PSW.W=0 absolute to physical mapping. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06include/hw/elf: Remove truncating signed castsRichard Henderson1-7/+10
There's nothing about elf that specifically requires signed vs unsigned. This is very much a target-specific preference. In the meantime, casting low and high from uint64_t back to Elf_SWord to uint64_t discards high bits that might have been set by translate_fn. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Return zero for r0 from load_gprRichard Henderson1-3/+1
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Precompute zero into DisasContextRichard Henderson1-16/+18
Reduce the number of times we look for the constant 0. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Fix interruption based on default PSWHelge Deller2-4/+16
The default PSW is set by the operating system with the PDC_PSW firmware call. Use that setting to decide if wide mode is to be enabled for interruptions and EIRR usage. Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement PERMHRichard Henderson2-0/+31
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement MIXH, MIXWRichard Henderson2-0/+60
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement HSHLADD, HSHRADDRichard Henderson4-2/+76
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement HSHL, HSHRRichard Henderson2-0/+40
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement HAVGRichard Henderson4-0/+22
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement HSUBRichard Henderson4-0/+53
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement HADDRichard Henderson4-1/+79
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Replace tcg_gen_*_tl with tcg_gen_*_i64Richard Henderson1-4/+4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Use tcg_temp_new_i64 not tcg_temp_newRichard Henderson1-80/+82
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Adjust vmstate_env for pa2.0 tlbRichard Henderson1-37/+58
Split out the tlb to a subsection so that it can be separately versioned -- the format is only partially following the architecture and is partially guided by the qemu implementation. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Remove remaining TARGET_REGISTER_BITS redirectionsRichard Henderson1-33/+13
The conversions to/from i64 can be eliminated entirely, folding computation into adjacent operations. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Remove most of the TARGET_REGISTER_BITS redirectionsRichard Henderson1-505/+407
Remove all but those intended to change type to or from i64. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Remove TARGET_REGISTER_BITSRichard Henderson11-299/+135
Rely only on TARGET_LONG_BITS, fixed at 64, and hppa_is_pa20. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06hw/hppa: Use uint32_t instead of target_uregRichard Henderson1-6/+6
The size of target_ureg is going to change. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement IDTLBT, IITLBTRichard Henderson4-13/+100
Rename the existing insert tlb helpers to emphasize that they are for pa1.1 cpus. Implement a combined i/d tlb for pa2.0. Still missing is the new 'P' tlb bit. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement STDBYRichard Henderson4-5/+213
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement CLRBTS, POPBTS, PUSHBTS, PUSHNOMRichard Henderson2-0/+8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement SHRPDRichard Henderson2-32/+73
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement EXTRDRichard Henderson2-13/+36
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement DEPD, DEPDIRichard Henderson2-30/+69
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement LDD, LDCD, LDDA, STD, STDARichard Henderson2-4/+15
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode ADDB double-wordRichard Henderson1-0/+11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode CMPIB double-wordRichard Henderson2-3/+18
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode d for cmpb instructionsRichard Henderson2-6/+15
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode d for bb instructionsRichard Henderson2-6/+4
Manipulate the shift count so that the bit to be tested is always placed at the MSB. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode d for sub instructionsRichard Henderson2-17/+17
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode d for add instructionsRichard Henderson2-18/+19
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode d for cmpclr instructionsRichard Henderson2-8/+9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode d for unit instructionsRichard Henderson2-20/+19
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode d for logical instructionsRichard Henderson2-12/+13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Remove TARGET_HPPA64Richard Henderson5-29/+8
Allow both user-only and system mode to run pa2.0 cpus. Avoid creating a separate qemu-system-hppa64 binary; force the qemu-hppa binary to use TARGET_ABI32. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Drop attempted gdbstub support for hppa64Richard Henderson1-19/+13
There is no support for hppa64 in gdb. Any attempt to provide the data for the larger hppa64 registers results in an error from gdb. Mask CR_SAR writes to the width of the register: 5 or 6 bits. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06linux-user/hppa: Fixes for TARGET_ABI32Richard Henderson1-3/+3
Avoid target_ulong and use abi_* types. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>