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* hw/intc/arm_gic: Make ICDDCR/GICD_CTLR bankedFabian Aggeler2015-05-121-1/+1
| | | | | | | | | | | | | | | | | | | | | ICDDCR/GICD_CTLR is banked if the GIC has the security extensions, and the S (or only) copy has separate enable bits for Group0 and Group1 enable if the GIC implements interrupt groups. EnableGroup0 (Bit [1]) in GICv1 is architecturally IMPDEF. Since this bit (Enable Non-secure) is present in the integrated GIC of the Cortex-A9 MPCore, we support this bit in our GICv1 implementation too. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1430502643-25909-7-git-send-email-peter.maydell@linaro.org Message-id: 1429113742-8371-8-git-send-email-greg.bellows@linaro.org [PMM: rewritten to store the state in a single s->ctlr uint32, with the NS register handled as an alias of bit 1 in that value; added vmstate version bump] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* armv7m_nvic: systick: Reload the RELOAD value and count down only if ENABLE ↵Adrian Huang2015-05-121-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | bit is set Consider the following pseudo code to configure SYSTICK (The recommended programming sequence from "the definitive guide to the arm cortex-m3"): SYSTICK Reload Value Register = 0xffff SYSTICK Current Value Register = 0 SYSTICK Control and Status Register = 0x7 The pseudo code "SYSTICK Current Value Register = 0" leads to invoking systick_reload(). As a consequence, the systick.tick member is updated and the systick timer starts to count down when the ENABLE bit of SYSTICK Control and Status Register is cleared. The worst case is that: during the system initialization, the reset value of the SYSTICK Control and Status Register is 0x00000000. When the code "SYSTICK Current Value Register = 0" is executed, the systick.tick member is accumulated with "(s->systick.reload + 1) * systick_scale(s)". The systick_scale() gets the external_ref_clock scale because the CLKSOURCE bit of the SYSTICK Control and Status Register is cleared. This is the incorrect behavior because of the code "SYSTICK Control and Status Register = 0x7". Actually, we want the processor clock instead of the external reference clock. This incorrect behavior defers the generation of the first interrupt. The patch fixes the above-mentioned issue by setting the systick.tick member and modifying the systick timer only if the ENABLE bit of the SYSTICK Control and Status Register is set. In addition, the Cortex-M3 Devices Generic User Guide mentioned that "When ENABLE is set to 1, the counter loads the RELOAD value from the SYST RVR register and then counts down". This patch adheres to the statement of the user guide. Signed-off-by: Adrian Huang <adrianhuang0701@gmail.com> Reviewed-by: Jim Huang <jserv.tw@gmail.com> [PMM: minor tweak to comment text] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* vmstate: accept QEMUTimer in VMSTATE_TIMER*, add VMSTATE_TIMER_PTR*Paolo Bonzini2015-01-261-1/+1
| | | | | | | Old users of VMSTATE_TIMER* are mechanically changed to VMSTATE_TIMER_PTR variants. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* arm_gic: remove unused parameter.KONRAD Frederic2014-10-241-1/+1
| | | | | | | | | This removes num_irq parameter from gic_init_irqs_and_distributor as it is not used. Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com> Message-id: 1412859651-15060-1-git-send-email-fred.konrad@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* armv7m_nvic: fix AIRCR implementationOran Avraham2014-06-191-1/+4
| | | | | | | | | The returned reset value was wrong (off by one zero nibble), and qemu didn't log unimplemented writes to the PRIGROUP field. Signed-off-by: Oran Avraham <oranav@gmail.com> Message-id: 1403010447-4627-1-git-send-email-oranav@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* savevm: Remove all the unneeded version_minimum_id_old (arm)Juan Quintela2014-05-131-2/+1
| | | | | | | | | | | | | | | | | | | | | After commit 767adce2d, they are redundant. This way we don't assign them except when needed. Once there, there were lots of cases where the ".fields" indentation was wrong: .fields = (VMStateField []) { and .fields = (VMStateField []) { Change all the combinations to: .fields = (VMStateField[]){ The biggest problem (apart from aesthetics) was that checkpatch complained when we copy&pasted the code from one place to another. Signed-off-by: Juan Quintela <quintela@redhat.com> [PMM: fixed minor conflict, corrected commit message typos] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm: Clean up fragile use of error_is_set() in realize() methodsMarkus Armbruster2014-05-051-2/+4
| | | | | | | | | | | | | | | | | | | Using error_is_set(ERRP) to find out whether a function failed is either wrong, fragile, or unnecessarily opaque. It's wrong when ERRP may be null, because errors go undetected when it is. It's fragile when proving ERRP non-null involves a non-local argument. Else, it's unnecessarily opaque (see commit 84d18f0). I guess the error_is_set(errp) in the DeviceClass realize() methods are merely fragile right now, because I can't find a call chain that passes a null errp argument. Make the code more robust and more obviously correct: receive the error in a local variable, then propagate it through the parameter. Signed-off-by: Markus Armbruster <armbru@redhat.com> Acked-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
* armv7m_nvic: fix CPUID Base RegisterRabin Vincent2014-05-011-1/+1
| | | | | | | | | cp15.c0_cpuid is never initialized for ARMv7-M; take the value directly from cpu->midr instead. Signed-off-by: Rabin Vincent <rabin@rab.in> Message-id: 1398036308-32166-1-git-send-email-rabin@rab.in Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* aio / timers: Switch entire codebase to the new timer APIAlex Bligh2013-08-221-8/+8
| | | | | | | | | | | This is an autogenerated patch using scripts/switch-timer-api. Switch the entire code base to using the new timer API. Note this patch may introduce some line length issues. Signed-off-by: Alex Bligh <alex@alex.org.uk> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
* cpu: Replace cpu_single_env with CPUState current_cpuAndreas Färber2013-07-091-3/+8
| | | | | | Move it to qom/cpu.h. Signed-off-by: Andreas Färber <afaerber@suse.de>
* hw/i*: pass owner to memory_region_init* functionsPaolo Bonzini2013-07-041-3/+4
| | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* memory: add owner argument to initialization functionsPaolo Bonzini2013-07-041-3/+3
| | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* arm: fix location of some include filesPeter Maydell2013-04-151-1/+1
| | | | | | | | | | | The recent rearrangement of include files had some minor errors: devices.h is not ARM specific and should not be in arm/ arm.h should be in arm/ Move these two headers to correct this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* Typo, spelling and grammatical fixesPeter Maydell2013-04-121-1/+1
| | | | | | | Minor fixes to documentation and code comments. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
* hw: move private headers to hw/ subdirectories.Paolo Bonzini2013-04-081-1/+1
| | | | | | | Many headers are used only in a single directory. These can be kept in hw/. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* hw: move interrupt controllers to hw/intc/, configure with default-configs/Paolo Bonzini2013-04-081-0/+553
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>