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path: root/hw/intc/sifive_plic.c (follow)
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* hw/intc: sifive_plic: Fix the pending register range checkBin Meng2023-01-061-2/+3
* hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0Bin Meng2023-01-061-2/+3
* hw/intc: sifive_plic: Update "num-sources" property default valueBin Meng2023-01-061-1/+7
* hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in ...Bin Meng2023-01-061-3/+4
* hw/intc: sifive_plic: Improve robustness of the PLIC config parserBin Meng2023-01-061-8/+16
* hw/intc: sifive_plic: Drop PLICMode_HBin Meng2023-01-061-1/+0
* hw/intc: sifive_plic: fix out-of-bound access of source_priority arrayJim Shu2023-01-061-1/+11
* hw/intc: sifive_plic: Renumber the S irqs for numa supportFrédéric Pétrot2023-01-061-2/+2
* hw/intc: sifive_plic: change interrupt priority register to WARL fieldJim Shu2022-10-141-2/+19
* hw/intc: sifive_plic: fix hard-coded max priority levelJim Shu2022-10-141-2/+4
* hw/intc: sifive_plic: Fix multi-socket plic configuraitonAtish Patra2022-07-281-2/+2
* hw/intc: sifive_plic: Avoid overflowing the addr_config bufferAlistair Francis2022-06-101-10/+9
* target/riscv: Support start kernel directly by KVMYifei Jiang2022-01-211-5/+15
* hw/intc: sifive_plic: Cleanup remaining functionsAlistair Francis2022-01-081-87/+22
* hw/intc: sifive_plic: Cleanup the read functionAlistair Francis2022-01-081-44/+11
* hw/intc: sifive_plic: Cleanup the write functionAlistair Francis2022-01-081-49/+27
* hw/intc: sifive_plic: Add a reset functionAlistair Francis2022-01-081-0/+18
* hw/intc: sifive_plic: Cleanup the irq_request functionAlistair Francis2021-10-221-6/+4
* hw/intc: sifive_plic: Cleanup the realize functionAlistair Francis2021-10-221-21/+24
* hw/intc: sifive_plic: Move the propertiesAlistair Francis2021-10-221-15/+15
* hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis2021-09-211-7/+23
* Do not include hw/boards.h if it's not really necessaryThomas Huth2021-05-021-1/+0
* Do not include sysemu/sysemu.h if it's not really necessaryThomas Huth2021-05-021-1/+0
* target/riscv: Add sifive_plic vmstateYifei Jiang2020-11-031-1/+25
* qemu/atomic.h: rename atomic_ to qatomic_Stefan Hajnoczi2020-09-231-2/+2
* hw/riscv: Move sifive_plic model to hw/intcBin Meng2020-09-091-0/+524