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* intc/arm_gic: Add the virtualization extensions to the GIC stateLuc Michel2018-08-144-26/+137
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add the necessary parts of the virtualization extensions state to the GIC state. We choose to increase the size of the CPU interfaces state to add space for the vCPU interfaces (the GIC_NCPU_VCPU macro). This way, we'll be able to reuse most of the CPU interface code for the vCPUs. The only exception is the APR value, which is stored in h_apr in the virtual interface state for vCPUs. This is due to some complications with the GIC VMState, for which we don't want to break backward compatibility. APRs being stored in 2D arrays, increasing the second dimension would lead to some ugly VMState description. To avoid that, we keep it in h_apr for vCPUs. The vCPUs are numbered from GIC_NCPU to (GIC_NCPU * 2) - 1. The `gic_is_vcpu` function help to determine if a given CPU id correspond to a physical CPU or a virtual one. For the in-kernel KVM VGIC, since the exposed VGIC does not implement the virtualization extensions, we report an error if the corresponding property is set to true. Signed-off-by: Luc Michel <luc.michel@greensocs.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180727095421.386-6-luc.michel@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* intc/arm_gic: Remove some dead code and put some functions staticLuc Michel2018-08-142-25/+2
| | | | | | | | | | | | Some functions are now only used in arm_gic.c, put them static. Some of them where only used by the NVIC implementation and are not used anymore, so remove them. Signed-off-by: Luc Michel <luc.michel@greensocs.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180727095421.386-4-luc.michel@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* intc/arm_gic: Implement GICD_ISACTIVERn and GICD_ICACTIVERn registersLuc Michel2018-08-141-4/+57
| | | | | | | | | | | Implement GICD_ISACTIVERn and GICD_ICACTIVERn registers in the GICv2. Those registers allow to set or clear the active state of an IRQ in the distributor. Signed-off-by: Luc Michel <luc.michel@greensocs.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180727095421.386-3-luc.michel@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* intc/arm_gic: Refactor operations on the distributorLuc Michel2018-08-144-116/+127
| | | | | | | | | | | | | | | In preparation for the virtualization extensions implementation, refactor the name of the functions and macros that act on the GIC distributor to make that fact explicit. It will be useful to differentiate them from the ones that will act on the virtual interfaces. Signed-off-by: Luc Michel <luc.michel@greensocs.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180727095421.386-2-luc.michel@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* nvic: Change NVIC to support ARMv6-MJulia Suvorova2018-08-141-3/+18
| | | | | | | | | | | | The differences from ARMv7-M NVIC are: * ARMv6-M only supports up to 32 external interrupts (configurable feature already). The ICTR is reserved. * Active Bit Register is reserved. * ARMv6-M supports 4 priority levels against 256 in ARMv7-M. Signed-off-by: Julia Suvorova <jusual@mail.ru> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm: Add ARMv6-M programmer's model supportJulia Suvorova2018-08-141-0/+10
| | | | | | | | | | | | | Forbid stack alignment change. (CCR) Reserve FAULTMASK, BASEPRI registers. Report any fault as a HardFault. Disable MemManage, BusFault and UsageFault, so they always escalated to HardFault. (SHCSR) Signed-off-by: Julia Suvorova <jusual@mail.ru> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20180718095628.26442-1-jusual@mail.ru Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* nvic: Handle ARMv6-M SCS reserved registersJulia Suvorova2018-08-141-2/+49
| | | | | | | | | | Handle SCS reserved registers listed in ARMv6-M ARM D3.6.1. All reserved registers are RAZ/WI. ARM_FEATURE_M_MAIN is used for the checks, because these registers are reserved in ARMv8-M Baseline too. Signed-off-by: Julia Suvorova <jusual@mail.ru> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/intc/arm_gicv3_common: Move gicd shift bug handling to gicv3_post_loadPeter Maydell2018-08-061-40/+37
| | | | | | | | | | | | | | The code currently in gicv3_gicd_no_migration_shift_bug_post_load() that handles migration from older QEMU versions with a particular bug is misplaced. We need to run this after migration in all cases, not just the cases where the "arm_gicv3/gicd_no_migration_shift_bug" subsection is present, so it must go in a post_load hook for the top level VMSD, not for the subsection. Move it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-id: 20180806123445.1459-6-peter.maydell@linaro.org
* hw/intc/arm_gicv3_common: Move post_load hooks to top-level VMSDPeter Maydell2018-08-061-4/+4
| | | | | | | | | | | | | | | | | | Contrary to the the impression given in docs/devel/migration.rst, the migration code does not run the pre_load hook for a subsection unless the subsection appears on the wire, and so this is not a place where you can set the default value for state for the "subsection not present" case. Instead this needs to be done in a pre_load hook for whatever is the parent VMSD of the subsection. We got this wrong in two of the subsection definitions in the GICv3 migration structs; fix this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-id: 20180806123445.1459-5-peter.maydell@linaro.org
* hw/intc/arm_gicv3_common: Combine duplicate .subsections in vmstate_gicv3_cpuPeter Maydell2018-08-061-3/+0
| | | | | | | | | | | | | | | Commit 6692aac411199064 accidentally introduced a second initialization of the .subsections field of vmstate_gicv3_cpu, instead of adding the new subsection to the existing list. The effect of this was probably that migration of GICv3 with virtualization enabled was broken (or alternatively that migration of ICC_SRE_EL1 was broken, depending on which of the two initializers the compiler used). Combine the two into a single list. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180806123445.1459-3-peter.maydell@linaro.org
* hw/intc/arm_gicv3_common: Give no-migration-shift-bug subsection a needed ↵Peter Maydell2018-08-061-0/+6
| | | | | | | | | | | | | | | function Currently the migration code incorrectly treats a subsection with no .needed function pointer as if it was the subsection list terminator -- it is ignored and so is everything after it. Work around this by giving vmstate_gicv3_gicd_no_migration_shift_bug a 'needed' function that always returns true. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180806123445.1459-2-peter.maydell@linaro.org
* armv7m_nvic: Fix m-security subsection namePeter Maydell2018-07-301-1/+1
| | | | | | | | | | | | | | | The vmstate save/load code insists that subsections of a VMState must have names which include their parent VMState's name as a leading substring. Unfortunately it neither documents this nor checks it on device init or state save, but instead fails state load with a confusing error message ("Missing section footer for armv7m_nvic"). Fix the name of the m-security subsection of the NVIC, so that state save/load works correctly for the security-enabled NVIC. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180727113854.20283-2-peter.maydell@linaro.org
* target/arm: Escalate to correct HardFault when AIRCR.BFHFNMINS is setPeter Maydell2018-07-242-3/+7
| | | | | | | | | | | | | | | | | | When we escalate a v8M exception to HardFault, if AIRCR.BFHFNMINNS is set then we need to decide whether it should become a secure HardFault or a nonsecure HardFault. We should always escalate to the same target security state as the original exception. The current code tries to test this using the 'secure' bool, which is not right because that flag indicates whether the target security state only for banked exceptions; the effect was that we were incorrectly escalating always-secure exceptions like SecureFault to a nonsecure HardFault. Fix this by defining, logging and using a new 'targets_secure' bool which tracks the condition we actually want. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180723123457.2038-1-peter.maydell@linaro.org
* hw/intc/arm_gicv3: Check correct HCR_EL2 bit when routing IRQPeter Maydell2018-07-241-1/+1
| | | | | | | | | | | In icc_dir_write() we were incorrectly checking HCR_EL2.FMO when determining whether IRQ should be routed to EL2; this should be HCR_EL2.IMO (compare the GICv3 pseudocode ICC_DIR_EL1[]). Use the correct mask. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180723180337.17378-1-peter.maydell@linaro.org
* hw/intc/exynos4210_gic: Turn instance_init into realize functionThomas Huth2018-07-231-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | The instance_init function of the "exynos4210.gic" device creates a new "arm_gic" device and immediately realizes it with qdev_init_nofail(). This will leave a lot of object in the QOM tree during introspection of the "exynos4210.gic" device, e.g. reproducible by starting QEMU like this: qemu-system-aarch64 -M none -nodefaults -nographic -monitor stdio And then by running "info qom-tree" at the HMP monitor, followed by "device_add exynos4210.gic,help" and finally checking "info qom-tree" again. Also note that qdev_init_nofail() can exit QEMU in case of errors - and this must never happen during an instance_init function, otherwise QEMU could terminate unexpectedly during introspection of a device. Since most of the code that follows the qdev_init_nofail() depends on the realized "gicbusdev", the easiest solution to the problem is to turn the whole instance_init function into a realize function instead. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-id: 1532337784-334-1-git-send-email-thuth@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/*/realview: Fix introspection problem with 'realview_mpcore' & 'realview_gic'Thomas Huth2018-07-171-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | echo "{'execute':'qmp_capabilities'} {'execute':'device-list-properties'," \ "'arguments':{'typename':'realview_mpcore'}}" \ "{'execute': 'human-monitor-command', " \ "'arguments': {'command-line': 'info qtree'}}" | \ valgrind -q aarch64-softmmu/qemu-system-aarch64 -M none,accel=qtest -qmp stdio [...] ==2654== Invalid read of size 8 ==2654== at 0x61878A: qdev_print (qdev-monitor.c:686) ==2654== by 0x61878A: qbus_print (qdev-monitor.c:719) ==2654== by 0x452B38: handle_hmp_command (monitor.c:3446) ==2654== by 0x452D70: qmp_human_monitor_command (monitor.c:821) [...] Use sysbus_init_child_obj() to fix it. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-id: 1531745974-17187-14-git-send-email-thuth@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/armv7: Fix crash when introspecting the "iotkit" deviceThomas Huth2018-07-171-3/+2
| | | | | | | | | | | | | | | | | | | | | | QEMU currently crashes when introspecting the "iotkit" device and runnint "info qtree" afterwards, e.g. when running QEMU like this: echo "{'execute':'qmp_capabilities'} {'execute':'device-list-properties'," \ "'arguments':{'typename':'iotkit'}}" "{'execute': 'human-monitor-command', " \ "'arguments': {'command-line': 'info qtree'}}" | \ aarch64-softmmu/qemu-system-aarch64 -M none,accel=qtest -qmp stdio Use the new functions object_initialize_child() and sysbus_init_child_obj() to make sure that all objects get cleaned up correctly when the instances are destroyed. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1531745974-17187-5-git-send-email-thuth@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/intc/arm_gic: Fix handling of GICD_ITARGETSRPeter Maydell2018-07-161-2/+4
| | | | | | | | | | | | | | | | | | | | The GICD_ITARGETSR implementation still has some 11MPCore behaviour that we were incorrectly using in our GICv1 and GICv2 implementations for the case where the interrupt number is less than GIC_INTERNAL. The desired behaviour here is: * for 11MPCore: RAZ/WI for irqs 0..28; read a number matching the CPU doing the read for irqs 29..31 * for GICv1 and v2: RAZ/WI if uniprocessor; otherwise read a number matching the CPU doing the read for all irqs < 32 Stop squashing GICD_ITARGETSR to 0 for IRQs 0..28 unless this is an 11MPCore GIC. Reported-by: Jan Kiszka <jan.kiszka@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Message-id: 20180712154152.32183-3-peter.maydell@linaro.org
* hw/intc/arm_gic: Check interrupt number in gic_deactivate_irq()Peter Maydell2018-07-161-1/+15
| | | | | | | | | | | | | | | | | | | In gic_deactivate_irq() the interrupt number comes from the guest (on a write to the GICC_DIR register), so we need to sanity check that it isn't out of range before we use it as an array index. Handle this in a similar manner to the check we do in gic_complete_irq() for the GICC_EOI register. The array overrun is not disastrous because the calling code uses (value & 0x3ff) to extract the interrupt field, so the only out-of-range values possible are 1020..1023, which allow overrunning only from irq_state[] into the following irq_target[] array which the guest can already manipulate. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Message-id: 20180712154152.32183-2-peter.maydell@linaro.org
* ppc/xics: fix ICP reset pathGreg Kurz2018-07-161-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recent cleanup in commit a028dd423ee6 dropped the ICPStateClass::reset handler. It is now up to child ICP classes to call the DeviceClass::reset handler of the parent class, thanks to device_class_set_parent_reset(). This is a better object programming pattern, but unfortunately it causes QEMU to crash during CPU hotplug: (qemu) device_add host-spapr-cpu-core,id=core1,core-id=1 Segmentation fault (core dumped) When the hotplug path tries to reset the ICP device, we end up calling: static void icp_kvm_reset(DeviceState *dev) { ICPStateClass *icpc = ICP_GET_CLASS(dev); icpc->parent_reset(dev); but icpc->parent_reset is NULL... This happens because icp_kvm_class_init() calls: device_class_set_parent_reset(dc, icp_kvm_reset, &icpc->parent_reset); but dc->reset, ie, DeviceClass::reset for the TYPE_ICP type, is itself NULL. This patch hence sets DeviceClass::reset for the TYPE_ICP type to point to icp_reset(). It then registers a reset handler that calls DeviceClass::reset. If the ICP subtype has configured its own reset handler with device_class_set_parent_reset(), this ensures it will be called first and it can then call ICPStateClass::parent_reset safely. This fixes the reset path for the TYPE_KVM_ICP type, which is the only subtype that defines its own reset function. Reported-by: Satheesh Rajendran <sathnaga@linux.vnet.ibm.com> Suggested-by: David Gibson <david@gibson.dropbear.id.au> Fixes: a028dd423ee6dfd091a8c63028240832bf10f671 Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* ioapic: remove useless lower bounds checkPaolo Bonzini2018-07-061-1/+1
| | | | | | | | The vector cannot be negative. Coverity now reports this because it sees an array access before the check, in ioapic_stat_update_irq. Reviewed-by: Peter Xu <peterx@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* ppc/xics: rework the ICS classes inheritance treeCédric Le Goater2018-07-031-7/+5
| | | | | | | | | | | | | | | With the previous changes, we can now let the ICS_KVM class inherit directly from ICS_BASE class and not from the intermediate ICS_SIMPLE. It makes the class hierarchy much cleaner. What is left in the top classes is the low level interface to access the KVM XICS device in ICS_KVM and the XICS emulating handlers in ICS_SIMPLE. This should not break migration compatibility. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* ppc/xics: move the vmstate structures under the ics-base classCédric Le Goater2018-07-031-56/+56
| | | | | Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* ppx/xics: introduce a parent_reset in ICSStateClassCédric Le Goater2018-07-032-31/+40
| | | | | | | | Just like for the realize handlers, this makes possible to move the common ICSState code of the reset handlers in the ics-base class. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* ppc/xics: move the instance_init handler under the ics-base classCédric Le Goater2018-07-031-8/+8
| | | | | Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* ppc/xics: introduce a parent_realize in ICSStateClassCédric Le Goater2018-07-032-20/+37
| | | | | | | | This makes possible to move the common ICSState code of the realize handlers in the ics-base class. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* ppc/xics: introduce ICP DeviceRealize and DeviceReset handlersCédric Le Goater2018-07-033-19/+40
| | | | | | | | | This changes the ICP realize and reset handlers in DeviceRealize and DeviceReset handlers. parent handlers are now called from the inheriting classes which is a cleaner object pattern. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* hmp: obsolete "info ioapic"Peter Xu2018-06-281-11/+0
| | | | | | | | | | Let's start to use "info pic" just like other platforms. For now we keep the command for a while so that old users can know what is the new command to use. Signed-off-by: Peter Xu <peterx@redhat.com> Message-Id: <20171229073104.3810-6-peterx@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* ioapic: support "info irq"Peter Xu2018-06-282-0/+24
| | | | | | | | | | | | | This include both userspace and in-kernel ioapic. Note that the numbers can be inaccurate for kvm-ioapic. One reason is the same with kvm-i8259, that when irqfd is used, irqs can be delivered all inside kernel without our notice. Meanwhile, kvm-ioapic is specially treated when irq numbers <ISA_NUM_IRQS, those irqs will be delivered in kernel too via kvm-i8259 (please refer to kvm_pc_gsi_handler). Signed-off-by: Peter Xu <peterx@redhat.com> Message-Id: <20171229073104.3810-5-peterx@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* ioapic: some proper indents when dump infoPeter Xu2018-06-281-4/+4
| | | | | | | | So that now it looks better when with other irqchips. Signed-off-by: Peter Xu <peterx@redhat.com> Message-Id: <20171229073104.3810-4-peterx@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* ioapic: support "info pic"Peter Xu2018-06-281-0/+16
| | | | | | | | | People start to use "info pic" for all kinds of irqchip dumps. Let x86 ioapic join the family. It dumps the same thing as "info ioapic". Signed-off-by: Peter Xu <peterx@redhat.com> Message-Id: <20171229073104.3810-3-peterx@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* hw/intc/arm_gicv3_kvm: Get prepared to handle multiple redist regionsEric Auger2018-06-221-3/+34
| | | | | | | | | | | | | | Let's check if KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION is supported. If not, we check the number of redist region is equal to 1 and use the legacy KVM_VGIC_V3_ADDR_TYPE_REDIST attribute. Otherwise we use the new attribute and allow to register multiple regions to the KVM device. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-id: 1529072910-16156-5-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/intc/arm_gicv3: Introduce redist-region-count array propertyEric Auger2018-06-223-8/+51
| | | | | | | | | | | | | | | | | | | To prepare for multiple redistributor regions, we introduce an array of uint32_t properties that stores the redistributor count of each redistributor region. Non accelerated VGICv3 only supports a single redistributor region. The capacity of all redist regions is checked against the number of vcpus. Machvirt is updated to set those properties, ie. a single redistributor region with count set to the number of vcpus capped by 123. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-id: 1529072910-16156-4-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Allow KVM device address overwritingEric Auger2018-06-223-5/+5
| | | | | | | | | | | | | | | | | | | | | for KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION attribute, the attribute data pointed to by kvm_device_attr.addr is a OR of the redistributor region address and other fields such as the index of the redistributor region and the number of redistributors the region can contain. The existing machine init done notifier framework sets the address field to the actual address of the device and does not allow to OR this value with other fields. This patch extends the KVMDevice struct with a new kda_addr_ormask member. Its value is passed at registration time and OR'ed with the resolved address on kvm_arm_set_device_addr(). Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1529072910-16156-3-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/intc/arm_gicv3: fix an extra left-shift when reading IPRIORITYRAmol Surati2018-06-222-2/+4
| | | | | | | | | | | | | | When either GICD_IPRIORITYR or GICR_IPRIORITYR is read as a 32-bit register, the post left-shift operator in the for loop causes an extra shift after the least significant byte has been placed. The 32-bit value actually returned is therefore the expected value shifted left by 8 bits. Signed-off-by: Amol Surati <suratiamol@gmail.com> Message-id: 20180614054857.26248-1-suratiamol@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* xics_kvm: fix a build breakCédric Le Goater2018-06-161-6/+4
| | | | | | | | | | | | | | | On CentOS 7.5, gcc-4.8.5-28.el7_5.1.ppc64le fails to build QEMU due to : hw/intc/xics_kvm.c: In function ‘ics_set_kvm_state’: hw/intc/xics_kvm.c:281:13: error: ‘ret’ may be used uninitialized in this function [-Werror=maybe-uninitialized] return ret; Fix the breakage and also remove the extra error reporting as kvm_device_access() already provides a substantial error message. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* arm: Don't crash if user tries to use a Cortex-M CPU without an NVICPeter Maydell2018-06-151-1/+5
| | | | | | | | | | | | | | | | | | | | | | The Cortex-M CPU and its NVIC are two intimately intertwined parts of the same hardware; it is not possible to use one without the other. Unfortunately a lot of our board models don't do any sanity checking on the CPU type the user asks for, so a command line like qemu-system-arm -M versatilepb -cpu cortex-m3 will create an M3 without an NVIC, and coredump immediately. In the other direction, trying a non-M-profile CPU in an M-profile board won't blow up, but doesn't do anything useful either: qemu-system-arm -M lm3s6965evb -cpu arm926 Add some checking in the NVIC and CPU realize functions that the user isn't trying to use an NVIC without an M-profile CPU or an M-profile CPU without an NVIC, so we can produce a helpful error message rather than a core dump. Fixes: https://bugs.launchpad.net/qemu/+bug/1766896 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180601160355.15393-1-peter.maydell@linaro.org
* arm_gicv3_kvm: kvm_dist_get/put_priority: skip the registers banked by ↵Shannon Zhao2018-06-151-2/+16
| | | | | | | | | | | | | | | GICR_IPRIORITYR While for_each_dist_irq_reg loop starts from GIC_INTERNAL, it forgot to offset the date array and index. This will overlap the GICR registers value and leave the last GIC_INTERNAL irq's registers out of update. Fixes: 367b9f527becdd20ddf116e17a3c0c2bbc486920 Cc: qemu-stable@nongnu.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* xics_kvm: use KVM helpersCédric Le Goater2018-06-121-38/+14
| | | | | | | | The KVM helpers hide the low level interface used to communicate to the XICS KVM device and provide a good cleanup to the XICS KVM models. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* arm_gicv3_kvm: kvm_dist_get/put: skip the registers banked by GICRShannon Zhao2018-06-082-0/+117
| | | | | | | | | | | | | | | | | | | | While we skip the GIC_INTERNAL irqs, we don't change the register offset accordingly. This will overlap the GICR registers value and leave the last GIC_INTERNAL irq's registers out of update. Fix this by skipping the registers banked by GICR. Also for migration compatibility if the migration source (old version qemu) doesn't send gicd_no_migration_shift_bug = 1 to destination, then we shift the data of PPI to get the right data for SPI. Fixes: 367b9f527becdd20ddf116e17a3c0c2bbc486920 Cc: qemu-stable@nongnu.org Reviewed-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Message-id: 1527816987-16108-1-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell2018-06-041-2/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | acpi, vhost, misc: fixes, features vDPA support, fix to vhost blk RO bit handling, some include path cleanups, NFIT ACPI table. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Fri 01 Jun 2018 17:25:19 BST # gpg: using RSA key 281F0DB8D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: (31 commits) vhost-blk: turn on pre-defined RO feature bit ACPI testing: test NFIT platform capabilities nvdimm, acpi: support NFIT platform capabilities tests/.gitignore: add entry for generated file arch_init: sort architectures ui: use local path for local headers qga: use local path for local headers colo: use local path for local headers migration: use local path for local headers usb: use local path for local headers sd: fix up include vhost-scsi: drop an unused include ppc: use local path for local headers rocker: drop an unused include e1000e: use local path for local headers ioapic: fix up includes ide: use local path for local headers display: use local path for local headers trace: use local path for local headers migration: drop an unused include ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * ioapic: fix up includesMichael S. Tsirkin2018-06-011-2/+1
| | | | | | | | | | | | | | | | | | | | include files shouldn't have the "include/" part, that is implied. Also, drop an unused include. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
* | KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twiceShannon Zhao2018-05-312-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | kvm_irqchip_create called by kvm_init will call kvm_init_irq_routing to initialize global capability variables. If we call kvm_init_irq_routing in GIC realize function, previous allocated memory will leak. Fix this by deleting the unnecessary call. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 1527750994-14360-1-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | arm_gicv3_kvm: increase clroffset accordinglyShannon Zhao2018-05-311-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | It forgot to increase clroffset during the loop. So it only clear the first 4 bytes. Fixes: 367b9f527becdd20ddf116e17a3c0c2bbc486920 Cc: qemu-stable@nongnu.org Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 1527047633-12368-1-git-send-email-zhaoshenglong@huawei.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/intc/arm_gicv3: Fix APxR<n> register dispatchingJan Kiszka2018-05-311-6/+6
|/ | | | | | | | | | | | There was a nasty flip in identifying which register group an access is targeting. The issue caused spuriously raised priorities of the guest when handing CPUs over in the Jailhouse hypervisor. Cc: qemu-stable@nongnu.org Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Message-id: 28b927d3-da58-bce4-cc13-bfec7f9b1cb9@siemens.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* heathrow: remove obsolete heathow_init() functionMark Cave-Ayland2018-04-271-18/+5
| | | | | | | Instead wire up heathrow to the CPU and grackle PCI host using qdev GPIOs. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/arm: Fetch GICv3 state directly from CPUARMStateAaron Lindsay2018-04-261-8/+2
| | | | | | | | | | | This eliminates the need for fetching it from el_change_hook_opaque, and allows for supporting multiple el_change_hooks without having to hack something together to find the registered opaque belonging to GICv3. Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1523997485-1905-6-git-send-email-alindsay@codeaurora.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/intc/arm_gicv3: Fix secure-GIC NS ICC_PMR and ICC_RPR accessesPeter Maydell2018-03-231-3/+3
| | | | | | | | | | | | | | | | | | | | | | If the GIC has the security extension support enabled, then a non-secure access to ICC_PMR must take account of the non-secure view of interrupt priorities, where real priorities 0x00..0x7f are secure-only and not visible to the non-secure guest, and priorities 0x80..0xff are shown to the guest as if they were 0x00..0xff. We had the logic here wrong: * on reads, the priority is in the secure range if bit 7 is clear, not if it is set * on writes, we want to set bit 7, not mask everything else Our ICC_RPR read code had the same error as ICC_PMR. (Compare the GICv3 spec pseudocode functions ICC_RPR_EL1 and ICC_PMR_EL1.) Fixes: https://bugs.launchpad.net/qemu/+bug/1748434 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-id: 20180315133441.24149-1-peter.maydell@linaro.org
* openpic_kvm: drop address_space_to_flatview callPaolo Bonzini2018-03-061-4/+0
| | | | | | | | | | | | | | The MemoryListener is registered on address_space_memory, there is not much to assert. This currently works because the callback is invoked only once when the listener is registered, but section->fv is the _new_ FlatView, not the old one on later calls and that would break. This confines address_space_to_flatview to exec.c and memory.c. Acked-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* openpic: move OpenPIC state and related definitions to openpic.hMark Cave-Ayland2018-03-061-157/+0
| | | | | | | | | This is to faciliate access to OpenPICState when wiring up the PIC to the macio controller. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>