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* hw/dma: Pass parent object to i8257_dma_init()Philippe Mathieu-Daudé2024-02-151-1/+1
| | | | | | | | Set I8257 instances parent (migration isn't affected). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240213114426.87836-1-philmd@linaro.org>
* hw/isa: Constify VMStateRichard Henderson2023-12-291-4/+4
| | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231221031652.119827-38-richard.henderson@linaro.org>
* hw/isa/piix: Implement multi-process QEMU support also for PIIX4Bernhard Beschow2023-10-221-8/+1
| | | | | | | | | | So far multi-process QEMU was only implemented for PIIX3. Move the support into the base class to achieve feature parity between both device models. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-Id: <20231007123843.127151-29-shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* hw/isa/piix: Resolve duplicate code regarding PCI interrupt wiringBernhard Beschow2023-10-221-11/+2
| | | | | | | | | | Now that both PIIX3 and PIIX4 use piix_set_irq() to trigger PCI IRQs the wiring in the respective realize methods can be shared, too. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231007123843.127151-28-shentey@gmail.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* hw/isa/piix: Reuse PIIX3's PCI interrupt triggering in PIIX4Bernhard Beschow2023-10-221-24/+3
| | | | | | | | | | Speeds up PIIX4 which resolves an old TODO. Also makes PIIX4 compatible with Xen which relies on pci_bus_fire_intx_routing_notifier() to be fired. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231007123843.127151-27-shentey@gmail.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* hw/isa/piix: Rename functions to be shared for PCI interrupt triggeringBernhard Beschow2023-10-221-36/+36
| | | | | | | | | | PIIX4 will get the same optimizations which are already implemented for PIIX3. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231007123843.127151-26-shentey@gmail.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4Bernhard Beschow2023-10-221-71/+9
| | | | | | | | | | Resolves duplicate code. Also makes PIIX4 respect the PIIX3 properties which get added, too. This allows for using PIIX4 in the PC machine. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-Id: <20231007123843.127151-25-shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* hw/isa/piix: Share PIIX3's base class with PIIX4Bernhard Beschow2023-10-221-55/+30
| | | | | | | | | | Having a common base class will allow for futher code sharing between PIIX3 and PIIX4. Moreover, it makes PIIX4 implement the acpi-dev-aml-interface. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231007123843.127151-24-shentey@gmail.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* hw/isa/piix: Harmonize names of reset control memory regionsBernhard Beschow2023-10-221-2/+2
| | | | | | | | | | | There is no need for having different names here. Having the same name further allows code to be shared between PIIX3 and PIIX4. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231007123843.127151-23-shentey@gmail.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* hw/isa/piix: Allow for optional PIT creation in PIIX3Bernhard Beschow2023-10-221-0/+6
| | | | | | | | | | | | | In the PC machine, the PIT is created in board code to allow it to be virtualized with various virtualization techniques. So explicitly disable its creation in the PC machine via a property which defaults to enabled. Once the PIIX implementations are consolidated this default will keep Malta working without further ado. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-Id: <20231007123843.127151-22-shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* hw/isa/piix: Allow for optional PIC creation in PIIX3Bernhard Beschow2023-10-221-2/+19
| | | | | | | | | | | | | In the PC machine, the PIC is created in board code to allow it to be virtualized with various virtualization techniques. So explicitly disable its creation in the PC machine via a property which defaults to enabled. Once the PIIX implementations are consolidated this default will keep Malta working without further ado. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-Id: <20231007123843.127151-21-shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* hw/isa/piix3: Merge hw/isa/piix4.cBernhard Beschow2023-10-221-0/+623
Now that the PIIX3 and PIIX4 device models are sufficiently prepared, their implementations can be merged into one file for further consolidation. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231007123843.127151-20-shentey@gmail.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>