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2020-09-09hw/riscv: sifive_u: Connect a DMA controllerBin Meng3-0/+42
SiFive FU540 SoC integrates a platform DMA controller with 4 DMA channels. This connects the exsiting SiFive PDMA model to the SoC, and adds its device tree data as well. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-17-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-09hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng10-22/+40
At present the CLINT timestamp is using a hard-coded timebase frequency value SIFIVE_CLINT_TIMEBASE_FREQ. This might not be true for all boards. Add a new 'timebase-freq' property to the CLINT device, and update various functions to accept this as a parameter. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-16-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-09hw/riscv: microchip_pfsoc: Hook GPIO controllersBin Meng2-0/+17
Microchip PolarFire SoC integrates 3 GPIOs controllers. It seems enough to create unimplemented devices to cover their register spaces at this point. With this commit, QEMU can boot to U-Boot (2nd stage bootloader) all the way to the Linux shell login prompt, with a modified HSS (1st stage bootloader). For detailed instructions on how to create images for the Icicle Kit board, please check QEMU RISC-V WiKi page at: https://wiki.qemu.org/Documentation/Platforms/RISCV Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1598924352-89526-15-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-09hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMsBin Meng2-0/+46
Microchip PolarFire SoC integrates 2 Candence GEMs to provide IEEE 802.3 standard-compliant 10/100/1000 Mbps ethernet interface. On the Icicle Kit board, GEM0 connects to a PHY at address 8 while GEM1 connects to a PHY at address 9. The 2nd stage bootloader (U-Boot) is using GEM1 by default, so we must specify 2 '-nic' options from the command line in order to get a working ethernet. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1598924352-89526-14-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-09hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23Bin Meng4-3/+7
When cadence_gem model was created for Xilinx boards, the PHY address was hard-coded to 23 in the GEM model. Now that we have introduced a property we can use that to tell GEM model what our PHY address is. Change all boards' GEM 'phy-addr' property value to 23, and set the PHY address default value to 0 in the GEM model. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-13-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-09hw/net: cadence_gem: Add a new 'phy-addr' propertyBin Meng2-2/+5
At present the PHY address of the PHY connected to GEM is hard-coded to either 23 (BOARD_PHY_ADDRESS) or 0. This might not be the case for all boards. Add a new 'phy-addr' property so that board can specify the PHY address for each GEM instance. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-12-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-09hw/riscv: microchip_pfsoc: Connect a DMA controllerBin Meng3-0/+27
On the Icicle Kit board, the HSS firmware utilizes the on-chip DMA controller to move the 2nd stage bootloader in the system memory. Let's connect a DMA controller to Microchip PolarFire SoC. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-11-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-09hw/dma: Add SiFive platform DMA controller emulationBin Meng4-0/+374
Microchip PolarFire SoC integrates a DMA engine that supports: * Independent concurrent DMA transfers using 4 DMA channels * Generation of interrupts on various conditions during execution which is actually an IP reused from the SiFive FU540 chip. This creates a model to support both polling and interrupt modes. Signed-off-by: Bin Meng <bin.meng@windriver.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-10-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-09hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD cardBin Meng3-0/+28
Microchip PolarFire SoC integrates one Cadence SDHCI controller. On the Icicle Kit board, one eMMC chip and an external SD card connect to this controller depending on different configuration. As QEMU does not support eMMC yet, we just emulate the SD card configuration. To test this, the Hart Software Services (HSS) should choose the SD card configuration: $ cp boards/icicle-kit-es/def_config.sdcard .config $ make BOARD=icicle-kit-es The SD card image can be built from the Yocto BSP at: https://github.com/polarfire-soc/meta-polarfire-soc-yocto-bsp Note the generated SD card image should be resized before use: $ qemu-img resize /path/to/sdcard.img 4G Launch QEMU with the following command: $ qemu-system-riscv64 -nographic -M microchip-icicle-kit -sd sdcard.img Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-9-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-09hw/sd: Add Cadence SDHCI emulationBin Meng4-0/+245
Cadence SD/SDIO/eMMC Host Controller (SD4HC) is an SDHCI compatible controller. The SDHCI compatible registers start from offset 0x200, which are called Slot Register Set (SRS) in its datasheet. This creates a Cadence SDHCI model built on top of the existing generic SDHCI model. Cadence specific Host Register Set (HRS) is implemented to make guest software happy. Signed-off-by: Bin Meng <bin.meng@windriver.com> Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-8-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-09hw/riscv: microchip_pfsoc: Connect 5 MMUARTsBin Meng3-0/+51
Microchip PolarFire SoC has 5 MMUARTs, and the Icicle Kit board wires 4 of them out. Let's connect all 5 MMUARTs. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-7-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-09hw/char: Add Microchip PolarFire SoC MMUART emulationBin Meng5-0/+153
Microchip PolarFire SoC MMUART is ns16550 compatible, with some additional registers. Create a simple MMUART model built on top of the existing ns16550 model. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-6-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-09hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit boardBin Meng6-0/+415
This is an initial support for Microchip PolarFire SoC Icicle Kit. The Icicle Kit board integrates a PolarFire SoC, with one SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA. For more details about Microchip PolarFire Soc, please see: https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga Unlike SiFive FU540, the RISC-V core resect vector is at 0x20220000. The following perepherals are created as an unimplemented device: - Bus Error Uint 0/1/2/3/4 - L2 cache controller - SYSREG - MPUCFG - IOSCBCFG More devices will be added later. The BIOS image used by this machine is hss.bin, aka Hart Software Services, which can be built from: https://github.com/polarfire-soc/hart-software-services To launch this machine: $ qemu-system-riscv64 -nographic -M microchip-icicle-kit The memory is set to 1 GiB by default to match the hardware. A sanity check on ram size is performed in the machine init routine to prompt user to increase the RAM size to > 1 GiB when less than 1 GiB ram is detected. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-5-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-09target/riscv: cpu: Set reset vector based on the configured property valueBin Meng4-5/+6
Now that we have the newly introduced 'resetvec' property in the RISC-V CPU and HART, instead of hard-coding the reset vector addr in the CPU's instance_init(), move that to riscv_cpu_realize() based on the configured property value from the RISC-V machines. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1598924352-89526-4-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-09hw/riscv: hart: Add a new 'resetvec' propertyBin Meng2-0/+4
RISC-V machines do not instantiate RISC-V CPUs directly, instead they do that via the hart array. Add a new property for the reset vector address to allow the value to be passed to the CPU, before CPU is realized. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1598924352-89526-3-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-09target/riscv: cpu: Add a new 'resetvec' propertyBin Meng2-0/+2
Currently the reset vector address is hard-coded in a RISC-V CPU's instance_init() routine. In a real world we can have 2 exact same CPUs except for the reset vector address, which is pretty common in the RISC-V core IP licensing business. Normally reset vector address is a configurable parameter. Let's create a 64-bit property to store the reset vector address which covers both 32-bit and 64-bit CPUs. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1598924352-89526-2-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-09riscv: sifive_test: Allow 16-bit writes to memory regionNathan Chancellor1-1/+1
When shutting down the machine running a mainline Linux kernel, the following error happens: $ build/riscv64-softmmu/qemu-system-riscv64 -bios default -M virt \ -display none -initrd rootfs.cpio -kernel Image -m 512m \ -nodefaults -serial mon:stdio ... Requesting system poweroff [ 4.999630] reboot: Power down sbi_trap_error: hart0: trap handler failed (error -2) sbi_trap_error: hart0: mcause=0x0000000000000007 mtval=0x0000000000100000 sbi_trap_error: hart0: mepc=0x000000008000d4cc mstatus=0x0000000000001822 sbi_trap_error: hart0: ra=0x000000008000999e sp=0x0000000080015c78 sbi_trap_error: hart0: gp=0xffffffe000e76610 tp=0xffffffe0081b89c0 sbi_trap_error: hart0: s0=0x0000000080015c88 s1=0x0000000000000040 sbi_trap_error: hart0: a0=0x0000000000000000 a1=0x0000000080004024 sbi_trap_error: hart0: a2=0x0000000080004024 a3=0x0000000080004024 sbi_trap_error: hart0: a4=0x0000000000100000 a5=0x0000000000005555 sbi_trap_error: hart0: a6=0x0000000000004024 a7=0x0000000080011158 sbi_trap_error: hart0: s2=0x0000000000000000 s3=0x0000000080016000 sbi_trap_error: hart0: s4=0x0000000000000000 s5=0x0000000000000000 sbi_trap_error: hart0: s6=0x0000000000000001 s7=0x0000000000000000 sbi_trap_error: hart0: s8=0x0000000000000000 s9=0x0000000000000000 sbi_trap_error: hart0: s10=0x0000000000000000 s11=0x0000000000000008 sbi_trap_error: hart0: t0=0x0000000000000000 t1=0x0000000000000000 sbi_trap_error: hart0: t2=0x0000000000000000 t3=0x0000000000000000 sbi_trap_error: hart0: t4=0x0000000000000000 t5=0x0000000000000000 sbi_trap_error: hart0: t6=0x0000000000000000 The kernel does a 16-bit write when powering off the machine, which was allowed before commit 5d971f9e67 ("memory: Revert "memory: accept mismatching sizes in memory_region_access_valid""). Make min_access_size match reality so that the machine can shut down properly now. Cc: qemu-stable@nongnu.org Fixes: 88a07990fa ("SiFive RISC-V Test Finisher") Fixes: 5d971f9e67 ("memory: Revert "memory: accept mismatching sizes in memory_region_access_valid"") Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200901055822.2721209-1-natechancellor@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-09target/riscv: Fix bug in getting trap cause name for trace_riscv_trapYifei Jiang3-2/+14
When the cause number is equal to or greater than 23, print "(unknown)" in trace_riscv_trap. The max valid number of riscv_excp_names is 23, so the last excpetion "guest_store_page_fault" can not be printed. In addition, the current check of cause is invalid for riscv_intr_names. So introduce riscv_cpu_get_trap_name to get the trap cause name. Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200814035819.1214-1-jiangyifei@huawei.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-08docs: update build system documentationPaolo Bonzini1-86/+11
Most of the Makefile bits are obsolete and can be removed. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08meson: remove linkage of sdl to baumBruce Rogers1-2/+2
Ever since commit 537fe2d63f744e7c96ff45b60d09486a81958e06 there has been a 'linkage' to sdl for compiling baum.c. Originally it had to do with including sdl cflags for any file including sdl headers. There is no longer any such need for baum.c, but the association has persisted in the make system, and with the switch to meson it has now become a hard requirement, which now causes chardev-baum.so to not be produced if sdl is not configured. Remove this bogus linkage. Signed-off-by: Bruce Rogers <brogers@suse.com> Message-Id: <20200903152933.97838-1-brogers@suse.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08meson: Convert undefsym.sh to undefsym.pyYonggang Luo3-21/+50
Shell scripts are not easily invoked from the build process on MSYS, so convert undefsym.sh to a python script. Signed-off-by: Yonggang Luo <luoyonggang@gmail.com> Message-Id: <20200902170054.810-3-luoyonggang@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08fuzz: Add support for custom fuzzing libraryAlexander Bulekov2-4/+12
On oss-fuzz, we must use the LIB_FUZZING_ENGINE and CFLAGS environment variables, rather than -fsanitize=fuzzer. With this change, when LIB_FUZZING_ENGINE is set, the --enable-fuzzing configure option will use that environment variable during the linking stage, rather than -fsanitize=fuzzer Signed-off-by: Alexander Bulekov <alxndr@bu.edu> Message-Id: <20200902173652.307222-3-alxndr@bu.edu> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08meson: specify fuzz linker script as a project argAlexander Bulekov2-4/+8
With this change, the fuzzer-linker script should be specified outside any --start-group/--end-group pairs. We need this on oss-fuzz, where partially applying the linker-script results in a linker failure Signed-off-by: Alexander Bulekov <alxndr@bu.edu> Message-Id: <20200902173652.307222-2-alxndr@bu.edu> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08oss-fuzz: fix rpathAlexander Bulekov1-1/+1
Prior to this change, readelf -d build/out/qemu/qemu-fuzz-i386-target-virtio-net-slirp ... 0x000000000000000f (RPATH) Library rpath: ['$$ORIGIN/lib':$ORIGIN/migration:$ORIGIN/] As of 1a4db552d8 ("ninjatool: quote dollars in variables"), we don't need to manually double the dollars. Also, remove the single-quotes as they are copied into the rpath. After this change: 0x000000000000000f (RPATH) Library rpath: [$ORIGIN/lib:$ORIGIN/migration:$ORIGIN/] Signed-off-by: Alexander Bulekov <alxndr@bu.edu> Message-Id: <20200902142657.112879-3-alxndr@bu.edu> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08configure: update dtc submoduleYonggang Luo1-4/+7
Update the dtc submodule in configure already and symlink dtc after git submodule update, because on win32 symlinks to non-existing folders are forbidden. Signed-off-by: Yonggang Luo <luoyonggang@gmail.com> Message-Id: <20200902170054.810-2-luoyonggang@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08docs: suggest Meson replacements for various configure functionsPaolo Bonzini1-3/+7
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08configure: drop dead variables and functionsPaolo Bonzini1-15/+1
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08configure: do not include dependency flags in QEMU_CFLAGS and LIBSPaolo Bonzini7-46/+7
All Meson executables should specify their dependencies explicitly, either directly or indirectly via declare_dependency. Makefiles instead did not propagate dependencies correctly from static libraries, for example. Therefore, flags for dependencies need not be included in QEMU_CFLAGS. LIBS is not used at all, so drop that one as well. In a few cases the dependencies were not yet specified, so add them. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08meson: get opengl compilation flags from OPENGL_CFLAGSPaolo Bonzini2-1/+3
The opengl compilation flags were added to QEMU_CFLAGS. We do not want them to be added to all compilation commands, so export them also via OPENGL_CFLAGS rather than via QEMU_CFLAGS. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08meson: get glib compilation flags from GLIB_CFLAGSPaolo Bonzini2-12/+14
The glib compilation flags were added to QEMU_CFLAGS. While we still want them to be added to all compilation commands (at least for now), do that via GLIB_CFLAGS rather than via QEMU_CFLAGS. This shows that glib is a special case and makes it clearer that QEMU_CFLAGS is only about compiler commands and not dependencies. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08configure: do not look for install(1)Paolo Bonzini3-56/+2
It is not used anymore, so there is no Solaris-specific check to perform. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08configure: remove unnecessary libm testPaolo Bonzini1-14/+0
The same test is already performed by meson.build. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08configure: move -ldl test to mesonPaolo Bonzini3-2/+5
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08meson: keep all compiler flags detection togetherPaolo Bonzini1-13/+17
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08configure: move disassembler configuration to mesonPaolo Bonzini4-94/+45
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08Makefile: inline the relevant parts of rules.makPaolo Bonzini5-180/+26
Most of rules.mak is not used anymore, just inline what's needed. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08Makefile: remove dead variables and includesPaolo Bonzini3-94/+0
Makefile.objs, the .d files and various CONFIG_* symbols are not used anymore by the Make side of the build; they are only processed by Meson. We can delete them. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08meson: compute config_all_devices directlyPaolo Bonzini3-16/+2
There is no need anymore to produce config-all-devices.mak, compute the resulting dictionary directly instead of going through grepy.sh. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08configure: remove dead code for in-tree buildsPaolo Bonzini1-12/+2
The $pwd_is_source_path variable is never "y", since configure re-executes itself from a build directory. Remove code that will never run. Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08meson: convert migration/initrd-stressMarc-André Lureau4-14/+25
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20200828110734.1638685-17-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08meson: fix migration/stress compilation with glibc>=2.30Marc-André Lureau2-0/+5
gettid() was introduced with glibc 2.30. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20200828110734.1638685-16-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08tests/migration/stress: remove unused exit_successMarc-André Lureau1-13/+0
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20200828110734.1638685-15-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08meson: convert the speed testsPaolo Bonzini4-13/+29
Use meson benchmark() for them, adjust mtest2make.py for that. A new target "make bench" can be used to run all benchmarks. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20200828110734.1638685-14-marcandre.lureau@redhat.com> [Rewrite mtest2make part. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08tests: do not print benchmark output to stdoutMarc-André Lureau3-9/+9
As this makes the TAP output invalid. Use g_test_message(). Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20200828110734.1638685-13-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08meson: convert atomic*-benchMarc-André Lureau2-5/+10
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20200828110734.1638685-11-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08meson: convert vhost-user-bridgeMarc-André Lureau2-2/+9
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20200828110734.1638685-10-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08meson: remove old socket_scm_helper ruleMarc-André Lureau1-1/+0
It was covered already in commit d3ca592b3c10 ("meson: convert check-block") Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20200828110734.1638685-9-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08meson: move keyutils dependency checkMarc-André Lureau2-29/+3
Since there is not minimum version specified, and it's a test-only dependency, it's fair to depend on a version that ships with a .pc I suppose. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20200828110734.1638685-8-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08meson: convert the unit testsMarc-André Lureau3-253/+174
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20200828110734.1638685-7-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-08ipxe: update binariesGerd Hoffmann8-0/+0
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>