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* ppc/pnv: Introduce PnvChipClass::xscom_core_base() methodGreg Kurz2019-12-171-7/+24
* ppc/pnv: Introduce PnvChipClass::intc_print_info() methodGreg Kurz2019-12-171-5/+25
* ppc/pnv: Introduce PnvMachineClass::dt_power_mgt()Greg Kurz2019-12-171-4/+6
* ppc/pnv: Introduce PnvMachineClass and PnvMachineClass::compatGreg Kurz2019-12-171-14/+18
* ppc/pnv: Drop PnvPsiClass::chip_typeGreg Kurz2019-12-171-3/+0
* ppc/pnv: Introduce PnvPsiClass::compatGreg Kurz2019-12-171-14/+11
* ppc/pnv: Fix OCC common area region mappingCédric Le Goater2019-12-172-9/+6
* ppc/pnv: Introduce PBA registersCédric Le Goater2019-12-173-34/+119
* ppc/pnv: populate the DT with realized XSCOM devicesCédric Le Goater2019-12-171-1/+4
* ppc/pnv: Loop on the whole hierarchy to populate the DT with the XSCOM nodesCédric Le Goater2019-12-171-1/+6
* target/ppc: Add SPR TBU40Suraj Jitindar Singh2019-12-171-0/+13
* target/ppc: Work [S]PURR implementation and add HV supportSuraj Jitindar Singh2019-12-171-10/+7
* target/ppc: Implement the VTB for HV accessSuraj Jitindar Singh2019-12-171-0/+16
* ppc/pnv: add a LPC Controller model for POWER10Cédric Le Goater2019-12-172-11/+44
* ppc/pnv: add a PSI bridge model for POWER10Cédric Le Goater2019-12-172-8/+44
* ppc/psi: cleanup definitionsCédric Le Goater2019-12-171-2/+5
* ppc/pnv: Introduce a POWER10 PnvChip and a powernv10 machineCédric Le Goater2019-12-173-11/+180
* ppc: Don't use CPUPPCState::irq_input_state with modern Book3s CPU modelsGreg Kurz2019-12-171-14/+2
* ppc: Deassert the external interrupt pin in KVM on resetGreg Kurz2019-12-171-0/+8
* spapr: Simplify ovec diffDavid Gibson2019-12-173-37/+15
* spapr: Fold h_cas_compose_response() into h_client_architecture_support()David Gibson2019-12-172-63/+53
* spapr: Improve handling of fdt buffer sizeDavid Gibson2019-12-171-22/+11
* spapr: Don't trigger a CAS reboot for XICS/XIVE mode changeoverDavid Gibson2019-12-171-20/+13
* ppc: well form kvmppc_hint_smt_possible error hint helperVladimir Sementsov-Ogievskiy2019-12-171-1/+1
* ppc/pnv: Clarify how the TIMA is accessed on a multichip systemCédric Le Goater2019-12-171-0/+14
* spapr: Pass the maximum number of vCPUs to the KVM interrupt controllerGreg Kurz2019-12-171-3/+5
* ppc/spapr: Implement the XiveFabric interfaceCédric Le Goater2019-12-171-0/+39
* ppc/pnv: Implement the XiveFabric interfaceCédric Le Goater2019-12-171-0/+35
* ppc/pnv: Fix TIMA indirect accessCédric Le Goater2019-12-171-0/+17
* ppc: Introduce a ppc_cpu_pir() helperCédric Le Goater2019-12-171-2/+7
* ppc/pnv: Instantiate cores separatelyGreg Kurz2019-12-171-18/+12
* ppc/pnv: Create BMC devices at machine initCédric Le Goater2019-12-172-20/+33
* ppc/pnv: Add HIOMAP commandsCédric Le Goater2019-12-173-0/+116
* ppc/pnv: Add a LPC "ranges" propertyCédric Le Goater2019-12-171-1/+13
* spapr: Abort if XICS interrupt controller cannot be initializedGreg Kurz2019-12-171-11/+2
* xics: Link ICS_PROP_XICS property to ICSState::xics pointerGreg Kurz2019-12-172-9/+3
* ppc/pnv: Link "chip" property to PnvXive::chip pointerGreg Kurz2019-12-171-2/+2
* ppc/pnv: Link "chip" property to PnvCore::chip pointerGreg Kurz2019-12-172-10/+4
* ppc/pnv: Link "chip" property to PnvHomer::chip pointerGreg Kurz2019-12-172-14/+14
* ppc/pnv: Link "psi" property to PnvOCC::psi pointerGreg Kurz2019-12-172-15/+13
* ppc/pnv: Link "psi" property to PnvLpc::psi pointerGreg Kurz2019-12-172-15/+12
* xive: Link "xive" property to XiveSource::xive pointerGreg Kurz2019-12-171-2/+1
* ppc/pnv: Drop "chip" link from POWER9 PSI objectGreg Kurz2019-12-171-2/+0
* ppc/pnv: Add a "/qemu" device tree nodeCédric Le Goater2019-12-171-0/+3
* ppc/pnv: Add a PNOR modelCédric Le Goater2019-12-173-1/+152
* hw: add compat machines for 5.0Cornelia Huck2019-12-141-1/+12
* virtio-blk: advertise F_WCE (F_FLUSH) if F_CONFIG_WCE is advertisedEvgeny Yakovlev2019-12-131-1/+1
* ppc/spapr_events: fix potential NULL pointer dereference in rtas_event_log_de...PanNengyuan2019-11-261-0/+1
* spapr: Work around spurious warnings from vfio INTx initializationDavid Gibson2019-11-261-1/+10
* spapr: Handle irq backend changes with VFIO PCI devicesDavid Gibson2019-11-261-0/+6