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2025-01-13target: Replace DEVICE(object_new) -> qdev_new()Philippe Mathieu-Daudé2-2/+2
Prefer QDev API for QDev objects, avoid the underlying QOM layer. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20240216110313.17039-8-philmd@linaro.org>
2025-01-13pc-bios/meson.build: Silent unuseful DTC warningsPhilippe Mathieu-Daudé1-1/+2
QEMU consumes some device tree blobs, so these have been committed to the tree in as firmware, along with the device tree source used to generate them. We know the blobs are "good enough" to have QEMU boot a system, so we don't really maintain and rebuild the sources. These blobs were generated with older 'dtc' binaries. We use the v1.6.1 version since 2021 (commit 962fde57b7 "dtc: Update to version 1.6.1"). Since commit 6e0dc9d2a8 ("meson: compile bundled device trees"), if dtc binary is available, it is directly used to compile the device tree sources. New versions of 'dtc' add checks which display warnings or errors. Our sources are a bit old, so dtc v1.6.1 now emit the following warnings on a fresh build: [163/3414] Generating pc-bios/canyonlands.dts with a custom command pc-bios/canyonlands.dts:47.9-50.4: Warning (unit_address_vs_reg): /memory: node has a reg or ranges property, but no unit name pc-bios/canyonlands.dts:210.13-429.5: Warning (unit_address_vs_reg): /plb/opb: node has a reg or ranges property, but no unit name pc-bios/canyonlands.dts:464.26-504.5: Warning (pci_bridge): /plb/pciex@d00000000: node name is not "pci" or "pcie" pc-bios/canyonlands.dts:506.26-546.5: Warning (pci_bridge): /plb/pciex@d20000000: node name is not "pci" or "pcie" pc-bios/canyonlands.dtb: Warning (unit_address_format): Failed prerequisite 'pci_bridge' pc-bios/canyonlands.dtb: Warning (pci_device_reg): Failed prerequisite 'pci_bridge' pc-bios/canyonlands.dtb: Warning (pci_device_bus_num): Failed prerequisite 'pci_bridge' pc-bios/canyonlands.dts:268.14-289.7: Warning (avoid_unnecessary_addr_size): /plb/opb/ebc/ndfc@3,0: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property [164/3414] Generating pc-bios/petalogix-s3adsp1800.dts with a custom command pc-bios/petalogix-s3adsp1800.dts:258.33-266.5: Warning (interrupt_provider): /plb/interrupt-controller@81800000: Missing #address-cells in interrupt provider [165/3414] Generating pc-bios/petalogix-ml605.dts with a custom command pc-bios/petalogix-ml605.dts:234.39-241.5: Warning (interrupt_provider): /axi/interrupt-controller@81800000: Missing #address-cells in interrupt provider [177/3414] Generating pc-bios/bamboo.dts with a custom command pc-bios/bamboo.dts:45.9-48.4: Warning (unit_address_vs_reg): /memory: node has a reg or ranges property, but no unit name pc-bios/bamboo.dts:87.13-154.5: Warning (unit_address_vs_reg): /plb/opb: node has a reg or ranges property, but no unit name pc-bios/bamboo.dts:198.3-50: Warning (chosen_node_stdout_path): /chosen:linux,stdout-path: Use 'stdout-path' instead pc-bios/bamboo.dts:87.13-154.5: Warning (interrupts_property): /plb/opb: Missing interrupt-parent pc-bios/bamboo.dts:100.14-108.6: Warning (interrupts_property): /plb/opb/ebc: Missing interrupt-parent From QEMU perspective, these warnings are not really useful. It is the responsibility of developers adding DT source/blob to QEMU repository to check the source doesn't produce warnings, but as long as the blob is useful enough, QEMU can consume it. So these warnings don't add any value, instead they are noisy and might distract us to focus on important warnings. Better disable them. 'dtc' provides the '--quiet' option for that [*]: $ dtc --help Usage: dtc [options] <input file> Options: -[qI:O:o:V:d:R:S:p:a:fb:i:H:sW:E:@AThv] -q, --quiet Quiet: -q suppress warnings, -qq errors, -qqq all Update meson to disable these unuseful DTC warnings. [*] https://lore.kernel.org/qemu-devel/CAFEAcA-WJ9J1YQunJ+bSG=wnpxh1By+Bf18j2CyV7G0vZ=8b7g@mail.gmail.com/ Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <20231006064750.33852-1-philmd@linaro.org>
2025-01-13docs/system/arm/virt: mention specific migration informationPierrick Bouvier1-0/+4
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20241219183211.3493974-4-pierrick.bouvier@linaro.org [PMM: Removed a paragraph about using non-versioned models.] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-01-13target/arm: change default pauth algorithm to impdefPierrick Bouvier6-9/+26
Pointer authentication on aarch64 is pretty expensive (up to 50% of execution time) when running a virtual machine with tcg and -cpu max (which enables pauth=on). The advice is always: use pauth-impdef=on. Our documentation even mentions it "by default" in docs/system/introduction.rst. Thus, we change the default to use impdef by default. This does not affect kvm or hvf acceleration, since pauth algorithm used is the one from host cpu. This change is retro compatible, in terms of cli, with previous versions, as the semantic of using -cpu max,pauth-impdef=on, and -cpu max,pauth-qarma3=on is preserved. The new option introduced in previous patch and matching old default is -cpu max,pauth-qarma5=on. It is retro compatible with migration as well, by defining a backcompat property, that will use qarma5 by default for virt machine <= 9.2. Tested by saving and restoring a vm from qemu 9.2.0 into qemu-master (10.0) for cpus neoverse-n2 and max. Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241219183211.3493974-3-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-01-13tests/tcg/aarch64: force qarma5 for pauth-3 testPeter Maydell1-0/+3
The pauth-3 test explicitly tests that a computation of the pointer-authentication produces the expected result. This means that it must be run with the QARMA5 algorithm. Explicitly set the pauth algorithm when running this test, so that it doesn't break when we change the default algorithm the 'max' CPU uses. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-01-13target/arm: add new property to select pauth-qarma5Pierrick Bouvier5-12/+31
Before changing default pauth algorithm, we need to make sure current default one (QARMA5) can still be selected. $ qemu-system-aarch64 -cpu max,pauth-qarma5=on ... Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241219183211.3493974-2-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-01-13target/arm: Move minor arithmetic helpers out of helper.cPeter Maydell4-285/+297
helper.c includes some small TCG helper functions used for mostly arithmetic instructions. These are TCG only and there's no need for them to be in the large and unwieldy helper.c. Move them out to their own source file in the tcg/ subdirectory, together with the op_addsub.h multiply-included template header that they use. Since we are moving op_addsub.h, we take the opportunity to give it a name which matches our convention for files which are not true header files but which are #included from other C files: op_addsub.c.inc. (Ironically, this means that helper.c no longer contains any TCG helper function definitions at all.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250110131211.2546314-1-peter.maydell@linaro.org Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2025-01-13tests/qtest/boot-serial-test: Initialize PL011 Control registerPhilippe Mathieu-Daudé1-1/+6
The tests using the PL011 UART of the virt and raspi machines weren't properly enabling the UART and its transmitter previous to sending characters. Follow the PL011 manual initialization recommendation by setting the proper bits of the control register. Update the ASM code prefixing: *UART_CTRL = UART_ENABLE | TX_ENABLE; to: while (true) { *UART_DATA = 'T'; } Note, since commit 51b61dd4d56 ("hw/char/pl011: Warn when using disabled transmitter") incomplete PL011 initialization can be logged using the '-d guest_errors' command line option. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-01-13tests/qtest/boot-serial-test: Reorder pair of instructions in PL011 testPhilippe Mathieu-Daudé1-1/+1
In the next commit we are going to use a different value for the $w1 register, maintaining the same $x2 value. In order to keep the next commit trivial to review, set $x2 before $w1. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Fabiano Rosas <farosas@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-01-13tests/qtest/boot-serial-test: Reduce for() loop in PL011 testsPhilippe Mathieu-Daudé1-6/+6
Since registers are not modified, we don't need to refill their values. Directly jump to the previous store instruction to keep filling the TXDAT register. The equivalent C code remains: while (true) { *UART_DATA = 'T'; } Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Fabiano Rosas <farosas@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-01-13tests/qtest/boot-serial-test: Improve ASM comments of PL011 testsPhilippe Mathieu-Daudé1-9/+9
Re-indent ASM comments adding the 'loop:' label. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Fabiano Rosas <farosas@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-01-13hw/misc: cast rpm to uint64_tTigran Sogomonian1-2/+3
The value of an arithmetic expression 'rpm * NPCM7XX_MFT_PULSE_PER_REVOLUTION' is a subject to overflow because its operands are not cast to a larger data type before performing arithmetic. Thus, need to cast rpm to uint64_t. Found by Linux Verification Center (linuxtesting.org) with SVACE. Signed-off-by: Tigran Sogomonian <tsogomonian@astralinux.ru> Reviewed-by: Patrick Leis <venture@google.com> Reviewed-by: Hao Wu <wuhaotsh@google.com> Message-id: 20241226130311.1349-1-tsogomonian@astralinux.ru Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-01-13hw/arm_sysctl: fix extracting 31th bit of valAnastasia Belova1-1/+1
1 << 31 is casted to uint64_t while bitwise and with val. So this value may become 0xffffffff80000000 but only 31th "start" bit is required. This is not possible in practice because the MemoryRegionOps uses the default max access size of 4 bytes and so none of the upper bytes of val will be set, but the bitfield extract API is clearer anyway. Use the bitfield extract() API instead. Found by Linux Verification Center (linuxtesting.org) with SVACE. Signed-off-by: Anastasia Belova <abelova@astralinux.ru> Message-id: 20241220125429.7552-1-abelova@astralinux.ru Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: add clarification to commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-01-11MAINTAINERS: Remove myself from reviewersWainer dos Santos Moschetta1-2/+0
The time I spent contributing to QEMU was great, but I've not been active for a long time now. So removing myself from the reviewers list of "Integration Testing with the Avocado framework" and "Build and test automation" subsystems. Signed-off-by: Wainer dos Santos Moschetta <wainersm@redhat.com> Message-Id: <20250103194450.360789-1-wainersm@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250108121054.1126164-33-alex.bennee@linaro.org>
2025-01-11dockerfiles: Remove 'MAINTAINER' entry in debian-tricore-cross.dockerPhilippe Mathieu-Daudé1-2/+0
AMSAT closed its email service [*] so my personal email address is now defunct. Remove it to avoid bouncing emails. [*] https://web.archive.org/web/20240617194936/https://forum.amsat-dl.org/index.php?thread/4581-amsat-mail-alias-service-to-end-august-1-2024/ Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20250102152513.61065-1-philmd@linaro.org> [AJB: update URL to web.archive.org] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250108121054.1126164-32-alex.bennee@linaro.org>
2025-01-11pc-bios: ensure keymaps dependencies set vnc testsAlex Bennée2-10/+9
I was seeing failures on vnc-display-test on FreeBSD: make vm-build-freebsd V=1 TARGET_LIST=aarch64-softmmu BUILD_TARGET=check-qtest QEMU_LOCAL=1 DEBUG=1 Leads to: qemu-system-aarch64: -vnc none: could not read keymap file: 'en-us' Broken pipe ../src/tests/qtest/libqtest.c:196: kill_qemu() tried to terminate QEMU process but encountered exit status 1 (expected 0) which was as far as I could tell because we don't populate the $BLD/pc-bios/keymaps (although scripts/symlink-install-tree.py attempts to symlink qemu-bundle/usr/local/share/qemu/keymaps/ to that dir). Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250108121054.1126164-31-alex.bennee@linaro.org>
2025-01-11tests/vm: allow interactive login as rootAlex Bennée2-3/+9
This is useful when debugging and you want to add packages to an image. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250108121054.1126164-30-alex.bennee@linaro.org>
2025-01-11tests/vm: partially un-tabify help outputAlex Bennée1-13/+13
While the make syntax itself uses tabs having a mixture of tabs and spaces in the vm-help output make no sense and confuses things lining up between terminal and editor. Fix that. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250108121054.1126164-29-alex.bennee@linaro.org>
2025-01-11tests/vm: fix build_path based pathAlex Bennée1-2/+1
We no longer need to go into the per-arch build directories to find the build directories binary. Lets call it directly. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250108121054.1126164-28-alex.bennee@linaro.org>
2025-01-11tests/lcitool: remove temp workaround for debian mips64elDaniel P. Berrangé2-29/+9
The workaround applied in commit c60473d29254b79d9437eface8b342e84663ba66 Author: Alex Bennée <alex.bennee@linaro.org> Date: Wed Oct 2 10:03:33 2024 +0200 testing: bump mips64el cross to bookworm and fix package list Is no longer required since the affected builds are now fixed. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Message-Id: <20241217133525.3836570-1-berrange@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250108121054.1126164-27-alex.bennee@linaro.org>
2025-01-11tests/docker: move riscv64 cross container from sid to trixieAlex Bennée2-3/+5
Although riscv64 isn't going to be a release architecture for trixie the packages are still built while it is testing. Moving from sid will also avoid some of the volatility we get from tracking the bleeding edge. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250108121054.1126164-26-alex.bennee@linaro.org>
2025-01-11tests/lcitool: bump to latest version of libvirt-ciAlex Bennée3-2/+2
We will shortly need this to build our riscv64 cross container. However to keep the delta down just do the bump first. As ccache4 is now preferred for FreeBSD to get the latest version there is a little update in the FreeBSD metadata. Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250108121054.1126164-25-alex.bennee@linaro.org>
2025-01-11tests/functional: extend test_aarch64_virt with vulkan testAlex Bennée1-2/+74
Now that we have virtio-gpu Vulkan support, let's add a test for it. Currently this is using images build by buildroot: https://lists.buildroot.org/pipermail/buildroot/2024-December/768196.html Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250108121054.1126164-24-alex.bennee@linaro.org>
2025-01-10tests/functional: bail aarch64_virt tests early if missing TCGAlex Bennée1-4/+7
The set_machine and require_accelerator steps can bail early so move those to the front of the test functions. While we are at it also clean up some long lines when adding the vm arguments. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250108121054.1126164-23-alex.bennee@linaro.org>
2025-01-10tests/functional: remove unused kernel_command_lineAlex Bennée1-2/+0
The Alpine test boots from the CDROM so we don't --append a command line. Drop the unused code. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250108121054.1126164-22-alex.bennee@linaro.org>
2025-01-10tests/functional: update tuxruntest to use uncompress utilityAlex Bennée1-11/+1
Use the utility functions to reduce code duplication. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250108121054.1126164-21-alex.bennee@linaro.org>
2025-01-10tests/functional: add zstd support to uncompress utilityAlex Bennée1-0/+24
Rather than using the python library (which has a different API anyway) lets just call the binary. zstdtools is already in out qemu.yml so all test containers should have it around. Tests should still use @skipIfMissingCommands('zstd') to gracefully handle when only minimal dependencies have been installed. Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250108121054.1126164-20-alex.bennee@linaro.org>
2025-01-10tests/functional: remove hacky sleep from the testsAlex Bennée1-14/+18
We have proper detection of prompts now so we don't need to guess with sleep() sprinkled through the test. The extra step of calling halt is just to flush the final bits of the log (although the last line is still missed). Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250108121054.1126164-19-alex.bennee@linaro.org>
2025-01-10system/qtest: properly feedback results of clock_[step|set]Alex Bennée1-9/+14
Time will not advance if the system is paused or there are no timer events set for the future. In absence of pending timer events advancing time would make no difference the system state. Attempting to do so would be a bug and the test or device under test would need fixing. Tighten up the result reporting to `FAIL` if time was not advanced. Reviewed-by: Fabiano Rosas <farosas@suse.de> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2687 Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250108121054.1126164-18-alex.bennee@linaro.org>
2025-01-10tests/qtest: remove clock_steps from virtio testsAlex Bennée1-4/+0
In the qtest environment time will not step forward if the system is paused (timers disabled) or we have no timer events to fire. As a result VirtIO events are responded to directly and we don't need to step time forward. We still do timeout processing to handle the fact the target QEMU may not be ready to respond right away. This will usually be due to a slow CI system or if QEMU is running under something like rr. Future qtest patches will assert that time actually changes when a step is requested. Reviewed-by: Fabiano Rosas <farosas@suse.de> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250108121054.1126164-17-alex.bennee@linaro.org>
2025-01-10tests/functional/aarch64: add tests for FEAT_RMEPierrick Bouvier3-0/+171
This boot an OP-TEE environment, and launch a nested guest VM inside it using the Realms feature. We do it for virt and sbsa-ref platforms. Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-Id: <20241220165212.3653495-1-pierrick.bouvier@linaro.org> [AJB: tweak ordering of setup, strip changelog from commit] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Thomas Huth <thuth@redhat.com> Message-Id: <20250108121054.1126164-16-alex.bennee@linaro.org>
2025-01-10tests/functional: update the x86_64 tuxrun testsAlex Bennée1-4/+4
Now there are new up to date images available we should update to them. Cc: Anders Roxell <anders.roxell@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250108121054.1126164-15-alex.bennee@linaro.org>
2025-01-10tests/functional: update the sparc64 tuxrun testsAlex Bennée1-4/+4
Now there are new up to date images available we should update to them. Cc: Anders Roxell <anders.roxell@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250108121054.1126164-14-alex.bennee@linaro.org>
2025-01-10tests/functional: update the s390x tuxrun testsAlex Bennée1-4/+4
Now there are new up to date images available we should update to them. Cc: Anders Roxell <anders.roxell@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250108121054.1126164-13-alex.bennee@linaro.org>
2025-01-10tests/functional: update the riscv64 tuxrun testsAlex Bennée1-8/+8
Now there are new up to date images available we should update to them. Note we re-use the riscv32 kernel and rootfs for test_riscv64_rv32. Cc: Anders Roxell <anders.roxell@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250108121054.1126164-12-alex.bennee@linaro.org>
2025-01-10tests/functional: update the riscv32 tuxrun testsAlex Bennée1-4/+4
Now there are new up to date images available we should update to them. Cc: Anders Roxell <anders.roxell@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250108121054.1126164-11-alex.bennee@linaro.org>
2025-01-10tests/functional: update the ppc64 tuxrun testsAlex Bennée1-8/+8
Now there are new up to date images available we should update to them. Cc: Anders Roxell <anders.roxell@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250108121054.1126164-10-alex.bennee@linaro.org>
2025-01-10tests/functional: update the ppc32 tuxrun testsAlex Bennée1-4/+4
Now there are new up to date images available we should update to them. Cc: Anders Roxell <anders.roxell@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250108121054.1126164-9-alex.bennee@linaro.org>
2025-01-10tests/functional: update the mips64el tuxrun testsAlex Bennée1-4/+4
Now there are new up to date images available we should update to them. Cc: Anders Roxell <anders.roxell@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250108121054.1126164-8-alex.bennee@linaro.org>
2025-01-10tests/functional: update the mips64 tuxrun testsAlex Bennée1-4/+4
Now there are new up to date images available we should update to them. Cc: Anders Roxell <anders.roxell@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250108121054.1126164-7-alex.bennee@linaro.org>
2025-01-10tests/functional: update the mips32el tuxrun testsAlex Bennée1-4/+4
Now there are new up to date images available we should update to them. Cc: Anders Roxell <anders.roxell@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250108121054.1126164-6-alex.bennee@linaro.org>
2025-01-10tests/functional: update the mips32 tuxrun testsAlex Bennée1-4/+4
Now there are new up to date images available we should update to them. Cc: Anders Roxell <anders.roxell@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250108121054.1126164-5-alex.bennee@linaro.org>
2025-01-10tests/functional: add a m68k tuxrun testsAlex Bennée3-0/+36
We didn't have this before and as it exercises the m68k virt platform it seems worth adding. We don't wait for the shutdown because QEMU will auto-exit on the shutdown. Cc: Laurent Vivier <laurent@vivier.eu> Cc: Anders Roxell <anders.roxell@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250108121054.1126164-4-alex.bennee@linaro.org>
2025-01-10tests/functional: update the i386 tuxrun testsAlex Bennée1-4/+4
Now there are new up to date images available we should update to them. Cc: Anders Roxell <anders.roxell@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250108121054.1126164-3-alex.bennee@linaro.org>
2025-01-10tests/functional: update the arm tuxrun testsAlex Bennée1-14/+14
Now there are new up to date images available we should update to them. Cc: Anders Roxell <anders.roxell@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250108121054.1126164-2-alex.bennee@linaro.org>
2025-01-09multifd: bugfix for incorrect migration data with qatzip compressionYuan Liu1-0/+1
When QPL compression is enabled on the migration channel and the same dirty page changes from a normal page to a zero page in the iterative memory copy, the dirty page will not be updated to a zero page again on the target side, resulting in incorrect memory data on the source and target sides. The root cause is that the target side does not record the normal pages to the receivedmap. The solution is to add ramblock_recv_bitmap_set_offset in target side to record the normal pages. Signed-off-by: Yuan Liu <yuan1.liu@intel.com> Reviewed-by: Jason Zeng <jason.zeng@intel.com> Reviewed-by: Peter Xu <peterx@redhat.com> Message-Id: <20241218091413.140396-4-yuan1.liu@intel.com> Signed-off-by: Fabiano Rosas <farosas@suse.de>
2025-01-09multifd: bugfix for incorrect migration data with QPL compressionYuan Liu1-0/+1
When QPL compression is enabled on the migration channel and the same dirty page changes from a normal page to a zero page in the iterative memory copy, the dirty page will not be updated to a zero page again on the target side, resulting in incorrect memory data on the source and target sides. The root cause is that the target side does not record the normal pages to the receivedmap. The solution is to add ramblock_recv_bitmap_set_offset in target side to record the normal pages. Signed-off-by: Yuan Liu <yuan1.liu@intel.com> Reviewed-by: Jason Zeng <jason.zeng@intel.com> Reviewed-by: Peter Xu <peterx@redhat.com> Message-Id: <20241218091413.140396-3-yuan1.liu@intel.com> Signed-off-by: Fabiano Rosas <farosas@suse.de>
2025-01-09multifd: bugfix for migration using compression methodsYuan Liu1-2/+1
When compression is enabled on the migration channel and the pages processed are all zero pages, these pages will not be sent and updated on the target side, resulting in incorrect memory data on the source and target sides. The root cause is that all compression methods call multifd_send_prepare_common to determine whether to compress dirty pages, but multifd_send_prepare_common does not update the IOV of MultiFDPacket_t when all dirty pages are zero pages. The solution is to always update the IOV of MultiFDPacket_t regardless of whether the dirty pages are all zero pages. Fixes: 303e6f54f9 ("migration/multifd: Implement zero page transmission on the multifd thread.") Cc: qemu-stable@nongnu.org #9.0+ Signed-off-by: Yuan Liu <yuan1.liu@intel.com> Reviewed-by: Jason Zeng <jason.zeng@intel.com> Reviewed-by: Peter Xu <peterx@redhat.com> Message-Id: <20241218091413.140396-2-yuan1.liu@intel.com> Signed-off-by: Fabiano Rosas <farosas@suse.de>
2025-01-09s390x: Fix CSS migrationFabiano Rosas1-1/+1
Commit a55ae46683 ("s390: move css_migration_enabled from machine to css.c") disabled CSS migration globally instead of doing it per-instance. CC: Paolo Bonzini <pbonzini@redhat.com> CC: qemu-stable@nongnu.org #9.1 Fixes: a55ae46683 ("s390: move css_migration_enabled from machine to css.c") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2704 Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20250109185249.23952-8-farosas@suse.de> Signed-off-by: Fabiano Rosas <farosas@suse.de>
2025-01-09migration: Fix arrays of pointers in JSON writerFabiano Rosas2-9/+50
Currently, if an array of pointers contains a NULL pointer, that pointer will be encoded as '0' in the stream. Since the JSON writer doesn't define a "pointer" type, that '0' will now be an uint8, which is different from the original type being pointed to, e.g. struct. (we're further calling uint8 "nullptr", but that's irrelevant to the issue) That mixed-type array shouldn't be compressed, otherwise data is lost as the code currently makes the whole array have the type of the first element: css = {NULL, NULL, ..., 0x5555568a7940, NULL}; {"name": "s390_css", "instance_id": 0, "vmsd_name": "s390_css", "version": 1, "fields": [ ..., {"name": "css", "array_len": 256, "type": "nullptr", "size": 1}, ..., ]} In the above, the valid pointer at position 254 got lost among the compressed array of nullptr. While we could disable the array compression when a NULL pointer is found, the JSON part of the stream still makes part of downtime, so we should avoid writing unecessary bytes to it. Keep the array compression in place, but if NULL and non-NULL pointers are mixed break the array into several type-contiguous pieces : css = {NULL, NULL, ..., 0x5555568a7940, NULL}; {"name": "s390_css", "instance_id": 0, "vmsd_name": "s390_css", "version": 1, "fields": [ ..., {"name": "css", "array_len": 254, "type": "nullptr", "size": 1}, {"name": "css", "type": "struct", "struct": {"vmsd_name": "s390_css_img", ... }, "size": 768}, {"name": "css", "type": "nullptr", "size": 1}, ..., ]} Now each type-discontiguous region will become a new JSON entry. The reader should interpret this as a concatenation of values, all part of the same field. Parsing the JSON with analyze-script.py now shows the proper data being pointed to at the places where the pointer is valid and "nullptr" where there's NULL: "s390_css (14)": { ... "css": [ "nullptr", "nullptr", ... "nullptr", { "chpids": [ { "in_use": "0x00", "type": "0x00", "is_virtual": "0x00" }, ... ] }, "nullptr", } Reviewed-by: Peter Xu <peterx@redhat.com> Message-Id: <20250109185249.23952-7-farosas@suse.de> Signed-off-by: Fabiano Rosas <farosas@suse.de>