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* memory,vhost: Allow for marking memory device memory regions unmergeableDavid Hildenbrand2023-10-121-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Let's allow for marking memory regions unmergeable, to teach flatview code and vhost to not merge adjacent aliases to the same memory region into a larger memory section; instead, we want separate aliases to stay separate such that we can atomically map/unmap aliases without affecting other aliases. This is desired for virtio-mem mapping device memory located on a RAM memory region via multiple aliases into a memory region container, resulting in separate memslots that can get (un)mapped atomically. As an example with virtio-mem, the layout would look something like this: [...] 0000000240000000-00000020bfffffff (prio 0, i/o): device-memory 0000000240000000-000000043fffffff (prio 0, i/o): virtio-mem 0000000240000000-000000027fffffff (prio 0, ram): alias memslot-0 @mem2 0000000000000000-000000003fffffff 0000000280000000-00000002bfffffff (prio 0, ram): alias memslot-1 @mem2 0000000040000000-000000007fffffff 00000002c0000000-00000002ffffffff (prio 0, ram): alias memslot-2 @mem2 0000000080000000-00000000bfffffff [...] Without unmergable memory regions, all three memslots would get merged into a single memory section. For example, when mapping another alias (e.g., virtio-mem-memslot-3) or when unmapping any of the mapped aliases, memory listeners will first get notified about the removal of the big memory section to then get notified about re-adding of the new (differently merged) memory section(s). In an ideal world, memory listeners would be able to deal with that atomically, like KVM nowadays does. However, (a) supporting this for other memory listeners (vhost-user, vfio) is fairly hard: temporary removal can result in all kinds of issues on concurrent access to guest memory; and (b) this handling is undesired, because temporarily removing+readding can consume quite some time on bigger memslots and is not efficient (e.g., vfio unpinning and repinning pages ...). Let's allow for marking a memory region unmergeable, such that we can atomically (un)map aliases to the same memory region, similar to (un)mapping individual DIMMs. Similarly, teach vhost code to not redo what flatview core stopped doing: don't merge such sections. Merging in vhost code is really only relevant for handling random holes in boot memory where; without this merging, the vhost-user backend wouldn't be able to mmap() some boot memory backed on hugetlb. We'll use this for virtio-mem next. Message-ID: <20230926185738.277351-18-david@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com>
* memory: Clarify mapping requirements for RamDiscardManagerDavid Hildenbrand2023-10-121-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | We really only care about the RAM memory region not being mapped into an address space yet as long as we're still setting up the RamDiscardManager. Once mapped into an address space, memory notifiers would get notified about such a region and any attempts to modify the RamDiscardManager would be wrong. While "mapped into an address space" is easy to check for RAM regions that are mapped directly (following the ->container links), it's harder to check when such regions are mapped indirectly via aliases. For now, we can only detect that a region is mapped through an alias (->mapped_via_alias), but we don't have a handle on these aliases to follow all their ->container links to test if they are eventually mapped into an address space. So relax the assertion in memory_region_set_ram_discard_manager(), remove the check in memory_region_get_ram_discard_manager() and clarify the doc. Message-ID: <20230926185738.277351-14-david@redhat.com> Reviewed-by: Maciej S. Szmigiero <maciej.szmigiero@oracle.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com>
* softmmu/physmem: Fixup qemu_ram_block_from_host() documentationDavid Hildenbrand2023-10-121-0/+15
| | | | | | | | | | | | | | Let's fixup the documentation (e.g., removing traces of the ram_addr parameter that no longer exists) and move it to the header file while at it. Message-ID: <20230926185738.277351-4-david@redhat.com> Suggested-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com>
* plugins: Set final instruction count in plugin_gen_tb_endMatt Borgerson2023-10-111-2/+2
| | | | | | | | | | | | | | | Translation logic may partially decode an instruction, then abort and remove the instruction from the TB. This can happen for example when an instruction spans two pages. In this case, plugins may get an incorrect result when calling qemu_plugin_tb_n_insns to query for the number of instructions in the TB. This patch updates plugin_gen_tb_end to set the final instruction count. Signed-off-by: Matt Borgerson <contact@mborgerson.com> [AJB: added g_assert to defed API] Message-Id: <CADc=-s5RwGViNTR-h5cq3np673W3RRFfhr4vCGJp0EoDUxvhog@mail.gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20231009164104.369749-23-alex.bennee@linaro.org>
* accel/tcg: Add plugin_enabled to DisasContextBaseRichard Henderson2023-10-111-0/+2
| | | | | | | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230824181233.1568795-2-richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20231009164104.369749-21-alex.bennee@linaro.org>
* gdbstub: Remove gdb_has_xml variableAkihiko Odaki2023-10-111-8/+0
| | | | | | | | | | | GDB has XML support since 6.7 which was released in 2007. It's time to remove support for old GDB versions without XML support. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230912224107.29669-12-akihiko.odaki@daynix.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20231009164104.369749-19-alex.bennee@linaro.org>
* gdbstub: Introduce GDBFeature structureAkihiko Odaki2023-10-111-2/+7
| | | | | | | | | | | | | | Before this change, the information from a XML file was stored in an array that is not descriptive. Introduce a dedicated structure type to make it easier to understand and to extend with more fields. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230912224107.29669-6-akihiko.odaki@daynix.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20231009164104.369749-13-alex.bennee@linaro.org>
* Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu ↵Stefan Hajnoczi2023-10-051-3/+13
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging virtio,pci: features, cleanups vdpa: shadow vq vlan support net migration with cvq cxl: support emulating 4 HDM decoders serial number extended capability virtio: hared dma-buf Fixes, cleanups all over the place. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> * tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (53 commits) libvhost-user: handle shared_object msg vhost-user: add shared_object msg hw/display: introduce virtio-dmabuf util/uuid: add a hash function virtio: remove unused next argument from virtqueue_split_read_next_desc() virtio: remove unnecessary thread fence while reading next descriptor virtio: use shadow_avail_idx while checking number of heads libvhost-user.c: add assertion to vu_message_read_default pcie_sriov: unregister_vfs(): fix error path hw/i386/pc: improve physical address space bound check for 32-bit x86 systems amd_iommu: Fix APIC address check vdpa net: follow VirtIO initialization properly at cvq isolation probing vdpa net: stop probing if cannot set features vdpa net: fix error message setting virtio status hw/pci-bridge/cxl-upstream: Add serial number extended capability support hw/cxl: Support 4 HDM decoders at all levels of topology hw/cxl: Fix and use same calculation for HDM decoder block size everywhere hw/cxl: Add utility functions decoder interleave ways and target count. hw/cxl: Push cxl_decoder_count_enc() and cxl_decode_ig() into .c vdpa net: zero vhost_vdpa iova_tree pointer at cleanup ... Conflicts: hw/core/machine.c Context conflict with commit 314e0a84cd5d ("hw/core: remove needless includes") because it removed an adjacent #include.
| * virtio: don't zero out memory region cache for indirect descriptorsIlya Maximets2023-10-041-3/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Lots of virtio functions that are on a hot path in data transmission are initializing indirect descriptor cache at the point of stack allocation. It's a 112 byte structure that is getting zeroed out on each call adding unnecessary overhead. It's going to be correctly initialized later via special init function. The only reason to actually initialize right away is the ability to safely destruct it. Replacing a designated initializer with a function to only initialize what is necessary. Removal of the unnecessary stack initializations improves throughput of virtio-net devices in terms of 64B packets per second by 6-14 % depending on the case. Tested with a proposed af-xdp network backend and a dpdk testpmd application in the guest, but should be beneficial for other virtio devices as well. Signed-off-by: Ilya Maximets <i.maximets@ovn.org> Message-Id: <20230811143423.3258788-1-i.maximets@ovn.org> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Acked-by: Jason Wang <jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* | accel/tcg: Restrict dump_exec_info() declarationPhilippe Mathieu-Daudé2023-10-041-5/+0
| | | | | | | | | | | | | | | | | | | | | | In commit 00c9a5c2c3 ("accel/tcg: Restrict 'qapi-commands-machine.h' to system emulation") we moved the definition to accel/tcg/ which is where this function is called. No need to expose it outside. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230914185718.76241-4-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | exec: Move cpu_loop_foo() target agnostic functions to 'cpu-common.h'Philippe Mathieu-Daudé2023-10-042-30/+32
| | | | | | | | | | | | | | | | | | | | | | While these functions are not TCG specific, they are not target specific. Move them to "exec/cpu-common.h" so their callers don't have to be tainted as target specific. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230914185718.76241-3-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | exec: Make EXCP_FOO definitions target agnosticPhilippe Mathieu-Daudé2023-10-042-7/+7
| | | | | | | | | | | | | | | | | | | | The EXCP_* definitions don't need to be target specific, move them to "exec/cpu-common.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230914185718.76241-2-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | accel/tcg: Remove env_tlb()Anton Johansson2023-10-041-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | The function is no longer used to access the TLB, and has been replaced by cpu->neg.tlb. Signed-off-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230912153428.17816-9-anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> [rth: Merge comment update patch] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | accel/tcg: Modify tlb_*() to use CPUStateAnton Johansson2023-10-041-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | Changes tlb_*() functions to take CPUState instead of CPUArchState, as they don't require the full CPUArchState. This makes it easier to decouple target-(in)dependent code. Signed-off-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230912153428.17816-4-anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> [rth: Use cpu->neg.tlb instead of cpu_tlb()] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | accel/tcg: Remove env_neg()Richard Henderson2023-10-041-12/+1
| | | | | | | | | | | | | | | | Replace the single use within env_tlb() and remove. Reviewed-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | accel/tcg: Remove cpu_set_cpustate_pointersRichard Henderson2023-10-041-10/+0
| | | | | | | | | | | | | | | | | | This function is now empty, so remove it. In the case of m68k and tricore, this empties the class instance initfn, so remove those as well. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | accel/tcg: Replace CPUState.env_ptr with cpu_env()Richard Henderson2023-10-041-1/+0
| | | | | | | | | | Reviewed-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | accel/tcg: Remove cpu_neg()Richard Henderson2023-10-032-12/+1
| | | | | | | | | | | | | | | | Now that CPUNegativeOffsetState is part of CPUState, we can reference it directly. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | accel/tcg: Remove CPUState.icount_decr_ptrRichard Henderson2023-10-031-1/+0
| | | | | | | | | | | | | | We can now access icount_decr directly. Reviewed-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | accel/tcg: Move CPUNegativeOffsetState into CPUStateRichard Henderson2023-10-031-13/+9
| | | | | | | | | | | | | | | | Retain the separate structure to emphasize its importance. Enforce CPUArchState always follows CPUState without padding. Reviewed-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | accel/tcg: Validate placement of CPUNegativeOffsetStateRichard Henderson2023-10-031-0/+6
| | | | | | | | | | | | | | | | Verify that the distance between CPUNegativeOffsetState and CPUArchState is no greater than any alignment requirements. Reviewed-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | accel/tcg: Move CPUTLB definitions from cpu-defs.hRichard Henderson2023-10-031-150/+0
| | | | | | | | | | | | | | | | Accept that we will consume space in CPUState for CONFIG_USER_ONLY, since we cannot test CONFIG_SOFTMMU within hw/core/cpu.h. Reviewed-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | target/arm: Replace TARGET_PAGE_ENTRY_EXTRAAnton Johansson2023-10-031-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TARGET_PAGE_ENTRY_EXTRA is a macro that allows guests to specify additional fields for caching with the full TLB entry. This macro is replaced with a union in CPUTLBEntryFull, thus making CPUTLB target-agnostic at the cost of slightly inflated CPUTLBEntryFull for non-arm guests. Note, this is needed to ensure that fields in CPUTLB don't vary in offset between various targets. (arm is the only guest actually making use of this feature.) Signed-off-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230912153428.17816-2-anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | accel/tcg: Restrict tcg_exec_[un]realizefn() to TCGPhilippe Mathieu-Daudé2023-10-031-2/+0
| | | | | | | | | | | | | | | | | | | | | | We don't need to expose these TCG-specific methods to the whole code base. Register them as AccelClass handlers, they will be called by the generic accel_cpu_[un]realize() methods. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Claudio Fontana <cfontana@suse.de> Message-Id: <20231003123026.99229-8-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | accel/tcg: Have tcg_exec_realizefn() return a booleanPhilippe Mathieu-Daudé2023-10-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | Following the example documented since commit e3fe3988d7 ("error: Document Error API usage rules"), have tcg_exec_realizefn() return a boolean indicating whether an error is set or not. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Claudio Fontana <cfontana@suse.de> Message-Id: <20231003123026.99229-7-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | accel/tcg: Track current value of can_do_io in the TBRichard Henderson2023-09-281-0/+2
|/ | | | | | | | Simplify translator_io_start by recording the current known value of can_do_io within DisasContextBase. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* Merge tag 'mem-2023-09-19' of https://github.com/davidhildenbrand/qemu into ↵Stefan Hajnoczi2023-09-192-8/+15
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging Hi, "Host Memory Backends" and "Memory devices" queue ("mem"): - Support and document VM templating with R/O files using a new "rom" parameter for memory-backend-file - Some cleanups and fixes around NVDIMMs and R/O file handling for guest RAM - Optimize ioeventfd updates by skipping address spaces that are not applicable # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEG9nKrXNcTDpGDfzKTd4Q9wD/g1oFAmUJdykRHGRhdmlkQHJl # ZGhhdC5jb20ACgkQTd4Q9wD/g1pf2w//akOUoYMuamySGjXtKLVyMKZkjIys+Ama # k2C0xzsWAHBP572ezwHi8uxf5j9kzAjsw6GxDZ7FAamD9MhiohkEvkecloBx6f/c # q3fVHblBNkG7v2urtf4+6PJtJvhzOST2SFXfWeYhO/vaA04AYCDgexv82JN3gA6B # OS8WyOX62b8wILPSY2GLZ8IqpE9XnOYZwzVBn6YB1yo7ZkYEfXO6cA8nykNuNcOE # vppqDo7uVIX6317FWj8ygxmzFfOaj0WT2MT2XFzEIDfg8BInQN8HC4mTn0hcVKMa # N1y+eZH733CQKT+uNBRZ5YOeljOi4d6gEEyvkkA/L7e5D3Qg9hIdvHb4uryCFSWX # Vt07OP1XLBwCZFobOC6sg+2gtTZJxxYK89e6ZzEd0454S24w5bnEteRAaCGOP0XL # ww9xYULqhtZs55UC4rvZHJwdUAk1fIY4VqynwkeQXegvz6BxedNeEkJiiEU0Tizx # N2VpsxAJ7H/LLSFeZoCRESo4azrH6U4n7S/eS1tkCniFqibfe2yIQCDoJVfb42ec # gfg/vThCrDwHkIHzkMmoV8NndA7Q7SIkyMfYeEEBeZMeg8JzYll4DJEw/jQCacxh # KRUa+AZvGlTJUq0mkvyOVfLki+iaehoIUuY1yvMrmdWijPO8n3YybmP9Ljhr8VdR # 9MSYZe+I2v8= # =iraT # -----END PGP SIGNATURE----- # gpg: Signature made Tue 19 Sep 2023 06:25:45 EDT # gpg: using RSA key 1BD9CAAD735C4C3A460DFCCA4DDE10F700FF835A # gpg: issuer "david@redhat.com" # gpg: Good signature from "David Hildenbrand <david@redhat.com>" [unknown] # gpg: aka "David Hildenbrand <davidhildenbrand@gmail.com>" [full] # gpg: aka "David Hildenbrand <hildenbr@in.tum.de>" [unknown] # gpg: WARNING: The key's User ID is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 1BD9 CAAD 735C 4C3A 460D FCCA 4DDE 10F7 00FF 835A * tag 'mem-2023-09-19' of https://github.com/davidhildenbrand/qemu: memory: avoid updating ioeventfds for some address_space machine: Improve error message when using default RAM backend id softmmu/physmem: Hint that "readonly=on,rom=off" exists when opening file R/W for private mapping fails docs: Start documenting VM templating docs: Don't mention "-mem-path" in multi-process.rst softmmu/physmem: Never return directories from file_ram_open() softmmu/physmem: Fail creation of new files in file_ram_open() with readonly=true softmmu/physmem: Bail out early in ram_block_discard_range() with readonly files softmmu/physmem: Remap with proper protection in qemu_ram_remap() backends/hostmem-file: Add "rom" property to support VM templating with R/O files softmmu/physmem: Distinguish between file access mode and mmap protection nvdimm: Reject writing label data to ROM instead of crashing QEMU Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * memory: avoid updating ioeventfds for some address_spacehongmianquan2023-09-191-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When updating ioeventfds, we need to iterate all address spaces, but some address spaces do not register eventfd_add|del call when memory_listener_register() and they do nothing when updating ioeventfds. So we can skip these AS in address_space_update_ioeventfds(). The overhead of memory_region_transaction_commit() can be significantly reduced. For example, a VM with 8 vhost net devices and each one has 64 vectors, can reduce the time spent on memory_region_transaction_commit by 20%. Message-ID: <20230830032906.12488-1-hongmianquan@bytedance.com> Reviewed-by: Peter Xu <peterx@redhat.com> Signed-off-by: hongmianquan <hongmianquan@bytedance.com> Signed-off-by: David Hildenbrand <david@redhat.com>
| * softmmu/physmem: Distinguish between file access mode and mmap protectionDavid Hildenbrand2023-09-192-8/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a difference between how we open a file and how we mmap it, and we want to support writable private mappings of readonly files. Let's define RAM_READONLY and RAM_READONLY_FD flags, to replace the single "readonly" parameter for file-related functions. In memory_region_init_ram_from_fd() and memory_region_init_ram_from_file(), initialize mr->readonly based on the new RAM_READONLY flag. While at it, add some RAM_* flags we missed to add to the list of accepted flags in the documentation of some functions. No change in functionality intended. We'll make use of both flags next and start setting them independently for memory-backend-file. Message-ID: <20230906120503.359863-3-david@redhat.com> Acked-by: Peter Xu <peterx@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com>
* | thunk: Delete checks for old host definitionsAkihiko Odaki2023-09-151-2/+1
| | | | | | | | | | | | | | | | | | Alpha, IA-64, and PA-RISC hosts are no longer supported. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20230808152314.102036-1-akihiko.odaki@daynix.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | accel/tcg: Fix the comment for CPUTLBEntryFullLIU Zhiwei2023-09-151-6/+6
|/ | | | | | | | | | | | When memory region is ram, the lower TARGET_PAGE_BITS is not the physical section number. Instead, its value is always 0. Add comment and assert to make it clear. Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-Id: <20230901060118.379-1-zhiwei_liu@linux.alibaba.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Fix typo in translator_io_start() descriptionPhilippe Mathieu-Daudé2023-09-081-1/+1
| | | | | | | | | Missed while reviewing commit dfd1b81274 ("accel/tcg: Introduce translator_io_start"). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* exec/translation-block: Clean up includesPhilippe Mathieu-Daudé2023-08-311-3/+3
| | | | | | | | | 'qemu/atomic.h' and 'exec/target_page.h' are not used. 'qemu/interval-tree.h' is only required for user emulation. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230828221314.18435-12-philmd@linaro.org>
* target/translate: Restrict 'exec/cpu_ldst.h' to user emulationPhilippe Mathieu-Daudé2023-08-311-1/+1
| | | | | | | | | | Only handle_sigsegv_accerr_write(), declared with user emulation, requires "exec/cpu_ldst.h" (for the abi_ptr typedef). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230828221314.18435-6-philmd@linaro.org>
* exec/address-spaces.h: Remove unuseful 'exec/memory.h' includePhilippe Mathieu-Daudé2023-08-311-2/+0
| | | | | | | | | | | | "exec/address-spaces.h" declares get_system_io() and get_system_memory(), both returning a MemoryRegion pointer. MemoryRegion is forward declared in "qemu/typedefs.h", so we don't need any declaration from "exec/memory.h" here. Remove it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230619074153.44268-4-philmd@linaro.org>
* bulk: Do not declare function prototypes using 'extern' keywordPhilippe Mathieu-Daudé2023-08-312-23/+23
| | | | | | | | | | | | | | | | By default, C function prototypes declared in headers are visible, so there is no need to declare them as 'extern' functions. Remove this redundancy in a single bulk commit; do not modify: - meson.build (used to check function availability at runtime) - pc-bios/ - libdecnumber/ - tests/ - *.c Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20230605175647.88395-5-philmd@linaro.org>
* accel: Remove HAX acceleratorPhilippe Mathieu-Daudé2023-08-311-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | HAX is deprecated since commits 73741fda6c ("MAINTAINERS: Abort HAXM maintenance") and 90c167a1da ("docs/about/deprecated: Mark HAXM in QEMU as deprecated"), released in v8.0.0. Per the latest HAXM release (v7.8 [*]), the latest QEMU supported is v7.2: Note: Up to this release, HAXM supports QEMU from 2.9.0 to 7.2.0. The next commit (https://github.com/intel/haxm/commit/da1b8ec072) added: HAXM v7.8.0 is our last release and we will not accept pull requests or respond to issues after this. It became very hard to build and test HAXM. Its previous maintainers made it clear they won't help. It doesn't seem to be a very good use of QEMU maintainers to spend their time in a dead project. Save our time by removing this orphan zombie code. [*] https://github.com/intel/haxm/releases/tag/v7.8.0 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20230831082016.60885-1-philmd@linaro.org>
* Merge tag 'pull-maintainer-ominbus-300823-1' of ↵Stefan Hajnoczi2023-08-311-5/+15
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.com/stsquad/qemu into staging testing and gdbstub updates: - enable ccache for gitlab builds - fix various test info leakages for non V=1 - update style to allow loop vars - bump FreeBSD to v13.2 - clean-up gdbstub tests - various gdbstub doc and refactorings # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEEZoWumedRZ7yvyN81+9DbCVqeKkQFAmTvS2AACgkQ+9DbCVqe # KkRiRwgAhsinp2/KgnvkD0n6deQy/JWg9MfYIvvZacKEakIfQvCDoJ752AUZzUTw # ggQ+W2KuaoHTzwG+AOMLdzulkmspQ8xeFuD2aIpFjRMnZrO9jN2T4L0vcGLAd95c # 9QLqPeH8xRdhuK28+ILuYzKOKBcefQ44ufMLpxrS2iNITEsSg/Tw3MU91hbct49g # 3OR4bD1ueG5Ib/lXp8V/4GnRmfLdnp3k0i/6OHriq7Mpz4Lia67WblVsPEple66U # n7JCo2sI5/m+6p2tvKs7rH60xc8s1Za3kbK4ggEq3LVRfzVOordZqO+1ep6wklTY # 6nP9Ry9nZG3gqCmcNXfhoofm0vHaZA== # =Km9m # -----END PGP SIGNATURE----- # gpg: Signature made Wed 30 Aug 2023 10:00:00 EDT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * tag 'pull-maintainer-ominbus-300823-1' of https://gitlab.com/stsquad/qemu: gdbstub: move comment for gdb_register_coprocessor gdbstub: replace global gdb_has_xml with a function gdbstub: refactor get_feature_xml gdbstub: remove unused user_ctx field gdbstub: fixes cases where wrong threads were reported to GDB on SIGINT tests/tcg: clean-up gdb confirm/pagination settings tests: remove test-gdbstub.py .gitlab-ci.d/cirrus.yml: Update FreeBSD to v13.2 docs/style: permit inline loop variables tests/tcg: remove quoting for info output tests/docker: cleanup non-verbose output gitlab: enable ccache for many build jobs Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * gdbstub: move comment for gdb_register_coprocessorAlex Bennée2023-08-301-0/+10
| | | | | | | | | | | | | | | | | | Use proper kdoc style comments for this API function. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20230829161528.2707696-13-alex.bennee@linaro.org>
| * gdbstub: replace global gdb_has_xml with a functionAlex Bennée2023-08-301-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | Try and make the self reported global hack a little less hackish by providing a query function instead. As gdb_has_xml was always set if we negotiated XML we can now use the presence of ->target_xml as the test instead. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20230829161528.2707696-12-alex.bennee@linaro.org>
* | Revert "include/exec: typedef abi_ptr to vaddr in softmmu"Richard Henderson2023-08-291-2/+2
| | | | | | | | | | | | | | | | | | | | This reverts commit fc15bfb6a6bda8d4d01f1383579d385acae17c0f. This patch caused a regression for tricore-softmmu, ./tests/tcg/tricore-softmmu/test_boot_to_main.c.tst. Reported-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | softmmu: Use async_run_on_cpu in tcg_commitRichard Henderson2023-08-291-1/+0
|/ | | | | | | | | | | | | | | | | After system startup, run the update to memory_dispatch and the tlb_flush on the cpu. This eliminates a race, wherein a running cpu sees the memory_dispatch change but has not yet seen the tlb_flush. Since the update now happens on the cpu, we need not use qatomic_rcu_read to protect the read of memory_dispatch. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1826 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1834 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1846 Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* include/exec: Widen tlb_hit/tlb_hit_page()Anton Johansson2023-08-241-2/+2
| | | | | | | | | | tlb_addr is changed from target_ulong to uint64_t to match the type of a CPUTLBEntry value, and the addressed is changed to vaddr. Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230807155706.9580-8-anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* include/exec: typedef abi_ptr to vaddr in softmmuAnton Johansson2023-08-241-2/+2
| | | | | | | | | | | | In system mode, abi_ptr is primarily used for representing addresses when accessing guest memory with cpu_[st|ld]*(). Widening it from target_ulong to vaddr reduces the target dependence of these functions and is step towards building accel/ once for system mode. Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230807155706.9580-7-anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* include/exec: Replace target_ulong with abi_ptr in cpu_[st|ld]*()Anton Johansson2023-08-241-12/+12
| | | | | | | | | | | | | | | Changes the address type of the guest memory read/write functions from target_ulong to abi_ptr. (abi_ptr is currently typedef'd to target_ulong but that will change in a following commit.) This will reduce the coupling between accel/ and target/. Note: Function pointers that point to cpu_[st|ld]*() in target/riscv and target/rx are also updated in this commit. Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230807155706.9580-6-anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* linux-user: Use ARRAY_SIZE with bitmask_transtblRichard Henderson2023-08-091-4/+11
| | | | | | | | | | | | | | | | | | | Rather than using a zero tuple to end the table, use a macro to apply ARRAY_SIZE and pass that on to the convert functions. This fixes two bugs in which the conversion functions required that both the target and host masks be non-zero in order to continue, rather than require both target and host masks be zero in order to terminate. This affected mmap_flags_tbl when the host does not support all of the flags we wish to convert (e.g. MAP_UNINITIALIZED). Mapping these flags to zero is good enough, and matches how the kernel ignores bits that are unknown. Fixes: 4b840f96 ("linux-user: Populate more bits in mmap_flags_tbl") Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* Fixed incorrect LLONG alignment for openrisc and crisLuca Bonissi2023-08-071-0/+8
| | | | | | | | | | | | | | OpenRISC (or1k) has long long alignment to 4 bytes, but currently not defined in abitypes.h. This lead to incorrect packing of /epoll_event/ structure and eventually infinite loop while waiting for file descriptor[s] event[s]. Fixed also CRIS alignments (1 byte for all types). Signed-off-by: Luca Bonissi <qemu@bonslack.org> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1770 Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* misc: Fix some typos in documentation and commentsStefan Weil2023-08-011-1/+1
| | | | | | | | Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230730180329.851576-1-sw@weilnetz.de> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
* include/exec: Add WITH_MMAP_LOCK_GUARDRichard Henderson2023-07-231-0/+10
| | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Use HAVE_CMPXCHG128 instead of CONFIG_CMPXCHG128Richard Henderson2023-07-151-0/+2
| | | | | | | | | | | | | | | | | | We adjust CONFIG_ATOMIC128 and CONFIG_CMPXCHG128 with CONFIG_ATOMIC128_OPT in atomic128.h. It is difficult to tell when those changes have been applied with the ifdef we must use with CONFIG_CMPXCHG128. So instead use HAVE_CMPXCHG128, which triggers -Werror-undef when the proper header has not been included. Improves tcg_gen_atomic_cmpxchg_i128 for s390x host, which requires CONFIG_ATOMIC128_OPT. Without this we fall back to EXCP_ATOMIC to single-step 128-bit atomics, which is slow enough to cause some tests to time out. Reported-by: Thomas Huth <thuth@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>