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* hw/arm: Set number of MPU regions correctly for an505, an521, an524Peter Maydell2023-08-311-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The IoTKit, SSE200 and SSE300 all default to 8 MPU regions. The MPS2/MPS3 FPGA images don't override these except in the case of AN547, which uses 16 MPU regions. Define properties on the ARMSSE object for the MPU regions (using the same names as the documented RTL configuration settings, and following the pattern we already have for this device of using all-caps names as the RTL does), and set them in the board code. We don't actually need to override the default except on AN547, but it's simpler code to have the board code set them always rather than tracking which board subtypes want to set them to a non-default value separately from what that value is. Tho overall effect is that for mps2-an505, mps2-an521 and mps3-an524 we now correctly use 8 MPU regions, while mps3-an547 stays at its current 16 regions. It's possible some guest code wrongly depended on the previous incorrectly modeled number of memory regions. (Such guest code should ideally check the number of regions via the MPU_TYPE register.) The old behaviour can be obtained with additional -global arguments to QEMU: For mps2-an521 and mps2-an524: -global sse-200.CPU0_MPU_NS=16 -global sse-200.CPU0_MPU_S=16 -global sse-200.CPU1_MPU_NS=16 -global sse-200.CPU1_MPU_S=16 For mps2-an505: -global sse-200.CPU0_MPU_NS=16 -global sse-200.CPU0_MPU_S=16 NB that the way the implementation allows this use of -global is slightly fragile: if the board code explicitly sets the properties on the sse-200 object, this overrides the -global command line option. So we rely on: - the boards that need fixing all happen to use the SSE defaults - we can write the board code to only set the property if it is different from the default, rather than having all boards explicitly set the property - the board that does need to use a non-default value happens to need to set it to the same value (16) we previously used This works, but there are some kinds of refactoring of the mps2-tz.c code that would break the support for -global here. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1772 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20230724174335.2150499-4-peter.maydell@linaro.org
* hw/arm/armv7m: Add mpu-ns-regions and mpu-s-regions propertiesPeter Maydell2023-08-311-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | M-profile CPUs generally allow configuration of the number of MPU regions that they have. We don't currently model this, so our implementations of some of the board models provide CPUs with the wrong number of regions. RTOSes like Zephyr that hardcode the expected number of regions may therefore not run on the model if they are set up to run on real hardware. Add properties mpu-ns-regions and mpu-s-regions to the ARMV7M object, matching the ability of hardware to configure the number of Secure and NonSecure regions separately. Our actual CPU implementation doesn't currently support that, and it happens that none of the MPS boards we model set the number of regions differently for Secure vs NonSecure, so we provide an interface to the boards and SoCs that won't need to change if we ever do add that functionality in future, but make it an error to configure the two properties to different values. (The property name on the CPU is the somewhat misnamed-for-M-profile "pmsav7-dregion", so we don't follow that naming convention for the properties here. The TRM doesn't say what the CPU configuration variable names are, so we pick something, and follow the lowercase convention we already have for properties here.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20230724174335.2150499-3-peter.maydell@linaro.org
* Add i.MX7 SRC device implementationJean-Christophe Dubois2023-08-311-1/+2
| | | | | | | | | | | | | | | | | | | | | The SRC device is normally used to start the secondary CPU. When running Linux directly, QEMU is emulating a PSCI interface that UBOOT is installing at boot time and therefore the fact that the SRC device is unimplemented is hidden as Qemu respond directly to PSCI requets without using the SRC device. But if you try to run a more bare metal application (maybe uboot itself), then it is not possible to start the secondary CPU as the SRC is an unimplemented device. This patch adds the ability to start the secondary CPU through the SRC device so that you can use this feature in bare metal applications. Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: ce9a0162defd2acee5dc7f8a674743de0cded569.1692964892.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Add i.MX7 missing TZ devices and memory regionsJean-Christophe Dubois2023-08-311-0/+7
| | | | | | | | | | | | | | | | | | | * Add TZASC as unimplemented device. - Allow bare metal application to access this (unimplemented) device * Add CSU as unimplemented device. - Allow bare metal application to access this (unimplemented) device * Add various memory segments - OCRAM - OCRAM EPDC - OCRAM PXP - OCRAM S - ROM - CAAM Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: f887a3483996ba06d40bd62ffdfb0ecf68621987.1692964892.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Refactor i.MX7 processor codeJean-Christophe Dubois2023-08-311-84/+242
| | | | | | | | | | | | | | | * Add Addr and size definition for all i.MX7 devices in i.MX7 header file. * Use those newly defined named constants whenever possible. * Standardize the way we init a familly of unimplemented devices - SAI - PWM - CAN * Add/rework few comments Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Message-id: 59e195d33e4d486a8d131392acd46633c8c10ed7.1692964892.git.jcd@tribudubois.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Add i.MX6UL missing devices.Jean-Christophe Dubois2023-08-311-1/+1
| | | | | | | | | | | | | * Add TZASC as unimplemented device. - Allow bare metal application to access this (unimplemented) device * Add CSU as unimplemented device. - Allow bare metal application to access this (unimplemented) device * Add 4 missing PWM devices Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 59e4dc56e14eccfefd379275ec19048dff9c10b3.1692964892.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Refactor i.MX6UL processor codeJean-Christophe Dubois2023-08-311-11/+123
| | | | | | | | | | | | | | | * Add Addr and size definition for most i.MX6UL devices in i.MX6UL header file. * Use those newly defined named constants whenever possible. * Standardize the way we init a familly of unimplemented devices - SAI - PWM - CAN * Add/rework few comments Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Message-id: d579043fbd4e4b490370783fda43fc02c8e9be75.1692964892.git.jcd@tribudubois.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Remove i.MX7 IOMUX GPR device from i.MX6ULJean-Christophe Dubois2023-08-311-2/+0
| | | | | | | | | | | | | | | i.MX7 IOMUX GPR device is not equivalent to i.MX6UL IOMUXC GPR device. In particular, register 22 is not present on i.MX6UL and this is actualy The only register that is really emulated in the i.MX7 IOMUX GPR device. Note: The i.MX6UL code is actually also implementing the IOMUX GPR device as an unimplemented device at the same bus adress and the 2 instantiations were actualy colliding. So we go back to the unimplemented device for now. Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Message-id: 48681bf51ee97646479bb261bee19abebbc8074e.1692964892.git.jcd@tribudubois.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* arm: spelling fixesMichael Tokarev2023-07-251-1/+1
| | | | | Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
* hw/misc/bcm2835_property: Handle CORE_CLK_ID firmware propertySergey Kambalin2023-06-191-0/+5
| | | | | | | | | | | | | Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20230612223456.33824-5-philmd@linaro.org Message-Id: <20230531155258.8361-1-sergey.kambalin@auriga.com> [PMD: Split from bigger patch: 3/4] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> [PMM: added a comment about RPI_FIRMWARE_CORE_CLK_RATE really being SoC-specific] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/misc/bcm2835_property: Replace magic frequency values by definitionsSergey Kambalin2023-06-191-0/+5
| | | | | | | | | | | Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230612223456.33824-4-philmd@linaro.org Message-Id: <20230531155258.8361-1-sergey.kambalin@auriga.com> [PMD: Split from bigger patch: 4/4] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm: introduce xenpvh machineVikram Garhwal2023-06-151-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | Add a new machine xenpvh which creates a IOREQ server to register/connect with Xen Hypervisor. Optional: When CONFIG_TPM is enabled, it also creates a tpm-tis-device, adds a TPM emulator and connects to swtpm running on host machine via chardev socket and support TPM functionalities for a guest domain. Extra command line for aarch64 xenpvh QEMU to connect to swtpm: -chardev socket,id=chrtpm,path=/tmp/myvtpm2/swtpm-sock \ -tpmdev emulator,id=tpm0,chardev=chrtpm \ -machine tpm-base-addr=0x0c000000 \ swtpm implements a TPM software emulator(TPM 1.2 & TPM 2) built on libtpms and provides access to TPM functionality over socket, chardev and CUSE interface. Github repo: https://github.com/stefanberger/swtpm Example for starting swtpm on host machine: mkdir /tmp/vtpm2 swtpm socket --tpmstate dir=/tmp/vtpm2 \ --ctrl type=unixio,path=/tmp/vtpm2/swtpm-sock & Signed-off-by: Vikram Garhwal <vikram.garhwal@amd.com> Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
* hw: arm: allwinner-sramc: Add SRAM Controller support for R40qianfan Zhao2023-06-061-0/+3
| | | | | | | | | Only a few important registers are added, especially the SRAM_VER register. Signed-off-by: qianfan Zhao <qianfanguijin@163.com> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw: arm: allwinner-r40: Add emac and gmac supportqianfan Zhao2023-06-061-0/+6
| | | | | | | | R40 has two ethernet controllers named as emac and gmac. The emac is compatibled with A10, and the GMAC is compatibled with H3. Signed-off-by: qianfan Zhao <qianfanguijin@163.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/allwinner-r40: add SDRAM controller deviceqianfan Zhao2023-06-061-1/+12
| | | | | | | | | | | Types of memory that the SDRAM controller supports are DDR2/DDR3 and capacities of up to 2GiB. This commit adds emulation support of the Allwinner R40 SDRAM controller. This driver only support 256M, 512M and 1024M memory now. Signed-off-by: qianfan Zhao <qianfanguijin@163.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw: arm: allwinner-r40: Add i2c0 deviceqianfan Zhao2023-06-061-0/+3
| | | | | | | | | | | TWI(i2c) is designed to be used as an interface between CPU host and the serial 2-Wire bus. It can support all standard 2-Wire transfer, can be operated in standard mode(100kbit/s) or fast-mode, supporting data rate up to 400kbit/s. Signed-off-by: qianfan Zhao <qianfanguijin@163.com> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw: allwinner-r40: Complete uart devicesqianfan Zhao2023-06-061-0/+8
| | | | | | | R40 has eight UARTs, support both 16450 and 16550 compatible modes. Signed-off-by: qianfan Zhao <qianfanguijin@163.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/allwinner-r40: add Clock Control Unitqianfan Zhao2023-06-061-0/+2
| | | | | | | | | | | | | The CCU provides the registers to program the PLLs and the controls most of the clock generation, division, distribution, synchronization and gating. This commit adds support for the Clock Control Unit which emulates a simple read/write register interface. Signed-off-by: qianfan Zhao <qianfanguijin@163.com> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw: arm: Add bananapi M2-Ultra and allwinner-r40 supportqianfan Zhao2023-06-061-0/+110
| | | | | | | | | | | Allwinner R40 (sun8i) SoC features a Quad-Core Cortex-A7 ARM CPU, and a Mali400 MP2 GPU from ARM. It's also known as the Allwinner T3 for In-Car Entertainment usage, A40i and A40pro are variants that differ in applicable temperatures range (industrial and military). Signed-off-by: qianfan Zhao <qianfanguijin@163.com> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* xlnx-versal: Connect Xilinx VERSAL CANFD controllersVikram Garhwal2023-06-061-0/+12
| | | | | | | | | | Connect CANFD0 and CANFD1 on the Versal-virt machine and update xlnx-versal-virt document with CANFD command line examples. Signed-off-by: Vikram Garhwal <vikram.garhwal@amd.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/omap: Remove unused omap_uart_attach()Bernhard Beschow2023-06-051-1/+0
| | | | | | | | | | | | | The function is unused since commit bdad3654d3c55f478e538037d9eccd204e5fc8ee ('hw/arm/nseries: Remove invalid/unnecessary n8x0_uart_setup()'). Signed-off-by: Bernhard Beschow <shentey@gmail.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230523195608.125820-3-shentey@gmail.com> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
* hw/arm/smmuv3: Add knob to choose translation stage and enable stage-2Mostafa Saleh2023-05-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | As everything is in place, we can use a new system property to advertise which stage is supported and remove bad_ste from STE stage2 config. The property added arm-smmuv3.stage can have 3 values: - "1": Stage-1 only is advertised. - "2": Stage-2 only is advertised. If not passed or an unsupported value is passed, it will default to stage-1. Advertise VMID16. Don't try to decode CD, if stage-2 is configured. Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Mostafa Saleh <smostafa@google.com> Tested-by: Eric Auger <eric.auger@redhat.com> Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Message-id: 20230516203327.2051088-11-smostafa@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/smmuv3: Add CMDs related to stage-2Mostafa Saleh2023-05-301-0/+1
| | | | | | | | | | | | | | | | | CMD_TLBI_S2_IPA: As S1+S2 is not enabled, for now this can be the same as CMD_TLBI_NH_VAA. CMD_TLBI_S12_VMALL: Added new function to invalidate TLB by VMID. For stage-1 only commands, add a check to throw CERROR_ILL if used when stage-1 is not supported. Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Mostafa Saleh <smostafa@google.com> Tested-by: Eric Auger <eric.auger@redhat.com> Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Message-id: 20230516203327.2051088-9-smostafa@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/smmuv3: Add VMID to TLB taggingMostafa Saleh2023-05-301-2/+3
| | | | | | | | | | | | | | | | Allow TLB to be tagged with VMID. If stage-1 is only supported, VMID is set to -1 and ignored from STE and CMD_TLBI_NH* cmds. Update smmu_iotlb_insert trace event to have vmid. Signed-off-by: Mostafa Saleh <smostafa@google.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Message-id: 20230516203327.2051088-8-smostafa@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/smmuv3: Parse STE config for stage-2Mostafa Saleh2023-05-302-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Parse stage-2 configuration from STE and populate it in SMMUS2Cfg. Validity of field values are checked when possible. Only AA64 tables are supported and Small Translation Tables (STT) are not supported. According to SMMUv3 UM(IHI0070E) "5.2 Stream Table Entry": All fields with an S2 prefix (with the exception of S2VMID) are IGNORED when stage-2 bypasses translation (Config[1] == 0). Which means that VMID can be used(for TLB tagging) even if stage-2 is bypassed, so we parse it unconditionally when S2P exists. Otherwise it is set to -1.(only S1P) As stall is not supported, if S2S is set the translation would abort. For S2R, we reuse the same code used for stage-1 with flag record_faults. However when nested translation is supported we would need to separate stage-1 and stage-2 faults. Fix wrong shift in STE_S2HD, STE_S2HA, STE_S2S. Signed-off-by: Mostafa Saleh <smostafa@google.com> Tested-by: Eric Auger <eric.auger@redhat.com> Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20230516203327.2051088-6-smostafa@google.com [PMM: fixed format string] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/smmuv3: Refactor stage-1 PTWMostafa Saleh2023-05-301-3/+13
| | | | | | | | | | | | | | | | | | | | | | In preparation for adding stage-2 support, rename smmu_ptw_64 to smmu_ptw_64_s1 and refactor some of the code so it can be reused in stage-2 page table walk. Remove AA64 check from PTW as decode_cd already ensures that AA64 is used, otherwise it faults with C_BAD_CD. A stage member is added to SMMUPTWEventInfo to differentiate between stage-1 and stage-2 ptw faults. Add stage argument to trace_smmu_ptw_level be consistent with other trace events. Signed-off-by: Mostafa Saleh <smostafa@google.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Message-id: 20230516203327.2051088-4-smostafa@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/smmuv3: Update translation config to hold stage-2Mostafa Saleh2023-05-301-3/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation for adding stage-2 support, add a S2 config struct(SMMUS2Cfg), composed of the following fields and embedded in the main SMMUTransCfg: -tsz: Size of IPA input region (S2T0SZ) -sl0: Start level of translation (S2SL0) -affd: AF Fault Disable (S2AFFD) -record_faults: Record fault events (S2R) -granule_sz: Granule page shift (based on S2TG) -vmid: Virtual Machine ID (S2VMID) -vttb: Address of translation table base (S2TTB) -eff_ps: Effective PA output range (based on S2PS) They will be used in the next patches in stage-2 address translation. The fields in SMMUS2Cfg, are reordered to make the shared and stage-1 fields next to each other, this reordering didn't change the struct size (104 bytes before and after). Stage-1 only fields: aa64, asid, tt, ttb, tbi, record_faults, oas. oas is stage-1 output address size. However, it is used to check input address in case stage-1 is unimplemented or bypassed according to SMMUv3 manual IHI0070.E "3.4. Address sizes" Shared fields: stage, disabled, bypassed, aborted, iotlb_*. No functional change intended. Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Mostafa Saleh <smostafa@google.com> Tested-by: Eric Auger <eric.auger@redhat.com> Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Message-id: 20230516203327.2051088-3-smostafa@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* fsl-imx6: Add SNVS support for i.MX6 boardsVitaly Cheptsov2023-05-301-0/+2
| | | | | | | | | | | | | | SNVS is supported on both i.MX6 and i.MX6UL and is needed to support shutdown on the board. Cc: Peter Maydell <peter.maydell@linaro.org> (odd fixer:SABRELITE / i.MX6) Cc: Jean-Christophe Dubois <jcd@tribudubois.net> (reviewer:SABRELITE / i.MX6) Cc: qemu-arm@nongnu.org (open list:SABRELITE / i.MX6) Cc: qemu-devel@nongnu.org (open list:All patches CC here) Signed-off-by: Vitaly Cheptsov <cheptsov@ispras.ru> Message-id: 20230515095015.66860-1-cheptsov@ispras.ru Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/boot: Make write_bootloader() public as arm_write_bootloader()Cédric Le Goater2023-05-021-0/+49
| | | | | | | | | | | | | | | | | | | | | | | The arm boot.c code includes a utility function write_bootloader() which assists in writing a boot-code fragment into guest memory, including handling endianness and fixing it up with entry point addresses and similar things. This is useful not just for the boot.c code but also in board model code, so rename it to arm_write_bootloader() and make it globally visible. Since we are making it public, make its API a little neater: move the AddressSpace* argument to be next to the hwaddr argument, and allow the fixupcontext array to be const, since we never modify it in this function. Cc: qemu-stable@nongnu.org Signed-off-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230424152717.1333930-2-peter.maydell@linaro.org [PMM: Split out from another patch by Cédric, added doc comment] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* fsl-imx7: Add fec[12]-phy-connected propertiesGuenter Roeck2023-04-201-0/+1
| | | | | | | | | | Add fec[12]-phy-connected properties and use it to set phy-connected and phy-consumer properties for imx_fec. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Message-id: 20230315145248.1639364-5-linux@roeck-us.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* fsl-imx6ul: Add fec[12]-phy-connected propertiesGuenter Roeck2023-04-201-0/+1
| | | | | | | | | | Add fec[12]-phy-connected properties and use it to set phy-connected and phy-consumer properties for imx_fec. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Message-id: 20230315145248.1639364-3-linux@roeck-us.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm: Add WDT to Allwinner-H3 and Orangepi-PCStrahinja Jankovic2023-04-201-1/+4
| | | | | | | | | | This patch adds WDT to Allwinner-H3 and Orangepi-PC. WDT is added as an overlay to the Timer module memory area. Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Message-id: 20230326202256.22980-4-strahinja.p.jankovic@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm: Add WDT to Allwinner-A10 and CubieboardStrahinja Jankovic2023-04-201-0/+2
| | | | | | | | | | This patch adds WDT to Allwinner-A10 and Cubieboard. WDT is added as an overlay to the Timer module memory map. Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Message-id: 20230326202256.22980-3-strahinja.p.jankovic@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw: arm: allwinner-h3: Fix and complete H3 i2c devicesqianfan Zhao2023-03-061-0/+6
| | | | | | | | | | | Allwinner h3 has 4 twi(i2c) devices named twi0, twi1, twi2 and r_twi. The registers are compatible with TYPE_AW_I2C_SUN6I, write 1 to clear control register's INT_FLAG bit. Signed-off-by: qianfan Zhao <qianfanguijin@163.com> Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* aspeed: Introduce a spi_boot region under the SoCCédric Le Goater2023-03-021-0/+5
| | | | | | | | | | | | | | The default boot address of the Aspeed SoCs is 0x0. For this reason, the FMC flash device contents are remapped by HW on the first 256MB of the address space. In QEMU, this is currently done in the machine init with the setup of a region alias. Move this code to the SoC and introduce an extra container to prepare ground for the boot ROM region which will overlap the FMC flash remapping. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* Merge tag 'pull-target-arm-20230227' of ↵Peter Maydell2023-02-278-14/+12
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * Various code cleanups * More refactoring working towards allowing a build without CONFIG_TCG # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmP8ty0ZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3na0EACToAEGC4/iFigdKD7ZwG3F # FvoDcMRRSdElcSo7BTDrFBBOH5/BYhorUq+mVpPvEYADXNaPOCmXWieSJpu68sJC # VpVLPMhGS8lTsT16C2vB/4Lh4t8pJgs7aej90nqKk2rGgKw4ZNwMS+7Eg6n2lKf/ # V27+O+drJxgYzO6feveuKtIQXsHkx4//DNOCDPLLvrrOk+1NWnyPyT/UDxV/emyr # KLBbeXqcNhPkn7xZtvM7WARSHZcqhEPBkIAJG2H9HE4imxNm8d8ADZjEMbfE9ZNE # MDanpM6BYYDWw4y2A8J5QmbiLu3znH8RWmWHww1v6UQ7qyBCLx+HyEGKipGd3Eoe # 48hi/ktsAJUb1lRrk9gOJ+NsokGINzI5urFOReUh1q6+5us0Q0VpwjyVvhi8REy3 # 5gOMDC7O2zH+bLN08kseDXfc7vR9wLrIHqMloMgJzpjG5KcL67nVCPHcOwxe0sfn # 0SYWUY0UFNSYgEGBG6JfM6LiM1lRREzlw6YnnaJ+GUf/jdIUbMV6PKpL34TGLeQ3 # xEWrKV0+PMoWHwN0Pdo1tMXm7mc/9H27Mf7hB5k0Hp3dfQ7nIdkfnFA2YEUSxIQt # OXYsKLTJmO/4XIAYCHhIOncPTmM6KWNQajDJMIuEdYYV67Xb88EIv5Hg8q6tS/mN # uuQfun3Z2UbAtGvzN5Yx1w== # =K0Vo # -----END PGP SIGNATURE----- # gpg: Signature made Mon 27 Feb 2023 13:59:09 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20230227' of https://git.linaro.org/people/pmaydell/qemu-arm: (25 commits) hw: Replace qemu_or_irq typedef by OrIRQState hw/or-irq: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE() hw/irq: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE() iothread: Remove unused IOThreadClass / IOTHREAD_CLASS hw/arm/musicpal: Remove unused dummy MemoryRegion hw/intc/armv7m_nvic: Use QOM cast CPU() macro hw/timer/cmsdk-apb-timer: Remove unused 'qdev-properties.h' header hw/char/cmsdk-apb-uart: Open-code cmsdk_apb_uart_create() hw/char/xilinx_uartlite: Open-code xilinx_uartlite_create() hw/char/xilinx_uartlite: Expose XILINX_UARTLITE QOM type hw/char/pl011: Open-code pl011_luminary_create() hw/char/pl011: Un-inline pl011_create() hw/gpio/max7310: Simplify max7310_realize() tests/avocado: add machine:none tag to version.py cpu-defs.h: Expose CPUTLBEntryFull to non-TCG code target/arm: Don't access TCG code when debugging with KVM target/arm: Move regime_using_lpae_format into internal.h target/arm: Move hflags code into the tcg directory target/arm: Wrap arm_rebuild_hflags calls with tcg_enabled target/arm: Move psci.c into the tcg directory ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw: Replace qemu_or_irq typedef by OrIRQStatePhilippe Mathieu-Daudé2023-02-277-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OBJECT_DECLARE_SIMPLE_TYPE() macro provides the OrIRQState declaration for free. Besides, the QOM code style is to use the structure name as typedef, and QEMU style is to use Camel Case, so rename qemu_or_irq as OrIRQState. Mechanical change using: $ sed -i -e 's/qemu_or_irq/OrIRQState/g' $(git grep -l qemu_or_irq) Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20230113200138.52869-5-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * include/hw/arm/allwinner-a10.h: Remove superfluous includes from the headerThomas Huth2023-02-271-2/+0
| | | | | | | | | | | | | | | | | | | | pci_device.h is not needed at all in allwinner-a10.h, and serial.h is only needed by the corresponding .c file. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20230215152233.210024-1-thuth@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | Updated the FSF address to <https://www.gnu.org/licenses/>Khadija Kamran2023-02-271-2/+1
|/ | | | | | | | | | | | | The Free Software Foundation moved to a new address and some sources in QEMU referred to their old location. The address should be updated and replaced by a pointer to <https://www.gnu.org/licenses/> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/379 Signed-off-by: Khadija Kamran <kkamran.bese16seecs@seecs.edu.pk> Message-Id: <576ee9203fdac99d7251a98faa66b9ce1e7febc5.1675941486.git.kkamran.bese16seecs@seecs.edu.pk> Reviewed-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Thomas Huth <thuth@redhat.com>
* hw/arm/smmu-common: Support 64-bit addressesJean-Philippe Brucker2023-02-161-2/+0
| | | | | | | | | | | Addresses targeting the second translation table (TTB1) in the SMMU have all upper bits set. Ensure the IOMMU region covers all 64 bits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20230214171921.1917916-2-jean-philippe@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm: Attach PSPI module to NPCM7XX SoCHao Wu2023-02-161-0/+2
| | | | | | | | Signed-off-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Titus Rwantare <titusr@google.com> Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org> Message-id: 20230208235433.3989937-4-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/smmuv3: Add GBPA registerMostafa Saleh2023-02-161-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | GBPA register can be used to globally abort all transactions. It is described in the SMMU manual in "6.3.14 SMMU_GBPA". ABORT reset value is IMPLEMENTATION DEFINED, it is chosen to be zero(Do not abort incoming transactions). Other fields have default values of Use Incoming. If UPDATE is not set, the write is ignored. This is the only permitted behavior in SMMUv3.2 and later.(6.3.14.1 Update procedure) As this patch adds a new state to the SMMU (GBPA), it is added in a new subsection for forward migration compatibility. GBPA is only migrated if its value is different from the reset value. It does this to be backward migration compatible if SW didn't write the register. Signed-off-by: Mostafa Saleh <smostafa@google.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20230214094009.2445653-1-smostafa@google.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Do not include "qemu/error-report.h" in headers that do not need itThomas Huth2023-02-141-1/+0
| | | | | | | | | | Include it in the .c files instead that use the error reporting functions. Message-Id: <20230210111931.1115489-1-thuth@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
* include/hw: Do not include "hw/registerfields.h" in headers that don't need itThomas Huth2023-02-141-1/+0
| | | | | | | | Include "hw/registerfields.h" in the .c files instead (if needed). Message-Id: <20230210112315.1116966-1-thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
* Drop duplicate #includeMarkus Armbruster2023-02-082-2/+0
| | | | | | | | | | | Tracked down with the help of scripts/clean-includes. Signed-off-by: Markus Armbruster <armbru@redhat.com> Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20230202133830.2152150-21-armbru@redhat.com>
* hw/arm/aspeed_ast10x0: Map the secure SRAMPhilippe Mathieu-Daudé2023-02-071-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some SRAM appears to be used by the Secure Boot unit and crypto accelerators. Name it 'secure sram'. Note, the SRAM base address was already present but unused (the 'SBC' index is used for the MMIO peripheral). Interestingly using CFLAGS=-Winitializer-overrides reports: ../hw/arm/aspeed_ast10x0.c:32:30: warning: initializer overrides prior initialization of this subobject [-Winitializer-overrides] [ASPEED_DEV_SBC] = 0x7E6F2000, ^~~~~~~~~~ ../hw/arm/aspeed_ast10x0.c:24:30: note: previous initialization is here [ASPEED_DEV_SBC] = 0x79000000, ^~~~~~~~~~ This fixes with Zephyr: uart:~$ rsa test rsa test vector[0]: [00:00:26.156,000] <err> os: ***** BUS FAULT ***** [00:00:26.157,000] <err> os: Precise data bus error [00:00:26.157,000] <err> os: BFAR Address: 0x79000000 [00:00:26.158,000] <err> os: r0/a1: 0x79000000 r1/a2: 0x00000000 r2/a3: 0x00001800 [00:00:26.158,000] <err> os: r3/a4: 0x79001800 r12/ip: 0x00000800 r14/lr: 0x0001098d [00:00:26.158,000] <err> os: xpsr: 0x81000000 [00:00:26.158,000] <err> os: Faulting instruction address (r15/pc): 0x0001e1bc [00:00:26.158,000] <err> os: >>> ZEPHYR FATAL ERROR 0: CPU exception on CPU 0 [00:00:26.158,000] <err> os: Current thread: 0x38248 (shell_uart) [00:00:26.165,000] <err> os: Halting system Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Delevoryas <peter@pjd.dev> [ clg: Fixed size of Secure Boot Controller Memory ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
* hw/arm/aspeed_ast10x0: Add various unimplemented peripheralsPhilippe Mathieu-Daudé2023-02-071-0/+11
| | | | | | | | | | | | | | Based on booting Zephyr demo from [1] running QEMU with '-d unimp' and checking missing devices in [2]. [1] https://github.com/AspeedTech-BMC/zephyr/releases/tag/v00.01.07 [2] https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/dts/arm/aspeed/ast10x0.dtsi Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Delevoryas <peter@pjd.dev> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* hw/arm/virt: Consolidate GIC finalize logicAlexander Graf2023-02-031-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | Up to now, the finalize_gic_version() code open coded what is essentially a support bitmap match between host/emulation environment and desired target GIC type. This open coding leads to undesirable side effects. For example, a VM with KVM and -smp 10 will automatically choose GICv3 while the same command line with TCG will stay on GICv2 and fail the launch. This patch combines the TCG and KVM matching code paths by making everything a 2 pass process. First, we determine which GIC versions the current environment is able to support, then we go through a single state machine to determine which target GIC mode that means for us. After this patch, the only user noticable changes should be consolidated error messages as well as TCG -M virt supporting -smp > 8 automatically. Signed-off-by: Alexander Graf <agraf@csgraf.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Zenghui Yu <yuzenghui@huawei.com> Message-id: 20221223090107.98888-2-agraf@csgraf.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/npcm7xx: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE()Philippe Mathieu-Daudé2023-01-121-12/+6
| | | | | | | | | | | NPCM7XX models have been commited after the conversion from commit 8063396bf3 ("Use OBJECT_DECLARE_SIMPLE_TYPE when possible"). Manually convert them. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230109140306.23161-11-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/intc/omap_intc: Use CamelCase for TYPE_OMAP_INTC type namePhilippe Mathieu-Daudé2023-01-121-5/+4
| | | | | | | | | | | Following docs/devel/style.rst guidelines, rename omap_intr_handler_s -> OMAPIntcState. This also remove a use of 'struct' in the DECLARE_INSTANCE_CHECKER() macro call. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230109140306.23161-7-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>