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* hw/core: Avoid including the full 'hw/core/cpu.h' in 'tcg-cpu-ops.h'Philippe Mathieu-Daudé2024-04-261-1/+5
| | | | | | | | | Only include what is required, avoiding the full CPUState API from the huge "hw/core/cpu.h" header. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240418192525.97451-4-philmd@linaro.org>
* exec: Declare CPUBreakpoint/CPUWatchpoint type in 'breakpoint.h' headerPhilippe Mathieu-Daudé2024-04-261-15/+1
| | | | | | | | | | | | | The CPUBreakpoint and CPUWatchpoint structures are declared in "hw/core/cpu.h", which contains declarations related to CPUState and CPUClass. Some source files only require the BP/WP definitions and don't need to pull in all CPU* API. In order to simplify, create a new "exec/breakpoint.h" header. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20240418192525.97451-3-philmd@linaro.org>
* exec: Declare MMUAccessType type in 'mmu-access-type.h' headerPhilippe Mathieu-Daudé2024-04-261-7/+1
| | | | | | | | | | | | The MMUAccessType enum is declared in "hw/core/cpu.h". "hw/core/cpu.h" contains declarations related to CPUState and CPUClass. Some source files only require MMUAccessType and don't need to pull in all CPU* declarations. In order to simplify, create a new "exec/mmu-access-type.h" header. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240418192525.97451-2-philmd@linaro.org>
* exec: Declare target_words_bigendian() in 'exec/tswap.h'Philippe Mathieu-Daudé2024-04-261-11/+0
| | | | | | | | | | | | | | We usually check target endianess before swapping values, so target_words_bigendian() declaration makes sense in "exec/tswap.h" with the target swapping helpers. Remove "hw/core/cpu.h" when it was only included to get the target_words_bigendian() declaration. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20231212123401.37493-16-philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* accel/hvf: Use accel-specific per-vcpu @dirty fieldPhilippe Mathieu-Daudé2024-04-261-2/+1
| | | | | | | | | | | HVF has a specific use of the CPUState::vcpu_dirty field (CPUState::vcpu_dirty is not used by common code). To make this field accel-specific, add and use a new @dirty variable in the AccelCPUState structure. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240424174506.326-4-philmd@linaro.org>
* exec: Rename NEED_CPU_H -> COMPILING_PER_TARGETPhilippe Mathieu-Daudé2024-04-261-2/+2
| | | | | | | | | | | | | | | | | | 'NEED_CPU_H' guard target-specific code; it is defined by meson altogether with the 'CONFIG_TARGET' definition. Rename NEED_CPU_H as COMPILING_PER_TARGET to clarify its meaning. Mechanical change running: $ sed -i s/NEED_CPU_H/COMPILING_PER_TARGET/g $(git grep -l NEED_CPU_H) then manually add a /* COMPILING_PER_TARGET */ comment after the '#endif' when the block is large. Inspired-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240322161439.6448-4-philmd@linaro.org>
* hw/core: Remove check on NEED_CPU_H in tcg-cpu-ops.hPhilippe Mathieu-Daudé2024-04-251-3/+0
| | | | | | | | | Commit fd3f7d24d4 ("include/hw/core: Remove i386 conditional on fake_user_interrupt") remove the need to check on NEED_CPU_H. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240321154838.95771-3-philmd@linaro.org>
* accel/tcg: Add tlb_fill_flags to CPUTLBEntryFullRichard Henderson2024-03-051-0/+3
| | | | | | | | | | | | Allow the target to set tlb flags to apply to all of the comparators. Remove MemTxAttrs.byte_swap, as the bit is not relevant to memory transactions, only the page mapping. Adjust target/sparc to set TLB_BSWAP directly. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240301204110.656742-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* cpu: Remove page_size_initRichard Henderson2024-02-291-2/+0
| | | | | | | | | | | | Move qemu_host_page_{size,mask} and HOST_PAGE_ALIGN into bsd-user. It should be removed from bsd-user as well, but defer that cleanup. Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Ilya Leoshkevich <iii@linux.ibm.com> Acked-by: Helge Deller <deller@gmx.de> Message-Id: <20240102015808.132373-28-richard.henderson@linaro.org>
* plugins: create CPUPluginState and migrate plugin_maskAlex Bennée2024-02-281-4/+7
| | | | | | | | | | | As we expand the per-vCPU data for plugins we don't want to pollute CPUState. For now this just moves the plugin_mask (renamed to event_mask) as the memory callbacks are accessed directly by TCG generated code. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240227144335.1196131-23-alex.bennee@linaro.org>
* hw/core/cpu: Remove gdb_get_dynamic_xml memberAkihiko Odaki2024-02-281-4/+0
| | | | | | | | | | This function is no longer used. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20231213-gdb-v17-9-777047380591@daynix.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240227144335.1196131-14-alex.bennee@linaro.org>
* gdbstub: Infer number of core registers from XMLAkihiko Odaki2024-02-281-1/+2
| | | | | | | | | | | GDBFeature has the num_regs member so use it where applicable to remove magic numbers. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20231213-gdb-v17-8-777047380591@daynix.com> [AJB: remove core reg check from microblaze read reg] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240227144335.1196131-13-alex.bennee@linaro.org>
* hw/core: Add ResetContainer which holds objects implementing ResettablePeter Maydell2024-02-271-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement a ResetContainer. This is a subclass of Object, and it implements the Resettable interface. The container holds a list of arbitrary other objects which implement Resettable, and when the container is reset, all the objects it contains are also reset. This will allow us to have a 3-phase-reset equivalent of the old qemu_register_reset() API: we will have a single "simulation reset" top level ResetContainer, and objects in it are the equivalent of the old QEMUResetHandler functions. The qemu_register_reset() API manages its list of callbacks using a QTAILQ, but here we use a GPtrArray for our list of Resettable children: we expect the "remove" operation (which will need to do an iteration through the list) to be fairly uncommon, and we get simpler code with fewer memory allocations. Since there is currently no listed owner in MAINTAINERS for the existing reset-related source files, create a new section for them, and add these new files there also. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-id: 20240220160622.114437-7-peter.maydell@linaro.org Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
* include/hw/core: Add mmu_index to CPUClassRichard Henderson2024-02-031-0/+3
| | | | | | | To be used after all targets have populated the hook. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Introduce TCGCPUOps::cpu_exec_halt() handlerPhilippe Mathieu-Daudé2024-01-291-0/+2
| | | | | | | | | | | In order to make accel/tcg/ target agnostic, introduce the cpu_exec_halt() handler. Reviewed-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240124101639.30056-9-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Introduce TCGCPUOps::need_replay_interrupt() handlerPhilippe Mathieu-Daudé2024-01-291-0/+5
| | | | | | | | | | | | In order to make accel/tcg/ target agnostic, introduce the need_replay_interrupt() handler. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Message-Id: <20240124101639.30056-7-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* include/qemu: Add TCGCPUOps typedef to typedefs.hRichard Henderson2024-01-291-4/+1
| | | | | | | QEMU coding style recommends using structure typedefs. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* include/hw/core: Remove i386 conditional on fake_user_interruptAnton Johansson2024-01-291-3/+2
| | | | | | | | | | | Always include fake_user_interrupt in user-only build, despite only being used for i386. This will enable cpu-exec.c to be compiled only once. Signed-off-by: Anton Johansson <anjo@rev.ng> Message-ID: <20240119144024.14289-18-anjo@rev.ng> [rth: Split out of a larger patch; remove TARGET_I386 conditional.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* include/hw/core: Move do_interrupt in TCGCPUOpsAnton Johansson2024-01-291-5/+2
| | | | | | | | | | | The ifdef out of which it is moved is not quite right: do_interrupt is only needed for system mode. Move it to the top of a different ifdef block, which preserves its position within the structure for that case. Signed-off-by: Anton Johansson <anjo@rev.ng> Message-Id: <20240119144024.14289-18-anjo@rev.ng> [rth: Split from a larger patch and simplified.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* hw/core: Include vaddr.h from cpu.hAnton Johansson2024-01-291-1/+1
| | | | | | | | | cpu-common.h is only needed for vaddr Signed-off-by: Anton Johansson <anjo@rev.ng> Message-Id: <20240119144024.14289-8-anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* hw/core/cpu: Update description of CPUState::nodePhilippe Mathieu-Daudé2024-01-051-1/+1
| | | | | | | | | 'next_cpu' was converted to 'node' in commit bdc44640cb ("cpu: Use QTAILQ for CPU list"). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231129183243.15859-1-philmd@linaro.org>
* hw/core/cpu: Remove final vestiges of dynamic state tracingPhilippe Mathieu-Daudé2024-01-051-3/+0
| | | | | | | | | The dynamic state tracing was removed in commit d0aaf08bb9. Fixes: d0aaf08bb9 ("tcg: remove the final vestiges of dstate") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231129182734.15565-1-philmd@linaro.org>
* cpu: Add helper cpu_model_from_type()Gavin Shan2024-01-051-0/+13
| | | | | | | | | | | | | | | | | | Add helper cpu_model_from_type() to extract the CPU model name from the CPU type name in two circumstances: (1) The CPU type name is the combination of the CPU model name and suffix. (2) The CPU type name is same to the CPU model name. The helper will be used in the subsequent commits to conver the CPU type name to the CPU model name. Suggested-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Gavin Shan <gshan@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20231114235628.534334-6-gshan@redhat.com> [PMD: Mention returned string must be released with g_free()] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
* hw/cpu: Update the comments of nr_cores and nr_diesZhao Liu2023-11-071-1/+1
| | | | | | | | | | | | | | | In the nr_threads' comment, specify it represents the number of threads in the "core" to avoid confusion. Also add comment for nr_dies in CPUX86State. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Babu Moger <babu.moger@amd.com> Tested-by: Yongwei Ma <yongwei.ma@intel.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-ID: <20231024090323.1859210-5-zhao1.liu@linux.intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
* hw/cpu: Clean up global variable shadowingPhilippe Mathieu-Daudé2023-11-071-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | Fix: hw/core/machine.c:1302:22: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] const CPUArchId *cpus = possible_cpus->cpus; ^ hw/core/numa.c:69:17: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] uint16List *cpus = NULL; ^ hw/acpi/aml-build.c:2005:20: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] CPUArchIdList *cpus = ms->possible_cpus; ^ hw/core/machine-smp.c:77:14: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] unsigned cpus = config->has_cpus ? config->cpus : 0; ^ include/hw/core/cpu.h:589:17: note: previous declaration is here extern CPUTailQ cpus; ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Ani Sinha <anisinha@redhat.com> Message-Id: <20231010115048.11856-2-philmd@linaro.org>
* exec/cpu: Have cpu_exec_realize() return a booleanPhilippe Mathieu-Daudé2023-11-071-1/+1
| | | | | | | | | | Following the example documented since commit e3fe3988d7 ("error: Document Error API usage rules"), have cpu_exec_realizefn() return a boolean indicating whether an error is set or not. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230918160257.30127-22-philmd@linaro.org>
* hw/cpu: Call object_class_is_abstract() once in cpu_class_by_name()Philippe Mathieu-Daudé2023-11-071-3/+4
| | | | | | | | | Let CPUClass::class_by_name() handlers to return abstract classes, and filter them once in the public cpu_class_by_name() method. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908112235.75914-3-philmd@linaro.org>
* accel: Introduce cpu_exec_reset_hold()Philippe Mathieu-Daudé2023-11-071-0/+1
| | | | | | | | | | | | | Introduce cpu_exec_reset_hold() which call an accelerator specific AccelOpsClass::cpu_reset_hold() handler. Define a stub on TCG user emulation, because CPU reset is irrelevant there. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230918104153.24433-3-philmd@linaro.org>
* memory: follow Error API guidelinesMarc-André Lureau2023-10-192-2/+4
| | | | | | | | | | Return true/false on success/failure. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20231009075310.153617-1-marcandre.lureau@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
* gdbstub: Replace gdb_regs with an arrayAkihiko Odaki2023-10-111-1/+1
| | | | | | | | | | | | | An array is a more appropriate data structure than a list for gdb_regs since it is initialized only with append operation and read-only after initialization. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230912224107.29669-13-akihiko.odaki@daynix.com> [AJB: fixed a checkpatch violation] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20231009164104.369749-20-alex.bennee@linaro.org>
* hw/core/cpu: Return static value with gdb_arch_name()Akihiko Odaki2023-10-111-1/+1
| | | | | | | | | | | | | | | | All implementations of gdb_arch_name() returns dynamic duplicates of static strings. It's also unlikely that there will be an implementation of gdb_arch_name() that returns a truly dynamic value due to the nature of the function returning a well-known identifiers. Qualify the value gdb_arch_name() with const and make all of its implementations return static strings. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230912224107.29669-8-akihiko.odaki@daynix.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20231009164104.369749-15-alex.bennee@linaro.org>
* accel/tcg: Replace CPUState.env_ptr with cpu_env()Richard Henderson2023-10-041-3/+6
| | | | | Reviewed-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Move can_do_io to CPUNegativeOffsetStateRichard Henderson2023-10-031-4/+2
| | | | | | | | | Minimize the displacement to can_do_io, since it may be touched at the start of each TranslationBlock. It fits into other padding within the substructure. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Remove CPUState.icount_decr_ptrRichard Henderson2023-10-031-2/+0
| | | | | | | We can now access icount_decr directly. Reviewed-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Move CPUNegativeOffsetState into CPUStateRichard Henderson2023-10-031-2/+15
| | | | | | | | Retain the separate structure to emphasize its importance. Enforce CPUArchState always follows CPUState without padding. Reviewed-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Move CPUTLB definitions from cpu-defs.hRichard Henderson2023-10-031-0/+141
| | | | | | | | Accept that we will consume space in CPUState for CONFIG_USER_ONLY, since we cannot test CONFIG_SOFTMMU within hw/core/cpu.h. Reviewed-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel: Rename AccelCPUClass::cpu_realizefn() -> cpu_target_realize()Philippe Mathieu-Daudé2023-10-031-1/+1
| | | | | | | | | | The AccelCPUClass::cpu_realizefn handler is meant for target specific code, rename it using '_target_' to emphasis it. Suggested-by: Claudio Fontana <cfontana@suse.de> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20231003123026.99229-3-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Simplify tlb_plugin_lookupRichard Henderson2023-09-161-13/+0
| | | | | | | | | | | | | | | Now that we defer address space update and tlb_flush until the next async_run_on_cpu, the plugin run at the end of the instruction no longer has to contend with a flushed tlb. Therefore, delete SavedIOTLB entirely. Properly return false from tlb_plugin_lookup when we do not have a tlb match. Fixes a bug in which SavedIOTLB had stale data, because there were multiple i/o accesses within a single insn. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: spelling fixesMichael Tokarev2023-08-311-1/+1
| | | | | | | | Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Message-ID: <20230823065335.1919380-18-mjt@tls.msk.ru> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-ID: <20230823065335.1919380-19-mjt@tls.msk.ru> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
* accel: Remove HAX acceleratorPhilippe Mathieu-Daudé2023-08-311-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | HAX is deprecated since commits 73741fda6c ("MAINTAINERS: Abort HAXM maintenance") and 90c167a1da ("docs/about/deprecated: Mark HAXM in QEMU as deprecated"), released in v8.0.0. Per the latest HAXM release (v7.8 [*]), the latest QEMU supported is v7.2: Note: Up to this release, HAXM supports QEMU from 2.9.0 to 7.2.0. The next commit (https://github.com/intel/haxm/commit/da1b8ec072) added: HAXM v7.8.0 is our last release and we will not accept pull requests or respond to issues after this. It became very hard to build and test HAXM. Its previous maintainers made it clear they won't help. It doesn't seem to be a very good use of QEMU maintainers to spend their time in a dead project. Save our time by removing this orphan zombie code. [*] https://github.com/intel/haxm/releases/tag/v7.8.0 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20230831082016.60885-1-philmd@linaro.org>
* plugins: force slow path when plugins instrument memory opsAlex Bennée2023-07-031-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The lack of SVE memory instrumentation has been an omission in plugin handling since it was introduced. Fortunately we can utilise the probe_* functions to force all all memory access to follow the slow path. We do this by checking the access type and presence of plugin memory callbacks and if set return the TLB_MMIO flag. We have to jump through a few hoops in user mode to re-use the flag but it was the desired effect: ./qemu-system-aarch64 -display none -serial mon:stdio \ -M virt -cpu max -semihosting-config enable=on \ -kernel ./tests/tcg/aarch64-softmmu/memory-sve \ -plugin ./contrib/plugins/libexeclog.so,ifilter=st1w,afilter=0x40001808 -d plugin gives (disas doesn't currently understand st1w): 0, 0x40001808, 0xe54342a0, ".byte 0xa0, 0x42, 0x43, 0xe5", store, 0x40213010, RAM, store, 0x40213014, RAM, store, 0x40213018, RAM And for user-mode: ./qemu-aarch64 \ -plugin contrib/plugins/libexeclog.so,afilter=0x4007c0 \ -d plugin \ ./tests/tcg/aarch64-linux-user/sha512-sve gives: 1..10 ok 1 - do_test(&tests[i]) 0, 0x4007c0, 0xa4004b80, ".byte 0x80, 0x4b, 0x00, 0xa4", load, 0x5500800370, load, 0x5500800371, load, 0x5500800372, load, 0x5500800373, load, 0x5500800374, load, 0x5500800375, load, 0x5500800376, load, 0x5500800377, load, 0x5500800378, load, 0x5500800379, load, 0x550080037a, load, 0x550080037b, load, 0x550080037c, load, 0x550080037d, load, 0x550080037e, load, 0x550080037f, load, 0x5500800380, load, 0x5500800381, load, 0x5500800382, load, 0x5500800383, load, 0x5500800384, load, 0x5500800385, load, 0x5500800386, lo ad, 0x5500800387, load, 0x5500800388, load, 0x5500800389, load, 0x550080038a, load, 0x550080038b, load, 0x550080038c, load, 0x550080038d, load, 0x550080038e, load, 0x550080038f, load, 0x5500800390, load, 0x5500800391, load, 0x5500800392, load, 0x5500800393, load, 0x5500800394, load, 0x5500800395, load, 0x5500800396, load, 0x5500800397, load, 0x5500800398, load, 0x5500800399, load, 0x550080039a, load, 0x550080039b, load, 0x550080039c, load, 0x550080039d, load, 0x550080039e, load, 0x550080039f, load, 0x55008003a0, load, 0x55008003a1, load, 0x55008003a2, load, 0x55008003a3, load, 0x55008003a4, load, 0x55008003a5, load, 0x55008003a6, load, 0x55008003a7, load, 0x55008003a8, load, 0x55008003a9, load, 0x55008003aa, load, 0x55008003ab, load, 0x55008003ac, load, 0x55008003ad, load, 0x55008003ae, load, 0x55008003af (4007c0 is the ld1b in the sha512-sve) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Cc: Robert Henry <robhenry@microsoft.com> Cc: Aaron Lindsay <aaron@os.amperecomputing.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20230630180423.558337-20-alex.bennee@linaro.org>
* accel: Rename HVF 'struct hvf_vcpu_state' -> AccelCPUStatePhilippe Mathieu-Daudé2023-06-281-4/+0
| | | | | | | | | | | | | | | | We want all accelerators to share the same opaque pointer in CPUState. Rename the 'hvf_vcpu_state' structure as 'AccelCPUState'. Use the generic 'accel' field of CPUState instead of 'hvf'. Replace g_malloc0() by g_new0() for readability. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20230624174121.11508-17-philmd@linaro.org>
* accel: Move HAX hThread to accelerator contextPhilippe Mathieu-Daudé2023-06-281-1/+0
| | | | | | | | | hThread variable is only used by the HAX accelerator, so move it to the accelerator specific context. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230624174121.11508-9-philmd@linaro.org>
* accel: Rename HAX 'struct hax_vcpu_state' -> AccelCPUStatePhilippe Mathieu-Daudé2023-06-281-3/+2
| | | | | | | | | | | | | We want all accelerators to share the same opaque pointer in CPUState. Start with the HAX context, renaming its forward declarated structure 'hax_vcpu_state' as 'AccelCPUState'. Document the CPUState field. Directly use the typedef. Remove the amusing but now unnecessary casts in NVMM / WHPX. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230624174121.11508-8-philmd@linaro.org>
* accel: Rename 'hax_vcpu' as 'accel' in CPUStatePhilippe Mathieu-Daudé2023-06-281-1/+1
| | | | | | | | | All accelerators will share a single opaque context in CPUState. Start by renaming 'hax_vcpu' as 'accel'. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230624174121.11508-7-philmd@linaro.org>
* accel/tcg: Store some tlb flags in CPUTLBEntryFullRichard Henderson2023-06-261-0/+1
| | | | | | | | | | | | | | | We have run out of bits we can use within the CPUTLBEntry comparators, as TLB_FLAGS_MASK cannot overlap alignment. Store slow_flags[] in CPUTLBEntryFull, and merge with the flags from the comparator. A new TLB_FORCE_SLOW bit is set within the comparator as an indication that the slow path must be used. Move TLB_BSWAP to TLB_SLOW_FLAGS_MASK. Since we are out of bits, we cannot create a new bit without moving an old one. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* kvm: reuse per-vcpu stats fd to avoid vcpu interruptionMarcelo Tosatti2023-06-261-0/+1
| | | | | | | | | | | | | | | | | A regression has been detected in latency testing of KVM guests. More specifically, it was observed that the cyclictest numbers inside of an isolated vcpu (running on isolated pcpu) are: Where a maximum of 50us is acceptable. The implementation of KVM_GET_STATS_FD uses run_on_cpu to query per vcpu statistics, which interrupts the vcpu (and is unnecessary). To fix this, open the per vcpu stats fd on vcpu initialization, and read from that fd from QEMU's main thread. Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* Revert "cputlb: Restrict SavedIOTLB to system emulation"Peter Maydell2023-06-211-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit d7ee93e24359703debf4137f4cc632563aa4e8d1. That commit tries to make a field in the CPUState struct not be present when CONFIG_USER_ONLY is set. Unfortunately, you can't conditionally omit fields in structs like this based on ifdefs that are set per-target. If you try it, then code in files compiled per-target (where CONFIG_USER_ONLY is or can be set) will disagree about the struct layout with files that are compiled once-only (where this kind of ifdef is never set). This manifests specifically in 'make check-tcg' failing, because code in cpus-common.c that sets up the CPUState::cpu_index field puts it at a different offset from the code in plugins/core.c in qemu_plugin_vcpu_init_hook() which reads the cpu_index field. The latter then hits an assert because from its point of view every thread has a 0 cpu_index. There might be other weird behaviour too. Mostly we catch this kind of bug because the CONFIG_whatever is listed in include/exec/poison.h and so the reference to it in build-once source files will then cause a compiler error. Unfortunately CONFIG_USER_ONLY is an exception to that: we have some places where we use it in "safe" ways in headers that will be seen by once-only source files (e.g. ifdeffing out function prototypes) and it would be a lot of refactoring to be able to get to a position where we could poison it. This leaves us in a "you have to be careful to walk around the bear trap" situation... Fixes: d7ee93e243597 ("cputlb: Restrict SavedIOTLB to system emulation") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20230620175712.1331625-1-peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* cputlb: Restrict SavedIOTLB to system emulationPhilippe Mathieu-Daudé2023-06-201-2/+4
| | | | | | | | | | | Commit 2f3a57ee47 ("cputlb: ensure we save the IOTLB data in case of reset") added the SavedIOTLB structure -- which is system emulation specific -- in the generic CPUState structure. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221216215519.5522-3-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* hw/core/cpu: Check for USER_ONLY definition instead of SOFTMMU onePhilippe Mathieu-Daudé2023-06-202-53/+53
| | | | | | | | | | | | Since we *might* have user emulation with softmmu, replace the system emulation check by !user emulation one. Invert the #ifdef'ry in TCGCPUOps structure for clarity. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230613133347.82210-6-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>