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2025-03-08exec: Declare tlb_hit*() in 'exec/cputlb.h'Philippe Mathieu-Daudé2-23/+23
Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20241114011310.3615-20-philmd@linaro.org>
2025-03-08exec: Declare tlb_set_page() in 'exec/cputlb.h'Philippe Mathieu-Daudé15-15/+24
Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20241114011310.3615-18-philmd@linaro.org>
2025-03-08exec: Declare tlb_set_page_with_attrs() in 'exec/cputlb.h'Philippe Mathieu-Daudé4-27/+30
Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20241114011310.3615-17-philmd@linaro.org>
2025-03-08exec: Declare tlb_set_page_full() in 'exec/cputlb.h'Philippe Mathieu-Daudé3-23/+24
Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20241114011310.3615-16-philmd@linaro.org>
2025-03-08exec: Declare tlb_reset_dirty*() in 'exec/cputlb.h'Philippe Mathieu-Daudé4-3/+9
Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20241114011310.3615-14-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-03-08accel/tcg: Compile watchpoint.c onceRichard Henderson4-6/+5
Move tb_check_watchpoint declaration from tb-internal.h, which is still target-specific, to internal-common.h, which isn't. Otherwise, all that is required to build watchpoint.c once is to include the new exec/cpu-interrupt.h instead of exec/exec-all.h. Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-03-08include/exec: Split out exec/cpu-interrupt.hRichard Henderson3-65/+71
Some of these bits are actually common to all cpus; while the reset have common reservations for target-specific usage. While generic code cannot know what the target-specific usage is, common code can know what to do with the bits, e.g. single-step. Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-03-07include/exec: Move TARGET_PAGE_{SIZE,MASK,BITS} to target_page.hRichard Henderson5-48/+51
Re-use the TARGET_PAGE_BITS_VARY mechanism to define TARGET_PAGE_SIZE and friends when not compiling per-target. Inline qemu_target_page_{size,mask,bits} as they are now trivial. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-03-07accel/tcg: Restrict CPU_TLB_DYN_*_BITS definitions to accel/tcg/Philippe Mathieu-Daudé2-26/+27
CPU_TLB_DYN_*_BITS definitions are only used by accel/tcg/cputlb.c and accel/tcg/translate-all.c. Move them to accel/tcg/tb-internal.h. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250305191859.71608-1-philmd@linaro.org>
2025-03-07linux-user/main: Allow setting tb-sizeIlya Leoshkevich1-0/+12
While qemu-system can set tb-size using -accel tcg,tb-size=n, there is no similar knob for qemu-user. Add one in a way similar to how one-insn-per-tb is already handled. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240730215532.1442-1-iii@linux.ibm.com>
2025-03-06include: Poison TARGET_PHYS_ADDR_SPACE_BITS definitionPhilippe Mathieu-Daudé1-0/+1
Ensure common code never use this target specific definition. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250305153929.43687-4-philmd@linaro.org>
2025-03-06system: Open-code qemu_init_arch_modules() using target_name()Philippe Mathieu-Daudé3-12/+6
Mostly revert commit c80cafa0c73 ("system: Add qemu_init_arch_modules") but using target_name() instead of the target specific 'TARGET_NAME' definition. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250305005225.95051-3-philmd@linaro.org>
2025-03-06target/i386: Mark WHPX APIC region as little-endianPhilippe Mathieu-Daudé1-1/+1
This device is only used by the x86 targets, which are only built as little-endian. Therefore the DEVICE_NATIVE_ENDIAN definition expand to DEVICE_LITTLE_ENDIAN (besides, the DEVICE_BIG_ENDIAN case isn't tested). Simplify directly using DEVICE_LITTLE_ENDIAN. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250212113938.38692-6-philmd@linaro.org>
2025-03-06target/alpha: Do not mix exception flags and FPCR bitsPhilippe Mathieu-Daudé1-8/+7
get_float_exception_flags() returns exception flags, which are distinct from the FPCR bits used as error code. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250211162604.83446-1-philmd@linaro.org>
2025-03-06target/riscv: Convert misa_mxl_max using GLib macrosPhilippe Mathieu-Daudé1-5/+5
Use GLib conversion macros to pass misa_mxl_max as riscv_cpu_class_init() class data. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210133134.90879-6-philmd@linaro.org>
2025-03-06target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXLPhilippe Mathieu-Daudé2-2/+2
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210133134.90879-5-philmd@linaro.org>
2025-03-06target/xtensa: Finalize config in xtensa_register_core()Philippe Mathieu-Daudé2-3/+4
Make XtensaConfigList::config not const. Only modify XtensaConfig within xtensa_register_core(), when the class is registered, not when it is initialized. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Message-Id: <20250210133134.90879-4-philmd@linaro.org>
2025-03-06target/sparc: Constify SPARCCPUClass::cpu_defPhilippe Mathieu-Daudé1-1/+1
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210133134.90879-3-philmd@linaro.org>
2025-03-06target/i386: Constify X86CPUModel usesPhilippe Mathieu-Daudé2-5/+5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210133134.90879-2-philmd@linaro.org>
2025-03-06disas: Remove target_words_bigendian() call in initialize_debug_target()Philippe Mathieu-Daudé1-6/+2
All CPUClass implementating disas_set_info() must set the disassemble_info::endian value. Ensure that by setting %endian to BFD_ENDIAN_UNKNOWN before calling the CPUClass::disas_set_info() handler, then asserting %endian is not BFD_ENDIAN_UNKNOWN after the call. This allows removing the target_words_bigendian() call in disas/. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20250210212931.62401-11-philmd@linaro.org>
2025-03-06target/xtensa: Set disassemble_info::endian value in disas_set_info()Philippe Mathieu-Daudé1-0/+2
Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210212931.62401-10-philmd@linaro.org>
2025-03-06target/sh4: Set disassemble_info::endian value in disas_set_info()Philippe Mathieu-Daudé1-0/+2
Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210212931.62401-9-philmd@linaro.org>
2025-03-06target/riscv: Set disassemble_info::endian value in disas_set_info()Philippe Mathieu-Daudé1-0/+9
Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210212931.62401-8-philmd@linaro.org>
2025-03-06target/ppc: Set disassemble_info::endian value in disas_set_info()Philippe Mathieu-Daudé1-0/+2
Have the CPUClass::disas_set_info() callback always set\ the disassemble_info::endian field. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210212931.62401-7-philmd@linaro.org>
2025-03-06target/mips: Set disassemble_info::endian value in disas_set_info()Philippe Mathieu-Daudé1-5/+5
Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210212931.62401-6-philmd@linaro.org>
2025-03-06target/microblaze: Set disassemble_info::endian value in disas_set_infoPhilippe Mathieu-Daudé1-0/+2
Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210212931.62401-5-philmd@linaro.org>
2025-03-06target/arm: Set disassemble_info::endian value in disas_set_info()Philippe Mathieu-Daudé1-7/+3
Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210212931.62401-4-philmd@linaro.org>
2025-03-06target: Set disassemble_info::endian value for big-endian targetsPhilippe Mathieu-Daudé5-0/+5
Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field for big-endian targets. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210212931.62401-3-philmd@linaro.org>
2025-03-06target: Set disassemble_info::endian value for little-endian targetsPhilippe Mathieu-Daudé6-0/+6
Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field for little-endian targets. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210212931.62401-2-philmd@linaro.org>
2025-03-06target/mips: Fix possible MSA int overflowDenis Rastyogin1-3/+3
Fix possible overflow in 1 << (DF_BITS(df) - 2) when DF_BITS(df) is 64 by using a 64-bit integer for the shift operation. Found by Linux Verification Center (linuxtesting.org) with SVACE. Reported-by: Dmitriy Fedin <d.fedin@fobos-nt.ru> Signed-off-by: Denis Rastyogin <gerben@altlinux.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-ID: <20250124122707.54264-1-gerben@altlinux.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-03-06target/tricore: Ensure not being build on user emulationPhilippe Mathieu-Daudé1-0/+4
Currently only system emulation is supported. Assert no target code is built for user emulation. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250121142341.17001-4-philmd@linaro.org>
2025-03-06target/rx: Ensure not being build on user emulationPhilippe Mathieu-Daudé3-12/+4
Currently only system emulation is supported. Assert no target code is built for user emulation. Remove #ifdef'ry since more work is required before being able to emulate a user process. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250121142341.17001-3-philmd@linaro.org>
2025-03-06target/hexagon: Ensure not being build on system emulationPhilippe Mathieu-Daudé1-0/+4
Currently only user emulation is supported. Assert no target code is built for system emulation. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com> Message-Id: <20250121142341.17001-2-philmd@linaro.org>
2025-03-06target/openrisc: Call cpu_openrisc_clock_init() in cpu_realize()Philippe Mathieu-Daudé3-4/+4
OpenRISC timer is architecturally tied to the CPU. It doesn't belong to the machine init() code to instanciate it: move its creation when a vCPU is realized (after being created). Reported-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250114231304.77150-1-philmd@linaro.org>
2025-03-06target/i386/hvf: Variable type fixup in decoderPhil Dennis-Jordan1-2/+2
decode_bytes reads 1, 2, 4, or 8 bytes at a time. The destination variable should therefore be a uint64_t, not a target_ulong. Signed-off-by: Phil Dennis-Jordan <phil@philjordan.eu> Fixes: ff2de1668c9 ("i386: hvf: remove addr_t") Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20241209203629.74436-9-phil@philjordan.eu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-03-06target/microblaze: Consider endianness while translating codePhilippe Mathieu-Daudé2-2/+10
Consider the CPU ENDI bit, swap instructions when the CPU endianness doesn't match the binary one. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241105130431.22564-17-philmd@linaro.org>
2025-03-06target/microblaze: Introduce mo_endian() helperPhilippe Mathieu-Daudé1-4/+10
mo_endian() returns the target endianness, currently static. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241105130431.22564-16-philmd@linaro.org>
2025-03-06target/microblaze: Set MO_TE once in do_load() / do_store()Philippe Mathieu-Daudé1-16/+20
All callers of do_load() / do_store() set MO_TE flag. Set it once in the callees. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241105130431.22564-15-philmd@linaro.org>
2025-03-06target/microblaze: Explode MO_TExx -> MO_TE | MO_xxPhilippe Mathieu-Daudé1-18/+18
Extract the implicit MO_TE definition in order to replace it by runtime variable in the next commit. Mechanical change using: $ for n in UW UL UQ UO SW SL SQ; do \ sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \ $(git grep -l MO_TE$n target/microblaze); \ done Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20241105130431.22564-14-philmd@linaro.org>
2025-03-06hw/core/generic-loader: Do not open-code cpu_set_pc()Philippe Mathieu-Daudé1-4/+1
Directly call cpu_set_pc() instead of open-coding it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250122093028.52416-2-philmd@linaro.org>
2025-03-06cpus: Restrict cpu_get_memory_mapping() to system emulationPhilippe Mathieu-Daudé1-2/+2
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250121142341.17001-5-philmd@linaro.org>
2025-03-06cpus: Have cpu_exec_initfn() per user / system emulationPhilippe Mathieu-Daudé3-9/+12
Slighly simplify cpu-target.c again by extracting cpu_exec_initfn() to cpu-{system,user}.c, adding an empty stub for user emulation. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250123234415.59850-19-philmd@linaro.org>
2025-03-06cpus: Have cpu_class_init_props() per user / system emulationPhilippe Mathieu-Daudé5-59/+72
Rather than maintaining a mix of system / user code for CPU class properties, move system properties to cpu-system.c and user ones to the new cpu-user.c unit. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250123234415.59850-18-philmd@linaro.org>
2025-03-06cpus: Restrict cpu_common_post_load() code to TCGPhilippe Mathieu-Daudé1-16/+19
CPU_INTERRUPT_EXIT was removed in commit 3098dba01c7 ("Use a dedicated function to request exit from execution loop"), tlb_flush() and tb_flush() are related to TCG accelerator. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250123234415.59850-17-philmd@linaro.org>
2025-03-06cpus: Fix style in cpu-target.cPhilippe Mathieu-Daudé1-3/+6
Fix style on code we are going to modify. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250123234415.59850-16-philmd@linaro.org>
2025-03-06accel/kvm: Remove unused 'system/cpus.h' header in kvm-cpus.hPhilippe Mathieu-Daudé1-2/+0
Missed in commit b86f59c7155 ("accel: replace struct CpusAccel with AccelOpsClass") which removed the single CpusAccel use. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250123234415.59850-7-philmd@linaro.org>
2025-03-06accel/tcg: Move cpu_memory_rw_debug() user implementation to user-exec.cPhilippe Mathieu-Daudé2-88/+82
cpu_memory_rw_debug() system implementation is defined in system/physmem.c. Move the user one to accel/tcg/user-exec.c to simplify cpu-target.c maintenance. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250217130610.18313-6-philmd@linaro.org>
2025-03-06accel/tcg: Avoid using lock_user() in cpu_memory_rw_debug()Philippe Mathieu-Daudé1-15/+2
We checked the page flags with page_get_flags(), so locking the page is superfluous. Remove the lock_user() calls and directly use g2h() in place. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250217130610.18313-5-philmd@linaro.org>
2025-03-06accel/tcg: Take mmap lock in the whole cpu_memory_rw_debug() functionPhilippe Mathieu-Daudé1-2/+4
Simplify user implementation of cpu_memory_rw_debug() by taking the mmap lock globally. See commit 87ab2704296 ("linux-user: Allow gdbstub to ignore page protection") for why this lock is necessary. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250217130610.18313-4-philmd@linaro.org>
2025-03-06accel/tcg: Include missing bswap headers in user-exec.cPhilippe Mathieu-Daudé1-0/+2
Commit 35c653c4029 ("tcg: Add 128-bit guest memory primitives") introduced the use of bswap128() which is declared in "qemu/int128.h", commit de95016dfbf ("accel/tcg: Implement helper_{ld,st}*_mmu for user-only") introduced the other bswap*() uses, which are declared in "qemu/bswap.h". Include the missing headers. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250217130610.18313-3-philmd@linaro.org>