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* util/cacheflush.c: Update cache flushing mechanism for EmscriptenKohei Tokunaga2025-05-061-0/+7
| | | | | | | | | | | | | | | | | Although __builtin___clear_cache is used to flush the instruction cache for a specified memory region, this operation doesn't apply to wasm, as its memory isn't executable. Moreover, Emscripten does not support this builtin and fails to compile it with the following error. > fatal error: error in backend: llvm.clear_cache is not supported on wasm To resolve this, this commit removes the call to __builtin___clear_cache for Emscripten build. Signed-off-by: Kohei Tokunaga <ktokunaga.mail@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Link: https://lore.kernel.org/r/2926a798fa52a3a5b11c3df4edd1643d2b7cdcb9.1745820062.git.ktokunaga.mail@gmail.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* util: Enhance flush_icache_range with separate data pointerRichard Henderson2021-01-071-2/+13
| | | | | | | | | | | | | We are shortly going to have a split rw/rx jit buffer. Depending on the host, we need to flush the dcache at the rw data pointer and flush the icache at the rx code pointer. For now, the two passed pointers are identical, so there is no effective change in behaviour. Reviewed-by: Joelle van Dyne <j@getutm.app> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* util: Extract flush_icache_range to cacheflush.cRichard Henderson2021-01-021-0/+24
This has been a tcg-specific function, but is also in use by hardware accelerators via physmem.c. This can cause link errors when tcg is disabled. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Joelle van Dyne <j@getutm.app> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201214140314.18544-3-richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>