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2021-06-21s390x/css: Add passthrough IRBEric Farman4-1/+23
Wire in the subchannel callback for building the IRB ESW and ECW space for passthrough devices, and copy the hardware's ESW into the IRB we are building. If the hardware presented concurrent sense, then copy that sense data into the IRB's ECW space. Signed-off-by: Eric Farman <farman@linux.ibm.com> Message-Id: <20210617232537.1337506-5-farman@linux.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/css: Refactor IRB constructionEric Farman4-16/+33
Currently, all subchannel types have "sense data" copied into the IRB.ECW space, and a couple flags enabled in the IRB.SCSW and IRB.ESW. But for passthrough (vfio-ccw) subchannels, this data isn't populated in the first place, so enabling those flags leads to unexpected behavior if the guest tries to process the sense data (zeros) in the IRB.ECW. Let's add a subchannel callback that builds these portions of the IRB, and move the existing code into a routine for those virtual subchannels. The passthrough subchannels will be able to piggy-back onto this later. Signed-off-by: Eric Farman <farman@linux.ibm.com> Message-Id: <20210617232537.1337506-4-farman@linux.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/css: Split out the IRB sense dataEric Farman1-7/+12
Let's move this logic into its own routine, so it can be reused later. Signed-off-by: Eric Farman <farman@linux.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210617232537.1337506-3-farman@linux.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/css: Introduce an ESW structEric Farman2-7/+24
The Interrupt Response Block is comprised of several other structures concatenated together, but only the 12-byte Subchannel-Status Word (SCSW) is defined as a proper struct. Everything else is a simple array of 32-bit words. Let's define a proper struct for the 20-byte Extended-Status Word (ESW) so that we can make good decisions about the sense data that would go into the ECW area for virtual vs passthrough devices. [CH: adapted ESW definition to build with mingw, as discussed] Signed-off-by: Eric Farman <farman@linux.ibm.com> Message-Id: <20210617232537.1337506-2-farman@linux.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21linux-user/s390x: Save and restore psw.mask properlyRichard Henderson1-5/+32
At present, we're referencing env->psw.mask directly, which fails to ensure that env->cc_op is incorporated or updated. Use s390_cpu_{set_psw,get_psw_mask} to fix this. Mirror the kernel's cleaning of the psw.mask in save_sigregs and restore_sigregs. Ignore PSW_MASK_RI for now, as qemu does not support that. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Tested-by: jonathan.albrecht <jonathan.albrecht@linux.vnet.ibm.com> Tested-by: <ruixin.bao@ibm.com> Message-Id: <20210615030744.1252385-6-richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21target/s390x: Use s390_cpu_{set_psw, get_psw_mask} in gdbstubRichard Henderson1-13/+2
No change in behaviour, as gdbstub was correctly written to install and extract the cc value. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Tested-by: jonathan.albrecht <jonathan.albrecht@linux.vnet.ibm.com> Tested-by: <ruixin.bao@ibm.com> Message-Id: <20210615030744.1252385-5-richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21target/s390x: Improve s390_cpu_dump_state vs cc_opRichard Henderson1-5/+7
Use s390_cpu_get_psw_mask so that we print the correct architectural value of psw.mask. Do not print cc_op unless tcg_enabled. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Tested-by: jonathan.albrecht <jonathan.albrecht@linux.vnet.ibm.com> Tested-by: <ruixin.bao@ibm.com> Message-Id: <20210615030744.1252385-4-richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21target/s390x: Do not modify cpu state in s390_cpu_get_psw_maskRichard Henderson1-4/+4
We want to use this function for debugging, and debug should not modify cpu state (even non-architectural cpu state) lest we introduce heisenbugs. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Tested-by: jonathan.albrecht <jonathan.albrecht@linux.vnet.ibm.com> Tested-by: <ruixin.bao@ibm.com> Message-Id: <20210615030744.1252385-3-richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21target/s390x: Expose load_psw and get_psw_mask to cpu.hRichard Henderson6-61/+69
Rename to s390_cpu_set_psw and s390_cpu_get_psw_mask at the same time. Adjust so that they compile for user-only. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Tested-by: jonathan.albrecht <jonathan.albrecht@linux.vnet.ibm.com> Tested-by: <ruixin.bao@ibm.com> Message-Id: <20210615030744.1252385-2-richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21configure: Check whether we can compile the s390-ccw bios with -msoft-floatThomas Huth1-1/+1
The -msoft-float switch is not available in older versions of Clang. Since we rely on the compiler to not generate floating point instructions unexpectedly, we block those old compilers now via a test in the configure script. Note that for some weird reasons, the Clang compiler only complains about the missing soft-float support if no other flags are passed via "-Wl,..." to the linker. So we have to use "compile_object" instead of "compile_prog" for this check. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210525142032.156989-1-thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/cpumodel: Bump up QEMU model to a stripped-down IBM z14 GA2David Hildenbrand3-8/+14
TCG implements everything we need to run basic z14 OS+software. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-27-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: We support Vector enhancements facilityDavid Hildenbrand1-0/+1
Everything is wired up and all new instructions are implemented. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-26-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21linux-user: elf: s390x: Prepare for Vector enhancements facilityDavid Hildenbrand2-0/+8
Let's check for S390_FEAT_VECTOR_ENH and set HWCAP_S390_VXRS_EXT accordingly. Add all missing HWCAP defined in upstream Linux. Cc: Laurent Vivier <laurent@vivier.eu> Acked-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-25-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Implement VECTOR FP (MAXIMUM|MINIMUM)David Hildenbrand5-0/+391
For IEEE functions, we can reuse the softfloat implementations. For the other functions, implement it generically for 32bit/64bit/128bit - carefully taking care of all weird special cases according to the tables defined in the PoP. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-24-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Implement VECTOR FP NEGATIVE MULTIPLY AND (ADD|SUBTRACT)David Hildenbrand4-2/+49
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-23-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR FP MULTIPLY AND (ADD|SUBTRACT)David Hildenbrand3-8/+87
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-22-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR FP TEST DATA CLASS IMMEDIATEDavid Hildenbrand3-2/+70
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-21-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR FP PERFORM SIGN OPERATIONDavid Hildenbrand1-33/+73
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-20-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Implement 128 bit for VECTOR FP LOAD ROUNDEDDavid Hildenbrand3-1/+30
128 bit -> 64 bit, there is only a single element to process. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-19-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Implement 64 bit for VECTOR FP LOAD LENGTHENEDDavid Hildenbrand3-3/+30
64 bit -> 128 bit, there is only a single final element. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-18-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE (AND SIGNAL) SCALARDavid Hildenbrand3-9/+77
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-17-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE *David Hildenbrand3-12/+121
In addition to 32/128bit variants, we also have to support the "Signal-on-QNaN (SQ)" bit. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-16-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR (LOAD FP INTEGER|FP SQUARE ROOT)David Hildenbrand3-15/+109
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-15-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Implement 32/128 bit for VECTOR FP (ADD|DIVIDE|MULTIPLY|SUBTRACT)David Hildenbrand3-14/+153
In case of 128bit, we always have a single element. Add new helpers for reading/writing 32/128 bit floats. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-14-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Implement VECTOR MULTIPLY SUM LOGICALDavid Hildenbrand2-0/+52
Fortunately, we only need the Doubleword implementation. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-13-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Implement VECTOR BIT PERMUTEDavid Hildenbrand4-0/+33
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-12-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Simplify wfc64() handlingDavid Hildenbrand1-11/+12
... and prepare for 32/128 bit support. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-11-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Simplify vflr64() handlingDavid Hildenbrand3-25/+8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-10-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Simplify vfll32() handlingDavid Hildenbrand3-22/+6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-9-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Simplify vfma64() handlingDavid Hildenbrand3-32/+20
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-8-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Simplify vftci64() handlingDavid Hildenbrand3-24/+13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-7-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Simplify vfc64() handlingDavid Hildenbrand3-107/+38
Pass the m5 field via simd_data() and don't provide specialized handlers for single-element variants. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-6-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Simplify vop64_2() handlingDavid Hildenbrand3-156/+58
Let's rework our macros and simplify. We still need helper functions in most cases due to the different parameters types. Next, we'll only have 32/128bit variants for vfi and vfsq, so special case the others. Note that for vfsq, the XxC and erm passed in the simd_data() will never be set, resulting in the same behavior. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-5-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Simplify vop64_3() handlingDavid Hildenbrand3-79/+30
Let's simplify, reworking our handler generation, passing the whole "m5" register content and not providing specialized handlers for "se", and reading/writing proper float64 values using new helpers. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-4-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Fix instruction name for VECTOR FP LOAD (LENGTHENED|ROUNDED)David Hildenbrand1-2/+2
Let's use the correct name. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-3-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/tcg: Fix FP CONVERT TO (LOGICAL) FIXED NaN handlingDavid Hildenbrand2-6/+43
In case we encounter a NaN, we have to return the smallest possible number, corresponding to either 0 or the maximum negative number. This seems to differ from IEEE handling as implemented in softfloat, whereby we return the biggest possible number. While at it, use float32_to_uint64() in the CLGEB handler. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210608092337.12221-2-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-06-21s390x/kvm: remove unused gs handlingCornelia Huck3-15/+1
With commit 0280b3eb7c05 ("s390x/kvm: use cpu model for gscb on compat machines"), we removed any calls to kvm_s390_get_gs() in favour of a different mechanism. Let's remove the unused kvm_s390_get_gs(), and with it the now unneeded cap_gs as well. Signed-off-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210602125050.492500-1-cohuck@redhat.com>
2021-06-20linux-user: Use public sigev_notify_thread_id member if availableMichael Forney2-1/+21
_sigev_un._tid is an internal glibc field and is not available on musl libc. The sigevent(7) man page and Linux UAPI headers both use sigev_notify_thread_id as a public way to access this field. musl libc supports this field since 1.2.2[0], and glibc plans to add support as well[1][2]. If sigev_notify_thread_id is not available, fall back to _sigev_un._tid as before. [0] http://git.musl-libc.org/cgit/musl/commit/?id=7c71792e87691451f2a6b76348e83ad1889f1dcb [1] https://www.openwall.com/lists/musl/2019/08/01/5 [2] https://sourceware.org/bugzilla/show_bug.cgi?id=27417 Signed-off-by: Michael Forney <mforney@mforney.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210526035556.7931-1-mforney@mforney.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-06-20linux-user: Fix incorrect use of feature-test-macrosMichael Forney1-4/+3
The _POSIX_C_SOURCE and _XOPEN_SOURCE macros are used by the application to indicate to libc which declarations it should expose. Since qemu does not define them anywhere, it does not make sense to check their value. Instead, since the intent is to determine whether the host struct stat supports the st_*tim fields, use the configure test result which does exactly that. Signed-off-by: Michael Forney <mforney@mforney.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210526035531.7871-1-mforney@mforney.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-06-20linux-user: Check for ieee128 fpbits in PPC64 HWCAP2 feature listKhem Raj1-1/+1
glibc 2.34 is now checking for this in hwcaps at runtime [1] and failing to run the binary if machine does not support 128bit IEEE fp Fixes Fatal glibc error: CPU lacks float128 support (POWER 9 or later required) [1] https://sourceware.org/git/?p=glibc.git;a=commitdiff;h=d337345ce145e23c5f3a956f349d924fdf54ce2d;hp=eb24865637a271ab7dad13190330105eab0d478d Signed-off-by: Khem Raj <raj.khem@gmail.com> Cc: Florian Weimer <fweimer@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210614191729.2981488-1-raj.khem@gmail.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-06-20tests/tcg/linux-test: Check that sigaction can query SIGKILL/SIGSTOPIlya Leoshkevich1-0/+9
Verify that querying is allowed, but making changes isn't. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210601145600.3131040-3-iii@linux.ibm.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-06-20linux-user: Let sigaction query SIGKILL/SIGSTOPIlya Leoshkevich1-1/+5
The kernel allows doing this, so let's allow this in qemu as well. Valgrind relies on this. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210601145600.3131040-2-iii@linux.ibm.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-06-20linux-user: Implement pivot_rootYAMAMOTO Takashi1-0/+21
Used by runc. Signed-off-by: YAMAMOTO Takashi <yamamoto@midokura.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210531055019.10149-6-yamamoto@midokura.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-06-19util/oslib-win32: Fix fatal assertion in qemu_try_memalignStefan Weil1-1/+5
The function is called with alignment == 0 which caused an assertion. Use the code from oslib-posix.c to fix that regression. Fixes: ed6f53f9ca9 Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210611105846.347954-1-sw@weilnetz.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-19tcg: expose TCGCond manipulation routinesAlessandro Di Federico2-69/+102
This commit moves into a separate file routines used to manipulate TCGCond. These will be employed by the idef-parser. Signed-off-by: Alessandro Di Federico <ale@rev.ng> Signed-off-by: Paolo Montesel <babush@rev.ng> Message-Id: <20210619093713.1845446-2-ale.qemu@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-19tcg: Restart when exhausting the stack frameRichard Henderson1-1/+5
Assume that we'll have fewer temps allocated after restarting with a fewer number of instructions. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-19tcg: Allocate sufficient storage in temp_allocate_frameRichard Henderson1-5/+26
This function should have been updated for vector types when they were introduced. Fixes: d2fd745fe8b Resolves: https://gitlab.com/qemu-project/qemu/-/issues/367 Cc: qemu-stable@nongnu.org Tested-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-19tcg/sparc: Fix temp_allocate_frame vs sparc stack biasRichard Henderson2-12/+13
We should not be aligning the offset in temp_allocate_frame, because the odd offset produces an aligned address in the end. Instead, pass the logical offset into tcg_set_frame and add the stack bias last. Cc: qemu-stable@nongnu.org Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-19accel/tcg: Probe the proper permissions for atomic opsRichard Henderson3-44/+83
We had a single ATOMIC_MMU_LOOKUP macro that probed for read+write on all atomic ops. This is incorrect for plain atomic load and atomic store. For user-only, we rely on the host page permissions. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/390 Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-19tests/tcg: Increase timeout for TCIRichard Henderson2-2/+7
The longest test at the moment seems to be a (slower) aarch64 host, for which test-mmap takes 64 seconds. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>