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2023-08-28configure: switch to ensuregroupPaolo Bonzini2-10/+12
Using the new ensuregroup command, the desired versions of meson and sphinx can be placed in pythondeps.toml rather than configure. The meson.install entry in pythondeps.toml matches the version that is found in python/wheels. This ensures that mkvenv.py uses the bundled wheel even if PyPI is enabled; thus not introducing warnings or errors from versions that are more recent than the one used in CI. The sphinx entries match what is shipped in Fedora 38. It's the last release that has support for older versions of Python (sphinx 6.0 requires Python 3.8) and especially docutils (of which sphinx 6.0 requires version 0.18). This is important because Ubuntu 20.04 has docutils 0.14 and Debian 11 has docutils 0.16. "mkvenv.py ensure" is only used to bootstrap tomli. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-08-28python: use vendored tomliPaolo Bonzini3-1/+10
Debian only introduced tomli in the bookworm release. Use a vendored wheel to avoid requiring a package that is only in bullseye-backports and is also absent in Ubuntu 20.04. While at it, fix an issue in the vendor.py scripts which does not add a newline after each package and hash. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-08-28configure: never use PyPI for MesonPaolo Bonzini1-6/+0
Since there is a vendored copy, there is no point in choosing online operation. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-08-28lcitool: bump libvirt-ci submodule and regeneratePaolo Bonzini16-31/+31
This brings in a newer version of the pipewire mapping, so rename it. Python 3.9 and 3.10 do not seem to work in OpenSUSE LEAP 15.5 (weird, because 3.9 persisted from 15.3 to 15.4) so bump the Python runtime version to 3.11. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-08-28python: mkvenv: add ensuregroup commandPaolo Bonzini3-1/+148
Introduce a new subcommand that retrieves the packages to be installed from a TOML file. This allows being more flexible in using the system version of a package, while at the same time using a known-good version when installing the package. This is important for packages that sometimes have backwards-incompatible changes or that depend on specific versions of their dependencies. Compared to JSON, TOML is more human readable and easier to edit. A parser is available in 3.11 but also available as a small (12k) package for older versions, tomli. While tomli is bundled with pip, this is only true of recent versions of pip. Of all the supported OSes pretty much only FreeBSD has a recent enough version of pip while staying on Python <3.11. So we cannot use the same trick that is in place for distlib. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-08-28python: mkvenv: introduce TOML-like representation of dependenciesPaolo Bonzini1-16/+61
We would like to place all Python dependencies in the same file, so that we can add more information without having long and complex command lines. The plan is to have a TOML file with one entry per package, for example [avocado] avocado-framework = { accepted = "(>=88.1, <93.0)", installed = "88.1", canary = "avocado" } Each TOML section will thus be a dictionary of dictionaries. Modify mkvenv.py's workhorse function, _do_ensure, to already operate on such a data structure. The "ensure" subcommand is modified to separate the depspec into a name and a version part, and use the result (plus the --diagnose argument) to build a dictionary for each command line argument. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-08-28python: mkvenv: tweak the matching of --diagnose to depspecsPaolo Bonzini1-1/+4
Move the matching between the "absent" array and dep_specs[0] inside the loop, preparing for the possibility of having multiple canaries among the installed packages. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-08-28dockerfiles: bump tricore cross compiler container to Debian 11Paolo Bonzini1-1/+1
With the release of version 12 on June 10, 2023, Debian 10 is not supported anymore. Modify the cross compiler container to build on a newer version. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-08-28configure: fix and complete detection of tricore toolsPaolo Bonzini1-4/+1
The tricore tools are not detected when they are installed in the host system, only if they are taken from an external container. For this reason the build-tricore-softmmu job was not running the TCG tests. In addition the container provides all tools, not just as/ld/gcc, so there is no need to special case tricore. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-08-24hw/loongarch: Fix ACPI processor id off-by-one errorJiajie Chen1-1/+1
In hw/acpi/aml-build.c:build_pptt() function, the code assumes that the ACPI processor id equals to the cpu index, for example if we have 8 cpus, then the ACPI processor id should be in range 0-7. However, in hw/loongarch/acpi-build.c:build_madt() function we broke the assumption. If we have 8 cpus again, the ACPI processor id in MADT table would be in range 1-8. It violates the following description taken from ACPI spec 6.4 table 5.138: If the processor structure represents an actual processor, this field must match the value of ACPI processor ID field in the processor’s entry in the MADT. It will break the latest Linux 6.5-rc6 with the following error message: ACPI PPTT: PPTT table found, but unable to locate core 7 (8) Invalid BIOS PPTT Here 7 is the last cpu index, 8 is the ACPI processor id learned from MADT. With this patch, Linux can properly detect SMT threads when "-smp 8,sockets=1,cores=4,threads=2" is passed: Thread(s) per core: 2 Core(s) per socket: 2 Socket(s): 2 The detection of number of sockets is still wrong, but that is out of scope of the commit. Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Bibo Mao <maobibo@loongson.cn> Message-Id: <20230820105658.99123-2-c@jia.je> Signed-off-by: Song Gao <gaosong@loongson.cn>
2023-08-24target/loongarch: Split fcc register to fcc0-7 in gdbstubJiajie Chen2-10/+15
Since GDB 13.1(GDB commit ea3352172), GDB LoongArch changed to use fcc0-7 instead of fcc register. This commit partially reverts commit 2f149c759 (`target/loongarch: Update gdb_set_fpu() and gdb_get_fpu()`) to match the behavior of GDB. Note that it is a breaking change for GDB 13.0 or earlier, but it is also required for GDB 13.1 or later to work. Signed-off-by: Jiajie Chen <c@jia.je> Acked-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230808054315.3391465-1-c@jia.je> Signed-off-by: Song Gao <gaosong@loongson.cn>
2023-08-24hw/intc/loongarch_pch: fix edge triggered irq handlingBibo Mao1-1/+6
For edge triggered irq, qemu_irq_pulse is used to inject irq. It will set irq with high level and low level soon to simluate pulse irq. For edge triggered irq, irq is injected and set as pending at rising level, do not clear irq at lowering level. LoongArch pch interrupt will clear irq for lowering level irq, there will be problem. ACPI ged deivce is edge-triggered irq, it is used for cpu/memory hotplug. This patch fixes memory hotplug issue on LoongArch virt machine. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230707091557.1474790-1-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2023-08-24target/loongarch: cpu: Implement get_arch_id callbackBibo Mao3-0/+11
Implement the callback for getting the architecture-dependent CPU ID, the cpu ID is physical id described in ACPI MADT table, this will be used for cpu hotplug. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230824005007.2000525-1-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2023-08-24target/loongarch: Add avail_IOCSR to check iocsr instructionsSong Gao2-9/+9
Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20230822032724.1353391-16-gaosong@loongson.cn> Message-Id: <20230822072219.35719-1-philmd@linaro.org>
2023-08-24target/loongarch: Add avail_LSX to check LSX instructionsSong Gao2-661/+823
Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20230822032724.1353391-15-gaosong@loongson.cn> Message-Id: <20230822073026.35776-1-philmd@linaro.org>
2023-08-24target/loongarch: Add avail_LAM to check atomic instructionsSong Gao2-36/+37
Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20230822032724.1353391-14-gaosong@loongson.cn> Message-Id: <20230822071959.35620-8-philmd@linaro.org>
2023-08-24target/loongarch: Add avail_LSPW to check LSPW instructionsSong Gao2-0/+9
Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20230822032724.1353391-13-gaosong@loongson.cn> Message-Id: <20230822071959.35620-7-philmd@linaro.org>
2023-08-24target/loongarch: Add avail_FP/FP_SP/FP_DP to check fpu instructionsSong Gao7-86/+159
Signed-off-by: Song Gao <gaosong@loongson.cn> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20230822032724.1353391-12-gaosong@loongson.cn> Message-Id: <20230822071959.35620-6-philmd@linaro.org>
2023-08-24hw/loongarch: Remove restriction of la464 cores in the virt machineSong Gao1-5/+0
Allow virt machine to be used with la132 instead of la464. Co-authored-by: Jiajie Chen <c@jia.je> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230822032724.1353391-11-gaosong@loongson.cn> Message-Id: <20230822071959.35620-5-philmd@linaro.org>
2023-08-24target/loongarch: Add LoongArch32 cpu la132Jiajie Chen1-0/+30
Add LoongArch32 cpu la132. Due to lack of public documentation of la132, it is currently a synthetic LoongArch32 cpu model. Details need to be added in the future. Signed-off-by: Jiajie Chen <c@jia.je> Signed-off-by: Song Gao <gaosong@loongson.cn> Acked-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230822032724.1353391-10-gaosong@loongson.cn> Message-Id: <20230822071959.35620-4-philmd@linaro.org>
2023-08-24target/loongarch: Add avail_64 to check la64-only instructionsSong Gao10-123/+152
The la32 instructions listed in Table 2 at https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#overview-of-basic-integer-instructions Co-authored-by: Jiajie Chen <c@jia.je> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20230822032724.1353391-9-gaosong@loongson.cn> Message-Id: <20230822071959.35620-3-philmd@linaro.org>
2023-08-24target/loongarch: Add a check parameter to the TRANS macroSong Gao14-944/+946
The default check parmeter is ALL. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20230822032724.1353391-8-gaosong@loongson.cn> Message-Id: <20230822071959.35620-2-philmd@linaro.org>
2023-08-24target/loongarch: Sign extend results in VA32 modeJiajie Chen1-0/+3
In VA32 mode, BL, JIRL and PC* instructions should sign-extend the low 32 bit result to 64 bits. Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230822032724.1353391-7-gaosong@loongson.cn> Message-Id: <20230822071959.35620-1-philmd@linaro.org>
2023-08-24target/loongarch: Truncate high 32 bits of address in VA32 modeJiajie Chen2-2/+20
When running in VA32 mode(!LA64 or VA32L[1-3] matching PLV), virtual address is truncated to 32 bits before address mapping. Signed-off-by: Jiajie Chen <c@jia.je> Co-authored-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230822032724.1353391-6-gaosong@loongson.cn> Message-Id: <20230822071405.35386-10-philmd@linaro.org>
2023-08-24target/loongarch: Extract set_pc() helperJiajie Chen4-11/+16
Signed-off-by: Jiajie Chen <c@jia.je> Co-authored-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230822032724.1353391-6-gaosong@loongson.cn> [PMD: Extract helper from bigger patch] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230822071405.35386-9-philmd@linaro.org>
2023-08-24target/loongarch: Extract make_address_pc() helperJiajie Chen3-3/+8
Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230822032724.1353391-7-gaosong@loongson.cn> [PMD: Extract helper from bigger patch] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230822071405.35386-8-philmd@linaro.org>
2023-08-24target/loongarch: Extract make_address_i() helperJiajie Chen6-57/+29
Signed-off-by: Jiajie Chen <c@jia.je> Co-authored-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230822032724.1353391-6-gaosong@loongson.cn> [PMD: Extract helper from bigger patch] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230822071405.35386-7-philmd@linaro.org>
2023-08-24target/loongarch: Extract make_address_x() helperJiajie Chen4-20/+22
Signed-off-by: Jiajie Chen <c@jia.je> Co-authored-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230822032724.1353391-6-gaosong@loongson.cn> [PMD: Extract helper from bigger patch] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230822071405.35386-6-philmd@linaro.org>
2023-08-24target/loongarch: Add LA64 & VA32 to DisasContextJiajie Chen3-0/+18
Add LA64 and VA32(32-bit Virtual Address) to DisasContext to allow the translator to reject doubleword instructions in LA32 mode for example. Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-ID: <20230822032724.1353391-5-gaosong@loongson.cn> Message-Id: <20230822071405.35386-5-philmd@linaro.org>
2023-08-24target/loongarch: Support LoongArch32 VPPNJiajie Chen2-7/+22
VPPN of TLBEHI/TLBREHI is limited to 19 bits in LA32. Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-ID: <20230822032724.1353391-4-gaosong@loongson.cn> Message-Id: <20230822071405.35386-4-philmd@linaro.org>
2023-08-24target/loongarch: Support LoongArch32 DMWJiajie Chen2-7/+26
LA32 uses a different encoding for CSR.DMW and a new direct mapping mechanism. Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-ID: <20230822032724.1353391-3-gaosong@loongson.cn> Message-Id: <20230822071405.35386-3-philmd@linaro.org>
2023-08-24target/loongarch: Support LoongArch32 TLB entryJiajie Chen2-9/+17
The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to zero in LoongArch32. Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-ID: <20230822032724.1353391-2-gaosong@loongson.cn> Message-Id: <20230822071405.35386-2-philmd@linaro.org>
2023-08-24target/loongarch: Add GDB support for loongarch32 modeJiajie Chen4-8/+81
GPRs and PC are 32-bit wide in loongarch32 mode. Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-ID: <20230817093121.1053890-4-gaosong@loongson.cn> [PMD: Rebased, set gdb_num_core_regs] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230821125959.28666-9-philmd@linaro.org>
2023-08-24target/loongarch: Add new object class for loongarch32 cpusJiajie Chen2-0/+12
Add object class stub for future loongarch32 cpus. Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-ID: <20230817093121.1053890-3-gaosong@loongson.cn> [Rebased on TYPE_LOONGARCH64_CPU introduction] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230821125959.28666-8-philmd@linaro.org>
2023-08-24target/loongarch: Add function to check current archJiajie Chen1-0/+10
Add is_la64 function to check if the current cpucfg[1].arch equals to 2(LA64). Signed-off-by: Jiajie Chen <c@jia.je> Co-authored-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-ID: <20230817093121.1053890-2-gaosong@loongson.cn> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230821125959.28666-7-philmd@linaro.org>
2023-08-24target/loongarch: Extract 64-bit specifics to loongarch64_cpu_class_initPhilippe Mathieu-Daudé1-8/+15
Extract loongarch64 specific code from loongarch_cpu_class_init() to a new loongarch64_cpu_class_init(). In preparation of supporting loongarch32 cores, rename these functions using the '64' suffix. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230821125959.28666-6-philmd@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
2023-08-24target/loongarch: Introduce abstract TYPE_LOONGARCH64_CPUPhilippe Mathieu-Daudé2-3/+10
In preparation of introducing TYPE_LOONGARCH32_CPU, introduce an abstract TYPE_LOONGARCH64_CPU. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230821125959.28666-5-philmd@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
2023-08-24target/loongarch: Fix loongarch_la464_initfn() misses setting LSPWSong Gao1-0/+1
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230817093121.1053890-11-gaosong@loongson.cn> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230821125959.28666-4-philmd@linaro.org>
2023-08-24target/loongarch: Remove duplicated disas_set_info assignmentPhilippe Mathieu-Daudé1-1/+0
Commit 228021f05e ("target/loongarch: Add core definition") sets disas_set_info to loongarch_cpu_disas_set_info. Probably due to a failed git-rebase, commit ca61e75071 ("target/loongarch: Add gdb support") also sets it to the same value. Remove the duplication. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230821125959.28666-3-philmd@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
2023-08-24target/loongarch: Log I/O write accesses to CSR registersPhilippe Mathieu-Daudé1-0/+2
Various CSR registers have Read/Write fields. We might want to see guest trying to change such registers. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230821125959.28666-2-philmd@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
2023-08-23docs/about/license: Update LICENSE URLPhilippe Mathieu-Daudé1-1/+1
In early 2021 (see commit 2ad784339e "docs: update README to use GitLab repo URLs") almost all of the code base was converted to point to GitLab instead of git.qemu.org. During 2023, git.qemu.org switched from a git mirror to a http redirect to GitLab (see [1]). Update the LICENSE URL to match its previous content, displaying the file raw content similarly to gitweb 'blob_plain' format ([2]). [1] https://lore.kernel.org/qemu-devel/CABgObfZu3mFc8tM20K-yXdt7F-7eV-uKZN4sKDarSeu7DYoRbA@mail.gmail.com/ [2] https://git-scm.com/docs/gitweb#Documentation/gitweb.txt-blobplain Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-ID: <20230822125716.55295-1-philmd@linaro.org>
2023-08-23tests/tcg/s390x: Test VSTRSIlya Leoshkevich2-0/+89
Add a small test to prevent regressions. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20230804233748.218935-4-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-08-23target/s390x: Fix the "ignored match" case in VSTRSIlya Leoshkevich1-37/+17
Currently the emulation of VSTRS recognizes partial matches in presence of \0 in the haystack, which, according to PoP, is not correct: If the ZS flag is one and a zero byte was detected in the second operand, then there can not be a partial match ... Add a check for this. While at it, fold a number of explicitly handled special cases into the generic logic. Cc: qemu-stable@nongnu.org Reported-by: Claudio Fontana <cfontana@suse.de> Closes: https://lists.gnu.org/archive/html/qemu-devel/2023-08/msg00633.html Fixes: 1d706f314191 ("target/s390x: vxeh2: vector string search") Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20230804233748.218935-3-iii@linux.ibm.com> Tested-by: Claudio Fontana <cfontana@suse.de> Acked-by: David Hildenbrand <david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-08-23linux-user/elfload: Enable vxe2 on s390xIlya Leoshkevich1-0/+1
The vxe2 hwcap is not set for programs running in linux-user, but is set by a Linux kernel running in softmmu. Add it to the former. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20230804233748.218935-2-iii@linux.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-08-23include/hw/virtio/virtio-gpu: Fix virtio-gpu with blob on big endian hostsThomas Huth1-0/+3
Using "-device virtio-gpu,blob=true" currently does not work on big endian hosts (like s390x). The guest kernel prints an error message like: [drm:virtio_gpu_dequeue_ctrl_func [virtio_gpu]] *ERROR* response 0x1200 (command 0x10c) and the display stays black. When running QEMU with "-d guest_errors", it shows an error message like this: virtio_gpu_create_mapping_iov: nr_entries is too big (83886080 > 16384) which indicates that this value has not been properly byte-swapped. And indeed, the virtio_gpu_create_blob_bswap() function (that should swap the fields in the related structure) fails to swap some of the entries. After correctly swapping all missing values here, too, the virtio-gpu device is now also working with blob=true on s390x hosts. Fixes: e0933d91b1 ("virtio-gpu: Add virtio_gpu_resource_create_blob") Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=2230469 Message-Id: <20230815122007.928049-1-thuth@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-08-23hw/s390x/s390-virtio-ccw: Remove superfluous code to set the NIC modelThomas Huth1-4/+0
The check for nd->model being NULL was originally required, but in commit e11f463295d95aba ("s390x/virtio: use qemu_check_nic_model()") the corresponding code had been replaced by a call to the function qemu_check_nic_model() - and this in turn calls qemu_find_nic_model() which contains the same check for nd->model being NULL again. So we can remove this from the calling site now. Message-Id: <20230804073525.11857-1-thuth@redhat.com> Reviewed-by: Halil Pasic <pasic@linux.ibm.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-08-23tests/tcg/s390x: Test VREPIlya Leoshkevich2-0/+82
Add a small test to prevent regressions. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20230807163459.849766-2-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-08-23target/s390x: Use a 16-bit immediate in VREPIlya Leoshkevich1-2/+2
Unlike most other instructions that contain an immediate element index, VREP's one is 16-bit, and not 4-bit. The code uses only 8 bits, so using, e.g., 0x101 does not lead to a specification exception. Fix by checking all 16 bits. Cc: qemu-stable@nongnu.org Fixes: 28d08731b1d8 ("s390x/tcg: Implement VECTOR REPLICATE") Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20230807163459.849766-1-iii@linux.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-08-23tests/tcg/s390x: Test VSTLIlya Leoshkevich2-0/+38
Add a small test to prevent regressions. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20230804235624.263260-2-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-08-23target/s390x: Fix VSTL with a large lengthIlya Leoshkevich1-1/+1
The length is always truncated to 16 bytes. Do not probe more than that. Cc: qemu-stable@nongnu.org Fixes: 0e0a5b49ad58 ("s390x/tcg: Implement VECTOR STORE WITH LENGTH") Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20230804235624.263260-1-iii@linux.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>