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2022-03-07hw/intc/arm_gicv3: Specify valid and impl in MemoryRegionOpsPeter Maydell1-0/+8
The GICv3 has some registers that support byte accesses, and some that support 8-byte accesses. Our TCG implementation implements all of this, switching on the 'size' argument and handling the registers that must support reads of that size while logging an error for attempted accesses to registers that do not support that size access. However we forgot to tell the core memory subsystem about this by specifying the .impl and .valid fields in the MemoryRegionOps struct, so the core was happily simulating 8 byte accesses by combining two 4 byte accesses. This doesn't have much guest-visible effect, since there aren't many 8 byte registers and they all support being written in two 4 byte parts. Set the .impl and .valid fields to say that all sizes from 1 to 8 bytes are both valid and implemented by the device. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220303202341.2232284-4-peter.maydell@linaro.org
2022-03-07hw/intc/arm_gicv3_its: Add trace events for table reads and writesPeter Maydell2-6/+40
For debugging guest use of the ITS, it can be helpful to trace when the ITS reads and writes the in-memory tables. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220303202341.2232284-3-peter.maydell@linaro.org
2022-03-07hw/intc/arm_gicv3_its: Add trace events for commandsPeter Maydell2-2/+38
When debugging code that's using the ITS, it's helpful to see tracing of the ITS commands that the guest executes. Add suitable trace events. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220303202341.2232284-2-peter.maydell@linaro.org
2022-03-07target/arm/translate-neon: Simplify align field check for VLD3Peter Maydell1-5/+5
For VLD3 (single 3-element structure to one lane), there is no alignment specification and the alignment bits in the instruction must be zero. This is bit [4] for the size=0 and size=1 cases, and bits [5:4] for the size=2 case. We do this check correctly in VLDST_single(), but we write it a bit oddly: in the 'case 3' code we check for bit 0 of a->align (bit [4] of the insn), and then we fall through to the 'case 2' code which checks bit 1 of a->align (bit [5] of the insn) in the size 2 case. Replace this with just checking "is a->align non-zero" for VLD3, which lets us drop the fall-through and put the cases in this switch in numerical order. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220303113741.2156877-3-peter.maydell@linaro.org
2022-03-07target/arm/translate-neon: UNDEF if VLD1/VST1 stride bits are non-zeroPeter Maydell1-0/+3
For VLD1/VST1 (single element to one lane) we are only accessing one register, and so the 'stride' is meaningless. The bits that would specify stride (insn bit [4] for size=1, bit [6] for size=2) are specified to be zero in the encoding (which would correspond to a stride of 1 for VLD2/VLD3/VLD4 etc), and we must UNDEF if they are not. We failed to make this check, which meant that we would incorrectly handle some instruction patterns as loads or stores instead of UNDEFing them. Enforce that stride == 1 for the nregs == 1 case. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/890 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220303113741.2156877-2-peter.maydell@linaro.org
2022-03-07osdep: Move memalign-related functions to their own headerPeter Maydell53-20/+112
Move the various memalign-related functions out of osdep.h and into their own header, which we include only where they are used. While we're doing this, add some brief documentation comments. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20220226180723.1706285-10-peter.maydell@linaro.org
2022-03-07util: Put qemu_vfree() in memalign.cPeter Maydell3-12/+11
qemu_vfree() is the companion free function to qemu_memalign(); put it in memalign.c so the allocation and free functions are together. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220226180723.1706285-9-peter.maydell@linaro.org Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-03-07util: Use meson checks for valloc() and memalign() presencePeter Maydell2-2/+6
Instead of assuming that all CONFIG_BSD have valloc() and anything else is memalign(), explicitly check for those functions in meson.build and use the "is the function present" define. Tests for specific functionality are better than which-OS checks; this also lets us give a helpful error message if somehow there's no usable function present. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20220226180723.1706285-8-peter.maydell@linaro.org
2022-03-07util: Share qemu_try_memalign() implementation between POSIX and WindowsPeter Maydell4-46/+40
The qemu_try_memalign() functions for POSIX and Windows used to be significantly different, but these days they are identical except for the actual allocation function called, and the POSIX version already has to have ifdeffery for different allocation functions. Move to a single implementation in memalign.c, which uses the Windows _aligned_malloc if we detect that function in meson. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220226180723.1706285-7-peter.maydell@linaro.org Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-03-07meson.build: Don't misdetect posix_memalign() on WindowsPeter Maydell1-1/+3
Currently we incorrectly think that posix_memalign() exists on Windows. This is because of a combination of: * the msys2/mingw toolchain/libc claim to have a __builtin_posix_memalign when there isn't a builtin of that name * meson will assume that if you have a __builtin_foo that counts for has_function('foo') Specifying a specific include file via prefix: causes meson to not treat builtins as sufficient and actually look for the function itself; see this meson pull request which added that as the official way to get the right answer: https://github.com/mesonbuild/meson/pull/1150 Currently this misdectection doesn't cause problems because we only use CONFIG_POSIX_MEMALIGN in oslib-posix.c; however that will change in a following commit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220226180723.1706285-6-peter.maydell@linaro.org Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-03-07util: Return valid allocation for qemu_try_memalign() with zero sizePeter Maydell2-1/+6
Currently qemu_try_memalign()'s behaviour if asked to allocate 0 bytes is rather variable: * on Windows, we will assert * on POSIX platforms, we get the underlying behaviour of the posix_memalign() or equivalent function, which may be either "return a valid non-NULL pointer" or "return NULL" Explictly check for 0 byte allocations, so we get consistent behaviour across platforms. We handle them by incrementing the size so that we return a valid non-NULL pointer that can later be passed to qemu_vfree(). This is permitted behaviour for the posix_memalign() API and is the most usual way that underlying malloc() etc implementations handle a zero-sized allocation request, because it won't trip up calling code that assumes NULL means an error. (This includes our own qemu_memalign(), which will abort on NULL.) This change is a preparation for sharing the qemu_try_memalign() code between Windows and POSIX. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-03-07util: Unify implementations of qemu_memalign()Peter Maydell4-28/+40
We implement qemu_memalign() in both oslib-posix.c and oslib-win32.c, but the two versions are essentially the same: they call qemu_try_memalign(), and abort() after printing an error message if it fails. The only difference is that the win32 version prints the GetLastError() value whereas the POSIX version prints strerror(errno). However, this is a bug in the win32 version: in commit dfbd0b873a85021 in 2020 we changed the implementation of qemu_try_memalign() from using VirtualAlloc() (which sets the GetLastError() value) to using _aligned_malloc() (which sets errno), but didn't update the error message to match. Replace the two separate functions with a single version in a new memalign.c file, which drops the unnecessary extra qemu_oom_check() function and instead prints a more useful message including the requested size and alignment as well as the errno string. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220226180723.1706285-4-peter.maydell@linaro.org Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-03-07util: Make qemu_oom_check() a static functionPeter Maydell3-4/+2
The qemu_oom_check() function, which we define in both oslib-posix.c and oslib-win32.c, is now used only locally in that file; make it static. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20220226180723.1706285-3-peter.maydell@linaro.org
2022-03-05target/ppc: Add missing helper_reset_fpstatus to helper_XVCVSPBF16Víctor Colombo1-0/+2
Fixes: 3909ff1fac ("target/ppc: Implement xvcvbf16spn and xvcvspbf16 instructions") Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220304175156.2012315-8-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-05target/ppc: Add missing helper_reset_fpstatus to VSX_MAX_MINCVíctor Colombo1-0/+2
Fixes: da499405aa ("target/ppc: Refactor VSX_MAX_MINC helper") Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220304175156.2012315-7-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-05target/ppc: split XXGENPCV macros for readabilityMatheus Ferst2-42/+57
Fixes: b090f4f1e3c9 ("target/ppc: Implement xxgenpcv[bhwd]m instruction") Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220304175156.2012315-6-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-05target/ppc: use andc in vrlqmiMatheus Ferst1-4/+2
Fixes: 7e5947df6e94 ("target/ppc: implement vrlqmi") Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220304175156.2012315-5-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-05target/ppc: use extract/extract2 to create vrlqnm maskMatheus Ferst1-7/+3
Fixes: 4e272668406b ("target/ppc: implement vrlqnm") Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220304175156.2012315-4-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-05target/ppc: use ext32u and deposit in do_vx_vmulhw_i64Matheus Ferst1-7/+3
Fixes: 29e9dfcf755e ("target/ppc: vmulh* instructions without helpers") Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220304175156.2012315-3-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-05target/ppc: Fix vmul[eo]* instructions marked 2.07Lucas Mateus Castro (alqotel)1-8/+8
Some ISA v2.03 Vector Multiply instructions marked to be ISA v2.07 only. This patch fixes it. Fixes: 80eca687c851 ("target/ppc: moved vector even and odd multiplication to decodetree") Reported-by: Howard Spoelstra <hsp.cat7@gmail.com> Suggested-by: Fabiano Rosas <farosas@linux.ibm.com> Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220304175156.2012315-2-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-05tests/tcg/ppc64le: Use Altivec register names in clobber listMatheus Ferst1-8/+8
LLVM/Clang doesn't know the VSX registers when compiling with -mabi=elfv1. Use only registers >= 32 and list them with their Altivec name. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220304165417.1981159-6-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-05tests/tcg/ppc64le: emit bcdsub with .long when neededMatheus Ferst1-31/+42
Based on GCC docs[1], we use the '-mpower8-vector' flag at config-time to detect the toolchain support to the bcdsub instruction. LLVM/Clang supports this flag since version 3.6[2], but the instruction and related builtins were only added in LLVM 14[3]. In the absence of other means to detect this support at config-time, we resort to __has_builtin to identify the presence of __builtin_bcdsub at compile-time. If the builtin is not available, the instruction is emitted with a ".long". [1] https://gcc.gnu.org/onlinedocs/gcc-8.3.0/gcc/PowerPC-AltiVec_002fVSX-Built-in-Functions.html [2] https://github.com/llvm/llvm-project/commit/59eb767e11d4ffefb5f55409524e5c8416b2b0db [3] https://github.com/llvm/llvm-project/commit/c933c2eb334660c131f4afc9d194fafb0cec0423 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220304165417.1981159-5-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-05tests/tcg/ppc64le: drop __int128 usage in bcdsubMatheus Ferst1-68/+61
Using __int128 with inline asm constraints like "v" generates incorrect code when compiling with LLVM/Clang (e.g., only one doubleword of the VSR is loaded). Instead, use a GPR pair to pass the 128-bits value and load the VSR with mtvsrd/xxmrghd. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220304165417.1981159-4-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-05target/ppc: change xs[n]madd[am]sp to use float64r32_muladdMatheus Ferst1-38/+20
Change VSX Scalar Multiply-Add/Subtract Type-A/M Single Precision helpers to use float64r32_muladd. This method should correctly handle all rounding modes, so the workaround for float_round_nearest_even can be dropped. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220304165417.1981159-3-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-05tests/tcg/ppc64le: use inline asm instead of __builtin_mtfsfMatheus Ferst1-10/+9
LLVM/Clang does not support __builtin_mtfsf. Acked-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220304165417.1981159-2-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-05Use long endian options for ppc64Miroslav Rezanina2-4/+4
GCC options pairs -mlittle/-mlittle-endian and -mbig/-mbig-endian are equivalent on ppc64 architecture. However, Clang supports only long version of the options. Use longer form in configure to properly support both GCC and Clang compiler. In addition, fix this issue in tcg test configure. Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Message-Id: <20220131091714.4825-1-mrezanin@redhat.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-04tcg/i386: Implement bitsel for avx512Richard Henderson2-2/+20
The general ternary logic operation can implement BITSEL. Funnel the 4-operand operation into three variants of the 3-operand instruction, depending on input operand overlap. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg/i386: Implement more logical operations for avx512Richard Henderson2-5/+39
AVX512VL has a general ternary logic operation, VPTERNLOGQ, which can implement NOT, ORC, NAND, NOR, EQV. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg/i386: Implement avx512 multiplyRichard Henderson1-6/+6
AVX512DQ has VPMULLQ. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg/i386: Implement avx512 min/max/absRichard Henderson1-7/+11
AVX512VL has VPABSQ, VPMAXSQ, VPMAXUQ, VPMINSQ, VPMINUQ. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg/i386: Expand scalar rotate with avx512 insnsRichard Henderson1-20/+29
Expand 32-bit and 64-bit scalar rotate with VPRO[LR]V; expand 16-bit scalar rotate with VPSHLDV. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg/i386: Remove rotls_vec from tcg_target_op_defRichard Henderson1-1/+0
There is no such instruction on x86, so we should not be pretending it has arguments. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg/i386: Expand vector word rotate as avx512vbmi2 shift-doubleRichard Henderson1-1/+17
While there are no specific 16-bit rotate instructions, there are double-word shifts, which can perform the same operation. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg/i386: Support avx512vbmi2 vector shift-double instructionsRichard Henderson3-0/+42
We will use VPSHLD, VPSHLDV and VPSHRDV for 16-bit rotates. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg/i386: Implement avx512 variable rotateRichard Henderson2-2/+25
AVX512VL has VPROLVD and VPRORVQ. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg/i386: Implement avx512 immediate rotateRichard Henderson2-3/+14
AVX512VL has VPROLD and VPROLQ, layered onto the same opcode as PSHIFTD, but requires EVEX encoding and W1. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg/i386: Implement avx512 immediate sari shiftRichard Henderson1-9/+21
AVX512 has VPSRAQ with immediate operand, in the same form as with AVX, but requires EVEX encoding and W1. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg/i386: Implement avx512 scalar shiftRichard Henderson1-2/+10
AVX512VL has VPSRAQ. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg/i386: Implement avx512 variable shiftsRichard Henderson1-8/+24
AVX512VL has VPSRAVQ, and AVX512BW has VPSLLVW, VPSRAVW, VPSRLVW. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg/i386: Use tcg_can_emit_vec_op in expand_vec_cmp_noinvRichard Henderson1-4/+4
The condition for UMIN/UMAX availability is about to change; use the canonical version. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg/i386: Add tcg_out_evex_opcRichard Henderson1-1/+50
The evex encoding is added here, for use in a subsequent patch. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg/i386: Detect AVX512Richard Henderson3-5/+43
There are some operation sizes in some subsets of AVX512 that are missing from previous iterations of AVX. Detect them. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg/s390x: Implement vector NAND, NOR, EQVRichard Henderson2-3/+20
Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg/ppc: Implement vector NAND, NOR, EQVRichard Henderson2-3/+18
Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg: Add opcodes for vector nand, nor, eqvRichard Henderson10-15/+51
We've had placeholders for these opcodes for a while, and should have support on ppc, s390x and avx512 hosts. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg: Set MAX_OPC_PARAM_IARGS to 7Ziqiao Kong2-2/+2
The last entry of DEF_HELPERS_FLAGS_n is DEF_HELPER_FLAGS_7 and thus the MAX_OPC_PARAM_IARGS should be 7. Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Ziqiao Kong <ziqiaokong@gmail.com> Message-Id: <20220227113127.414533-2-ziqiaokong@gmail.com> Fixes: e6cadf49c3d ("tcg: Add support for a helper with 7 arguments") Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg/optimize: only read val after const checkAlex Bennée1-4/+4
valgrind pointed out that arg_info()->val can be undefined which will be the case if the arguments are not constant. The ordering of the checks will have ensured we never relied on an undefined value but for the sake of completeness re-order the code to be clear. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20220209112142.3367525-1-alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04block/amend: Keep strong reference to BDSHanna Reitz1-0/+3
Otherwise, the BDS might be freed while the job is running, which would cause a use-after-free. Signed-off-by: Hanna Reitz <hreitz@redhat.com> Message-Id: <20220304153729.711387-5-hreitz@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2022-03-04block/amend: Always call .bdrv_amend_clean()Hanna Reitz1-2/+2
.bdrv_amend_clean() says block drivers can use it to clean up what was done in .bdrv_amend_pre_run(). Therefore, it should always be called after .bdrv_amend_pre_run(), which means we need it to call it in the JobDriver.free() callback, not in JobDriver.clean(). Signed-off-by: Hanna Reitz <hreitz@redhat.com> Message-Id: <20220304153729.711387-3-hreitz@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2022-03-04tests/qemu-iotests: Rework the checks and spots using GNU sedThomas Huth4-67/+57
Instead of failing the iotests if GNU sed is not available (or skipping them completely in the check-block.sh script), it would be better to simply skip the bash-based tests that rely on GNU sed, so that the other tests could still be run. Thus we now explicitely use "gsed" (either as direct program or as a wrapper around "sed" if it's the GNU version) in the spots that rely on the GNU sed behavior. Statements that use the "-r" parameter of sed have been switched to use "-E" instead, since this switch is supported by all sed versions on our supported build hosts (most also support "-r", but macOS' sed only supports "-E"). With all these changes in place, we then can also remove the sed checks from the check-block.sh script, so that "make check-block" can now be run on systems without GNU sed, too. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220216125454.465041-1-thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>