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2022-03-12Hexagon (target/hexagon) assignment to c4 should wait until packet commitTaylor Simpson2-5/+47
On Hexagon, c4 is an alias for predicate registers P3:0. If we assign to c4 inside a packet with reads from predicate registers, the predicate reads should get the old values. Test case added to tests/tcg/hexagon/preg_alias.c Co-authored-by: Michael Lambert <mlambert@cuicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220210021556.9217-13-tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-12Hexagon (target/hexagon) fix bug in conv_df2uw_chopTaylor Simpson2-1/+5
Fix typo that checked for 32 bit nan instead of 64 bit Test case added in tests/tcg/hexagon/usr.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220210021556.9217-11-tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-12Hexagon (tests/tcg/hexagon) fix inline asm in preg_alias.cTaylor Simpson1-24/+22
Replace consecutive inline asm blocks with a single one with proper outputs/inputs/clobbers rather than making assumptions about register values being carried between separate blocks. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220210021556.9217-10-tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-12Hexagon (tests/tcg/hexagon) update overflow testTaylor Simpson1-1/+60
Add a test that sets USR multiple times in a packet Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220210021556.9217-9-tsimpson@quicinc.com> Acked-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-12Hexagon (tests/tcg/hexagon) add floating point instructions to usr.cTaylor Simpson1-0/+339
Tests to confirm floating point instructions are properly setting exception bits in USR Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220210021556.9217-8-tsimpson@quicinc.com> Acked-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-12Hexagon (tests/tcg/hexagon) test instructions that might set bits in USRTaylor Simpson2-1/+805
Hexagon has ~200 instructions that set the saturate bit in USR, these were broken into groups of similar instructions and one instruction from each group is tested with at least one input that does not saturate and at least one input that does saturate. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220210021556.9217-7-tsimpson@quicinc.com> Acked-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-12Hexagon (target/hexagon) properly handle NaN in dfmin/dfmax/sfmin/sfmaxTaylor Simpson2-27/+66
The float??_minnum implementation differs from Hexagon for SNaN, it returns NaN, but Hexagon returns the other input. So, we use float??_minimum_number. Test cases added to tests/tcg/hexagon/fpstuff.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220308190410.22355-1-tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-12Hexagon (target/hexagon) properly handle denorm in arch_sf_recip_commonTaylor Simpson3-7/+49
The arch_sf_recip_common function was calling float32_getexp which adjusts for denorm, but the we actually need the raw exponent bits. This function is called from 3 instructions sfrecipa sffixupn sffixupd Test cases added to tests/tcg/hexagon/fpstuff.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220210021556.9217-6-tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-12Hexagon (target/hexagon) properly set FPINVF bit in sfcmp.uo and dfcmp.uoTaylor Simpson1-4/+2
Instead of checking for nan arguments, use float??_unordered_quiet test cases added in a subsequent patch to more extensively test USR bits Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220210021556.9217-4-tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-12Hexagon HVX (target/hexagon) fix bug in HVX saturate instructionsTaylor Simpson2-3/+72
Two tests added to tests/tcg/hexagon/hvx_misc.c v21.uw = vadd(v11.uw, v10.uw):sat v25:24.uw = vsub(v17:16.uw, v27:26.uw):sat Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220210021556.9217-3-tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-12Hexagon (target/hexagon) fix bug in circular addressingMichael Lambert2-5/+6
Versions V3 and earlier should treat the "K_const" and "length" values as unsigned. Modified circ_test_v3() in tests/tcg/hexagon/circ.c to reproduce the bug Signed-off-by: Michael Lambert <mlambert@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220210021556.9217-2-tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-09esp: recreate ESPState current_req after migrationMark Cave-Ayland1-0/+10
Since PDMA reads/writes are driven by the guest, it is possible that migration can occur whilst a SCSIRequest is still active. Fortunately active SCSIRequests are already included in the migration stream and restarted post migration but this still leaves the reference in ESPState uninitialised. Implement the SCSIBusInfo .load_request callback to obtain a reference to the currently active SCSIRequest and use it to recreate ESPState current_req after migration. Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220305155530.9265-11-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2022-03-09esp: include the current PDMA callback in the migration streamMark Cave-Ayland1-0/+31
This involves (re)adding a PDMA-specific subsection to hold the reference to the current PDMA callback. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220305155530.9265-10-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2022-03-09esp: convert ESPState pdma_cb from a function pointer to an integerMark Cave-Ayland2-14/+41
This prepares for the inclusion of the current PDMA callback in the migration stream since the callback is referenced by an integer instead of a function pointer. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220305155530.9265-9-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2022-03-09esp: introduce esp_pdma_cb() functionMark Cave-Ayland1-2/+7
This function is to be used to execute the current PDMA callback rather than dereferencing the ESPState pdma_cb function pointer directly. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220305155530.9265-8-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2022-03-09esp: introduce esp_set_pdma_cb() functionMark Cave-Ayland1-7/+12
This function is to be used to set the current PDMA callback rather than accessing the ESPState pdma_cb function pointer directly. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220305155530.9265-7-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2022-03-09macfb: set initial value of mode control registers in macfb_common_realize()Mark Cave-Ayland1-0/+8
If booting Linux directly in the q800 machine using -kernel rather than using a MacOS toolbox ROM, the mode control registers are never initialised, causing macfb_mode_write() to fail to determine the current resolution after migration. Resolve this by always setting the initial values of the mode control registers based upon the initial macfb properties during realize. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220305155530.9265-6-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2022-03-09macfb: add VMStateDescription fields for display type and VBL timerMark Cave-Ayland1-0/+2
These fields are required in the migration stream to restore macfb state correctly. Note this is a migration break, but since there are upcoming incompatible changes for the q800 machine (and migration does not even succeed without these patches) then this is not an issue. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220305155530.9265-5-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2022-03-09macfb: increase number of registers saved in MacfbStateMark Cave-Ayland2-1/+10
The MacOS toolbox ROM accesses a number of addresses between 0x0 and 0x200 during initialisation and resolution changes. Whilst the function of many of these registers is unknown, it is worth the minimal cost of saving these extra values as part of migration to help future-proof the migration stream for the q800 machine as it starts to stabilise. Note this is a migration break, but since there are upcoming incompatible changes for the q800 machine (and migration does not even succeed without these patches) then this is not an issue. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220305155530.9265-4-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2022-03-09macfb: don't use special irq_state and irq_mask variables in MacfbStateMark Cave-Ayland2-10/+7
The current IRQ state and IRQ mask are handled exactly the same as standard register accesses, so store these values directly in the regs array rather than having separate variables for them. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220305155530.9265-3-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2022-03-09macfb: add VMStateDescription for MacfbNubusState and MacfbSysBusStateMark Cave-Ayland1-2/+22
Currently when QEMU tries to migrate the macfb framebuffer it crashes randomly because the opaque provided by the DeviceClass vmsd property for both devices is set to MacfbState rather than MacfbNubusState or MacfbSysBusState as appropriate. Resolve the issue by adding new VMStateDescriptions for MacfbNubusState and MacfbSysBusState which embed the existing vmstate_macfb VMStateDescription within them using VMSTATE_STRUCT. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220305155530.9265-2-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2022-03-09macio/pmu.c: remove redundant codeMark Cave-Ayland2-35/+0
Now that the logic related to edge-triggered interrupts is all contained within the mos6522 device the redundant implementation for the mac99 PMU device can be removed. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220305150957.5053-13-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2022-03-09mos6522: implement edge-triggering for CA1/2 and CB1/2 control line IRQsMark Cave-Ayland4-12/+109
The mos6522 datasheet describes how the control lines IRQs are edge-triggered according to the configuration in the PCR register. Implement the logic according to the datasheet so that the interrupt bits in IFR are latched when the edge is detected, and cleared when reading portA/portB or writing to IFR as necessary. To maintain bisectibility this change also updates the SCSI, SCSI data, Nubus and VIA2 60Hz/1Hz clocks in the q800 machine to be negative edge-triggered as confirmed by the PCR programming in all of Linux, NetBSD and MacOS. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220305150957.5053-12-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2022-03-09mac_via: make SCSI_DATA (DRQ) bit live rather than latchedMark Cave-Ayland1-1/+16
The VIA2 on the Q800 machine is not a separate chip as in older Macs but instead is integrated into the on-board logic. From analysing the SCSI routines in the MacOS toolbox ROM (and to a lesser extent NetBSD and Linux) the expectation seems to be that the SCSI_DATA (DRQ) bit is live on the Q800 and not latched. Fortunately we can use the recently introduced mos6522 last_irq_levels variable which tracks the edge-triggered state to return the SCSI_DATA (DRQ) bit live to the guest OS. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220305150957.5053-11-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2022-03-09mos6522: record last_irq_levels in mos6522_set_irq()Mark Cave-Ayland2-2/+10
To detect edge-triggered IRQs it is necessary to store the last state of each IRQ in a last_irq_levels bitmap. Note: this is a migration break for machines which use mos6522 instances which are g3beige/mac99 (PPC) and q800 (m68k). Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220305150957.5053-10-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2022-03-09mos6522: add "info via" HMP command for debuggingMark Cave-Ayland4-0/+121
This displays detailed information about the device registers and timers to aid debugging problems with timers and interrupts. Currently the QAPI generators for HumanReadableText don't work correctly if used in qapi/target-misc.json when a non-specified target is built, so for now manually add a hmp_info_via() wrapper until direct support for per-device HMP/QMP commands is implemented. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220305150957.5053-9-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2022-03-09mos6522: add register names to register read/write trace eventsMark Cave-Ayland3-5/+14
This helps to follow how the guest is programming the mos6522 when debugging. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220305150957.5053-8-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2022-03-09mos6522: use device_class_set_parent_reset() to propagate reset to parentMark Cave-Ayland4-5/+9
Switch from using a legacy approach to the more formal approach for propagating device reset to the parent. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220305150957.5053-7-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2022-03-09mos6522: remove update_irq() and set_sr_int() methods from MOS6522DeviceClassMark Cave-Ayland2-11/+0
Now that the mos6522 IRQs are managed using standard qdev gpios these methods are no longer required. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220305150957.5053-6-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2022-03-09mos6522: switch over to use qdev gpios for IRQsMark Cave-Ayland6-56/+31
For historical reasons each mos6522 instance implements its own setting and update of the IFR flag bits using methods exposed by MOS6522DeviceClass. As of today this is no longer required, and it is now possible to implement the mos6522 IRQs as standard qdev gpios. Switch over to use qdev gpios for the mos6522 device and update all instances accordingly. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220305150957.5053-5-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2022-03-09mac_via: use IFR bit flag constants for VIA2 IRQsMark Cave-Ayland1-10/+9
This allows us to easily see how the physical control lines are mapped to the IFR bit flags. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220305150957.5053-4-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2022-03-09mac_via: use IFR bit flag constants for VIA1 IRQsMark Cave-Ayland1-10/+10
This allows us to easily see how the physical control lines are mapped to the IFR bit flags. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20220305150957.5053-3-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2022-03-09mos6522: add defines for IFR bit flagsMark Cave-Ayland1-7/+15
These are intended to make it easier to see how the physical control lines are wired for each instance. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220305150957.5053-2-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2022-03-08tests/avocado/linux_ssh_mips_malta.py: add missing accel (tcg) tagCleber Rosa1-0/+3
Being explicit about the accelerator used on these tests is a good thing in itself, but it will also be used in the filtering rules applied on "make check-avocado". Signed-off-by: Cleber Rosa <crosa@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220225210156.2032055-6-crosa@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-03-08hw/isa: Inline and remove one-line isa_init_irq()Bernhard Beschow16-23/+16
isa_init_irq() has become a trivial one-line wrapper for isa_get_irq(). It can therefore be removed. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Stefan Berger <stefanb@linux.ibm.com> (tpm_tis_isa) Acked-by: Corey Minyard <cminyard@mvista.com> (isa_ipmi_bt, isa_ipmi_kcs) Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20220301220037.76555-8-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220307134353.1950-14-philippe.mathieu.daude@gmail.com> Reviewed-by: Bernhard Beschow <shentey@gmail.com>
2022-03-08hw/isa: Drop unused attributes from ISADeviceBernhard Beschow2-15/+0
Now that the last users of ISADevice::isairq[] have been resolved during the previous commits, it can be removed for good. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220301220037.76555-7-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220307134353.1950-13-philippe.mathieu.daude@gmail.com> Reviewed-by: Bernhard Beschow <shentey@gmail.com>
2022-03-08hw/isa/isa-bus: Remove isabus_dev_print()Bernhard Beschow2-42/+0
All isabus_dev_print() did was to print up to two IRQ numbers per device. This is redundant if the IRQ numbers are present as QOM properties (see e.g. the modified tests/qemu-iotests/172.out). Now that the last devices relying on isabus_dev_print() had their IRQ numbers QOM'ified, the contribution of this function ultimately became redundant. Remove it. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220301220037.76555-5-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220307134353.1950-12-philippe.mathieu.daude@gmail.com> Reviewed-by: Bernhard Beschow <shentey@gmail.com>
2022-03-08hw/input/pckbd: QOM'ify IRQ numbersBernhard Beschow1-4/+22
Exposing the IRQ numbers as QOM properties not only allows them to be configurable but also to be printed by standard QOM mechanisms. This allows isabus_dev_print() to be retired eventually. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220301220037.76555-4-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220307134353.1950-11-philippe.mathieu.daude@gmail.com> Reviewed-by: Bernhard Beschow <shentey@gmail.com>
2022-03-08hw/rtc/m48t59-isa: QOM'ify IRQ numberBernhard Beschow1-1/+8
Exposing the IRQ number as a QOM property not only allows it to be configurable but also to be printed by standard QOM mechanisms. This allows isabus_dev_print() to be retired eventually. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220301220037.76555-3-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220307134353.1950-10-philippe.mathieu.daude@gmail.com> Reviewed-by: Bernhard Beschow <shentey@gmail.com>
2022-03-08hw/rtc/mc146818rtc: QOM'ify IRQ numberBernhard Beschow3-3/+13
Exposing the IRQ number as a QOM property not only allows it to be configurable but also to be displayed in HMP: Before: (qemu) info qtree ... dev: mc146818rtc, id "" gpio-out "" 1 base_year = 0 (0x0) lost_tick_policy = "discard" After: dev: mc146818rtc, id "" gpio-out "" 1 base_year = 0 (0x0) irq = 8 (0x8) lost_tick_policy = "discard" The reason the IRQ number didn's show up before is that this device does not call isa_init_irq(). Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220301220037.76555-2-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220307134353.1950-9-philippe.mathieu.daude@gmail.com> Reviewed-by: Bernhard Beschow <shentey@gmail.com>
2022-03-08hw/mips/gt64xxx_pci: Resolve gt64120_register()Bernhard Beschow3-21/+6
Now that gt64120_register() lost its pic parameter, there is an opportunity to remove it. gt64120_register() is old style by wrapping qdev API, and the new style is to use qdev directly. So take the opportunity and modernize the code. Suggested-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <20220217101924.15347-8-shentey@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-03-08hw/isa/piix4: Replace some magic IRQ constantsBernhard Beschow1-3/+3
This is a follow-up on patch "malta: Move PCI interrupt handling from gt64xxx_pci to piix4". gt64xxx_pci used magic constants, and probably didn't want to use piix4-specific constants. Now that the interrupt handing resides in piix4, its constants can be used. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20220217101924.15347-7-shentey@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-03-08hw/isa/piix4: Resolve global instance variableBernhard Beschow2-9/+3
Now that piix4_set_irq's opaque parameter references own PIIX4State, piix4_dev becomes redundant. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20220217101924.15347-6-shentey@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-03-08hw/isa/piix4: Pass PIIX4State as opaque parameter for piix4_set_irq()Bernhard Beschow1-3/+3
Passing PIIX4State rather than just the qemu_irq allows for resolving the global piix4_dev variable. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20220217101924.15347-5-shentey@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-03-08hw/isa/piix4: Resolve redundant i8259[] attributeBernhard Beschow1-6/+1
This is a follow-up on patch "malta: Move PCI interrupt handling from gt64xxx_pci to piix4" where i8259[] was moved from MaltaState to PIIX4State to make the code movement more obvious. However, i8259[] seems redundant to *isa, so remove it. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20220217101924.15347-4-shentey@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-03-08malta: Move PCI interrupt handling from gt64xxx_pci to piix4Bernhard Beschow4-61/+62
Handling PCI interrupts in piix4 increases cohesion and reduces differences between piix4 and piix3. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220217101924.15347-3-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-03-08hw/mips/gt64xxx_pci: Fix PCI IRQ levels to be preserved during migrationBernhard Beschow1-5/+2
Based on commit e735b55a8c11dd455e31ccd4420e6c9485191d0c: piix_pci: eliminate PIIX3State::pci_irq_levels PIIX3State::pci_irq_levels are redundant which is already tracked by PCIBus layer. So eliminate them. The IRQ levels in the PCIBus layer are already preserved during migration. By reusing them and rather than having a redundant implementation the bug is avoided in the first place. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220217101924.15347-2-shentey@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-03-08hw/sensor: add Renesas raa228000 deviceTitus Rwantare3-0/+123
Signed-off-by: Titus Rwantare <titusr@google.com> Reviewed-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Corey Minyard <cminyard@mvista.com> Message-Id: <20220307200605.4001451-10-titusr@google.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-03-08hw/sensor: add Renesas raa229004 PMBus deviceTitus Rwantare3-0/+27
The Renesas RAA229004 is a PMBus Multiphase Voltage Regulator Signed-off-by: Titus Rwantare <titusr@google.com> Reviewed-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Corey Minyard <cminyard@mvista.com> Message-Id: <20220307200605.4001451-9-titusr@google.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-03-08hw/sensor: add Intersil ISL69260 device modelTitus Rwantare8-0/+665
Signed-off-by: Titus Rwantare <titusr@google.com> Reviewed-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Corey Minyard <cminyard@mvista.com> Message-Id: <20220307200605.4001451-8-titusr@google.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>