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2025-07-01tests/functional: Require TCG to run Aarch64 imx8mp-evk testPhilippe Mathieu-Daudé1-0/+1
The imx8mp-evk machine can only run with the TCG accelerator. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-id: 20250623121845.7214-25-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01tests/functional: Restrict nested Aarch64 Xen test to TCGPhilippe Mathieu-Daudé1-0/+1
Currently QEMU only support accelerating EL0 and EL1, so features requiring EL2 (like virtualization) or EL3 must be emulated with TCG. On macOS this test fails: qemu-system-aarch64: mach-virt: HVF does not support providing Virtualization extensions to the guest CPU Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250623121845.7214-24-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01tests/functional: Set sbsa-ref machine type in each test functionPhilippe Mathieu-Daudé3-4/+7
fetch_firmware() is only about fetching firmware. Set the machine type and its default console in test_sbsaref_edk2_firmware(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@oss.qualcomm.com> Message-id: 20250623121845.7214-23-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01hw/arm/sbsa-ref: Tidy up use of RAMLIMIT_GB definitionPhilippe Mathieu-Daudé1-3/+5
Define RAMLIMIT_BYTES using the TiB definition and display the error parsed with size_to_str(): $ qemu-system-aarch64-unsigned -M sbsa-ref -m 9T qemu-system-aarch64-unsigned: sbsa-ref: cannot model more than 8 TiB of RAM Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250623121845.7214-22-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01hw/arm/virt: Rename cpu_post_init() -> post_cpus_gic_realized()Philippe Mathieu-Daudé1-4/+5
QDev uses _post_init() during instance creation, before being realized. Since here both vCPUs and GIC are REALIZED, rename as virt_post_cpus_gic_realized() for clarity. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250623121845.7214-21-philmd@linaro.org [PMM: also fixed up comment] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01hw/arm/virt: Make EL2 accelerator check an accept-listPhilippe Mathieu-Daudé1-1/+1
Currently only the TCG and qtest accelerators can handle an EL2 guest. Instead of making the condition check be "fail if KVM or HVF" (an exclude-list), make it a be "allow if TCG or qtest" (an accept-list). This is better for if/when we add new accelerators, as it makes the default be that we forbid an EL2 guest. This is the most likely to be correct and also "fails safe"; if the new accelerator really can support EL2 guests then the implementor will see that they need to add it to the accept-list. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20250623121845.7214-20-philmd@linaro.org [PMM: rewrote commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01hw/arm/virt: Make EL3-guest accel check an accept-listPhilippe Mathieu-Daudé1-1/+1
Currently only the TCG and qtest accelerators can handle an EL3 guest. Instead of making the condition check be "fail if KVM or HVF" (an exclude-list), make it a be "allow if TCG or qtest" (an accept-list). This is better for if/when we add new accelerators, as it makes the default be that we forbid an EL3 guest. This is the most likely to be correct and also "fails safe"; if the new accelerator really can support EL3 guests then the implementor will see that they need to add it to the accept-list. Reported-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250623121845.7214-19-philmd@linaro.org [PMM: rewrote commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01target/arm: Restrict system register properties to system binaryPhilippe Mathieu-Daudé1-5/+6
Do not expose the following system-specific properties on user-mode binaries: - psci-conduit - cntfrq (ARM_FEATURE_GENERIC_TIMER) - rvbar (ARM_FEATURE_V8) - has-mpu (ARM_FEATURE_PMSA) - pmsav7-dregion (ARM_FEATURE_PMSA) - reset-cbar (ARM_FEATURE_CBAR) - reset-hivecs (ARM_FEATURE_M) - init-nsvtor (ARM_FEATURE_M) - init-svtor (ARM_FEATURE_M_SECURITY) - idau (ARM_FEATURE_M_SECURITY) Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250623121845.7214-13-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01target/arm/hvf: Pass @target_el argument to hvf_raise_exception()Philippe Mathieu-Daudé1-7/+7
In preparation of raising exceptions at EL2, add the 'target_el' argument to hvf_raise_exception(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250623121845.7214-12-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01target/arm: Correct KVM & HVF dtb_compatible valuePhilippe Mathieu-Daudé2-2/+2
Linux kernel knows how to parse "arm,armv8", not "arm,arm-v8". See arch/arm64/boot/dts/foundation-v8.dts: https://github.com/torvalds/linux/commit/90556ca1ebdd Cc: qemu-stable@nongnu.org Fixes: 26861c7ce06 ("target-arm: Add minimal KVM AArch64 support") Fixes: 585df85efea ("hvf: arm: Implement -cpu host") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250623121845.7214-10-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01target/arm/hvf: Log $pc in hvf_unknown_hvc() trace eventPhilippe Mathieu-Daudé2-4/+4
Tracing $PC for unknown HVC instructions to not have to look at the disassembled flow of instructions. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250623121845.7214-9-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01accel/hvf: Trace VM memory mappingPhilippe Mathieu-Daudé4-0/+16
Trace memory mapped / unmapped in the guest. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250623121845.7214-8-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01target/arm/hvf: Trace hv_vcpu_run() failuresPhilippe Mathieu-Daudé2-1/+10
Allow distinguishing HV_ILLEGAL_GUEST_STATE in trace events. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250623121845.7214-7-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01target/arm/hvf: Directly re-lock BQL after hv_vcpu_run()Philippe Mathieu-Daudé1-2/+3
Keep bql_unlock() / bql_lock() close. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250623121845.7214-6-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01target/arm: Unify gen_exception_internal()Philippe Mathieu-Daudé3-7/+2
Same code, use the generic variant. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250623121845.7214-4-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01target/arm: Reduce arm_cpu_post_init() declaration scopePhilippe Mathieu-Daudé2-3/+1
arm_cpu_post_init() is only used within the same file unit. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250623121845.7214-3-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01target/arm: Remove arm_handle_psci_call() stubPhilippe Mathieu-Daudé1-5/+1
Since commit 0c1aaa66c24 ("target/arm: wrap psci call with tcg_enabled") the arm_handle_psci_call() call is elided when TCG is disabled. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250623121845.7214-2-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01qtest/bios-tables-test: Update blobs for its=off test on aarch64Gustavo Romero3-2/+0
Update blobs for the its=off test on aarch64 after fix. Basically, all structs related to ITS are gone in MADT and IORT tables after the fix (previously ITS was not properly disabled when "its=off" option was passed to the machine). MADT diff: [000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] -[004h 0004 4] Table Length : 000000B8 +[004h 0004 4] Table Length : 000000A4 [008h 0008 1] Revision : 04 -[009h 0009 1] Checksum : C1 +[009h 0009 1] Checksum : 08 [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 [024h 0036 4] Local Apic Address : 00000000 [028h 0040 4] Flags (decoded below) : 00000000 PC-AT Compatibility : 0 [02Ch 0044 1] Subtable Type : 0C [Generic Interrupt Distributor] [02Dh 0045 1] Length : 18 [02Eh 0046 2] Reserved : 0000 [030h 0048 4] Local GIC Hardware ID : 00000000 [034h 0052 8] Base Address : 0000000008000000 [03Ch 0060 4] Interrupt Base : 00000000 @@ -48,37 +48,29 @@ [064h 0100 8] Base Address : 0000000000000000 [06Ch 0108 8] Virtual GIC Base Address : 0000000000000000 [074h 0116 8] Hypervisor GIC Base Address : 0000000000000000 [07Ch 0124 4] Virtual GIC Interrupt : 00000000 [080h 0128 8] Redistributor Base Address : 0000000000000000 [088h 0136 8] ARM MPIDR : 0000000000000000 [090h 0144 1] Efficiency Class : 00 [091h 0145 1] Reserved : 00 [092h 0146 2] SPE Overflow Interrupt : 0000 [094h 0148 1] Subtable Type : 0E [Generic Interrupt Redistributor] [095h 0149 1] Length : 10 [096h 0150 2] Reserved : 0000 [098h 0152 8] Base Address : 00000000080A0000 [0A0h 0160 4] Length : 00F60000 -[0A4h 0164 1] Subtable Type : 0F [Generic Interrupt Translator] -[0A5h 0165 1] Length : 14 -[0A6h 0166 2] Reserved : 0000 -[0A8h 0168 4] Translation ID : 00000000 -[0ACh 0172 8] Base Address : 0000000008080000 -[0B4h 0180 4] Reserved : 00000000 IORT diff: [000h 0000 4] Signature : "IORT" [IO Remapping Table] -[004h 0004 4] Table Length : 000000EC +[004h 0004 4] Table Length : 000000AC [008h 0008 1] Revision : 03 -[009h 0009 1] Checksum : 57 +[009h 0009 1] Checksum : 97 [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 -[024h 0036 4] Node Count : 00000003 +[024h 0036 4] Node Count : 00000002 [028h 0040 4] Node Offset : 00000030 [02Ch 0044 4] Reserved : 00000000 -[030h 0048 1] Type : 00 -[031h 0049 2] Length : 0018 -[033h 0051 1] Revision : 01 +[030h 0048 1] Type : 04 +[031h 0049 2] Length : 0044 +[033h 0051 1] Revision : 04 [034h 0052 4] Reserved : 00000000 [038h 0056 4] Mapping Count : 00000000 [03Ch 0060 4] Mapping Offset : 00000000 -[040h 0064 4] ItsCount : 00000001 -[044h 0068 4] Identifiers : 00000000 - -[048h 0072 1] Type : 04 -[049h 0073 2] Length : 0058 -[04Bh 0075 1] Revision : 04 -[04Ch 0076 4] Reserved : 00000001 -[050h 0080 4] Mapping Count : 00000001 -[054h 0084 4] Mapping Offset : 00000044 - -[058h 0088 8] Base Address : 0000000009050000 -[060h 0096 4] Flags (decoded below) : 00000001 +[040h 0064 8] Base Address : 0000000009050000 +[048h 0072 4] Flags (decoded below) : 00000001 COHACC Override : 1 HTTU Override : 0 Proximity Domain Valid : 0 -[064h 0100 4] Reserved : 00000000 -[068h 0104 8] VATOS Address : 0000000000000000 -[070h 0112 4] Model : 00000000 -[074h 0116 4] Event GSIV : 0000006A -[078h 0120 4] PRI GSIV : 0000006B -[07Ch 0124 4] GERR GSIV : 0000006D -[080h 0128 4] Sync GSIV : 0000006C -[084h 0132 4] Proximity Domain : 00000000 -[088h 0136 4] Device ID Mapping Index : 00000000 - -[08Ch 0140 4] Input base : 00000000 -[090h 0144 4] ID Count : 0000FFFF -[094h 0148 4] Output Base : 00000000 -[098h 0152 4] Output Reference : 00000030 -[09Ch 0156 4] Flags (decoded below) : 00000000 - Single Mapping : 0 - -[0A0h 0160 1] Type : 02 -[0A1h 0161 2] Length : 004C -[0A3h 0163 1] Revision : 03 -[0A4h 0164 4] Reserved : 00000002 -[0A8h 0168 4] Mapping Count : 00000002 -[0ACh 0172 4] Mapping Offset : 00000024 - -[0B0h 0176 8] Memory Properties : [IORT Memory Access Properties] -[0B0h 0176 4] Cache Coherency : 00000001 -[0B4h 0180 1] Hints (decoded below) : 00 +[04Ch 0076 4] Reserved : 00000000 +[050h 0080 8] VATOS Address : 0000000000000000 +[058h 0088 4] Model : 00000000 +[05Ch 0092 4] Event GSIV : 0000006A +[060h 0096 4] PRI GSIV : 0000006B +[064h 0100 4] GERR GSIV : 0000006D +[068h 0104 4] Sync GSIV : 0000006C +[06Ch 0108 4] Proximity Domain : 00000000 +[070h 0112 4] Device ID Mapping Index : 00000000 + +[074h 0116 1] Type : 02 +[075h 0117 2] Length : 0038 +[077h 0119 1] Revision : 03 +[078h 0120 4] Reserved : 00000001 +[07Ch 0124 4] Mapping Count : 00000001 +[080h 0128 4] Mapping Offset : 00000024 + +[084h 0132 8] Memory Properties : [IORT Memory Access Properties] +[084h 0132 4] Cache Coherency : 00000001 +[088h 0136 1] Hints (decoded below) : 00 Transient : 0 Write Allocate : 0 Read Allocate : 0 Override : 0 -[0B5h 0181 2] Reserved : 0000 -[0B7h 0183 1] Memory Flags (decoded below) : 03 +[089h 0137 2] Reserved : 0000 +[08Bh 0139 1] Memory Flags (decoded below) : 03 Coherency : 1 Device Attribute : 1 -[0B8h 0184 4] ATS Attribute : 00000000 -[0BCh 0188 4] PCI Segment Number : 00000000 -[0C0h 0192 1] Memory Size Limit : 40 -[0C1h 0193 3] Reserved : 000000 - -[0C4h 0196 4] Input base : 00000000 -[0C8h 0200 4] ID Count : 000000FF -[0CCh 0204 4] Output Base : 00000000 -[0D0h 0208 4] Output Reference : 00000048 -[0D4h 0212 4] Flags (decoded below) : 00000000 - Single Mapping : 0 - -[0D8h 0216 4] Input base : 00000100 -[0DCh 0220 4] ID Count : 0000FEFF -[0E0h 0224 4] Output Base : 00000100 -[0E4h 0228 4] Output Reference : 00000030 -[0E8h 0232 4] Flags (decoded below) : 00000000 +[08Ch 0140 4] ATS Attribute : 00000000 +[090h 0144 4] PCI Segment Number : 00000000 +[094h 0148 1] Memory Size Limit : 40 +[095h 0149 3] Reserved : 000000 + +[098h 0152 4] Input base : 00000000 +[09Ch 0156 4] ID Count : 000000FF +[0A0h 0160 4] Output Base : 00000000 +[0A4h 0164 4] Output Reference : 00000030 +[0A8h 0168 4] Flags (decoded below) : 00000000 Single Mapping : 0 Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20250628195722.977078-10-gustavo.romero@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01hw/arm/virt-acpi-build: Fix ACPI IORT and MADT tables when its=offGustavo Romero2-54/+90
Currently, the ITS Group nodes in the IORT table and the GIC ITS Struct in the MADT table are always generated, even if GIC ITS is not available on the machine. This commit fixes it by not generating the ITS Group nodes, not mapping any other node to them, and not advertising the GIC ITS in the MADT table, when GIC ITS is not available on the machine. Since the fix changes the MADT and IORT tables, add the blobs for the "its=off" test to the allow list and update them in the next commit. This commit also renames the smmu_idmaps and its_idmaps variables in build_iort() to rc_smmu_idmaps and rc_its_idmaps, respectively, to make it clearer which nodes are involved in the mappings associated with these variables. Reported-by: Udo Steinberg <udo@hypervisor.org> Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Message-id: 20250628195722.977078-9-gustavo.romero@linaro.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2886 Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Co-authored-by: Philippe Mathieu-Daudé <philmd@linaro.org> [PMM: wrapped an overlong comment] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01qtest/bios-tables-test: Add blobs for its=off test on aarch64Gustavo Romero3-2/+0
Add blobs for test_acpi_aarch64_virt_tcg_its_off(), which introduces a new variant, .its_off, that requires variations of the MADT and IORT tables. MADT (aka APIC) diff: +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 000000B8 +[008h 0008 1] Revision : 04 +[009h 0009 1] Checksum : C1 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPC " +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : 00000000 +[028h 0040 4] Flags (decoded below) : 00000000 + PC-AT Compatibility : 0 + +[02Ch 0044 1] Subtable Type : 0C [Generic Interrupt Distributor] +[02Dh 0045 1] Length : 18 +[02Eh 0046 2] Reserved : 0000 +[030h 0048 4] Local GIC Hardware ID : 00000000 +[034h 0052 8] Base Address : 0000000008000000 +[03Ch 0060 4] Interrupt Base : 00000000 +[040h 0064 1] Version : 03 +[041h 0065 3] Reserved : 000000 + +[044h 0068 1] Subtable Type : 0B [Generic Interrupt Controller] +[045h 0069 1] Length : 50 +[046h 0070 2] Reserved : 0000 +[048h 0072 4] CPU Interface Number : 00000000 +[04Ch 0076 4] Processor UID : 00000000 +[050h 0080 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[054h 0084 4] Parking Protocol Version : 00000000 +[058h 0088 4] Performance Interrupt : 00000017 +[05Ch 0092 8] Parked Address : 0000000000000000 +[064h 0100 8] Base Address : 0000000000000000 +[06Ch 0108 8] Virtual GIC Base Address : 0000000000000000 +[074h 0116 8] Hypervisor GIC Base Address : 0000000000000000 +[07Ch 0124 4] Virtual GIC Interrupt : 00000000 +[080h 0128 8] Redistributor Base Address : 0000000000000000 +[088h 0136 8] ARM MPIDR : 0000000000000000 +[090h 0144 1] Efficiency Class : 00 +[091h 0145 1] Reserved : 00 +[092h 0146 2] SPE Overflow Interrupt : 0000 + +[094h 0148 1] Subtable Type : 0E [Generic Interrupt Redistributor] +[095h 0149 1] Length : 10 +[096h 0150 2] Reserved : 0000 +[098h 0152 8] Base Address : 00000000080A0000 +[0A0h 0160 4] Length : 00F60000 + +[0A4h 0164 1] Subtable Type : 0F [Generic Interrupt Translator] +[0A5h 0165 1] Length : 14 +[0A6h 0166 2] Reserved : 0000 +[0A8h 0168 4] Translation ID : 00000000 +[0ACh 0172 8] Base Address : 0000000008080000 +[0B4h 0180 4] Reserved : 00000000 IORT diff: +[000h 0000 4] Signature : "IORT" [IO Remapping Table] +[004h 0004 4] Table Length : 000000EC +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : 57 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPC " +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Node Count : 00000003 +[028h 0040 4] Node Offset : 00000030 +[02Ch 0044 4] Reserved : 00000000 + +[030h 0048 1] Type : 00 +[031h 0049 2] Length : 0018 +[033h 0051 1] Revision : 01 +[034h 0052 4] Reserved : 00000000 +[038h 0056 4] Mapping Count : 00000000 +[03Ch 0060 4] Mapping Offset : 00000000 + +[040h 0064 4] ItsCount : 00000001 +[044h 0068 4] Identifiers : 00000000 + +[048h 0072 1] Type : 04 +[049h 0073 2] Length : 0058 +[04Bh 0075 1] Revision : 04 +[04Ch 0076 4] Reserved : 00000001 +[050h 0080 4] Mapping Count : 00000001 +[054h 0084 4] Mapping Offset : 00000044 + +[058h 0088 8] Base Address : 0000000009050000 +[060h 0096 4] Flags (decoded below) : 00000001 + COHACC Override : 1 + HTTU Override : 0 + Proximity Domain Valid : 0 +[064h 0100 4] Reserved : 00000000 +[068h 0104 8] VATOS Address : 0000000000000000 +[070h 0112 4] Model : 00000000 +[074h 0116 4] Event GSIV : 0000006A +[078h 0120 4] PRI GSIV : 0000006B +[07Ch 0124 4] GERR GSIV : 0000006D +[080h 0128 4] Sync GSIV : 0000006C +[084h 0132 4] Proximity Domain : 00000000 +[088h 0136 4] Device ID Mapping Index : 00000000 + +[08Ch 0140 4] Input base : 00000000 +[090h 0144 4] ID Count : 0000FFFF +[094h 0148 4] Output Base : 00000000 +[098h 0152 4] Output Reference : 00000030 +[09Ch 0156 4] Flags (decoded below) : 00000000 + Single Mapping : 0 + +[0A0h 0160 1] Type : 02 +[0A1h 0161 2] Length : 004C +[0A3h 0163 1] Revision : 03 +[0A4h 0164 4] Reserved : 00000002 +[0A8h 0168 4] Mapping Count : 00000002 +[0ACh 0172 4] Mapping Offset : 00000024 + +[0B0h 0176 8] Memory Properties : [IORT Memory Access Properties] +[0B0h 0176 4] Cache Coherency : 00000001 +[0B4h 0180 1] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0B5h 0181 2] Reserved : 0000 +[0B7h 0183 1] Memory Flags (decoded below) : 03 + Coherency : 1 + Device Attribute : 1 +[0B8h 0184 4] ATS Attribute : 00000000 +[0BCh 0188 4] PCI Segment Number : 00000000 +[0C0h 0192 1] Memory Size Limit : 40 +[0C1h 0193 3] Reserved : 000000 + +[0C4h 0196 4] Input base : 00000000 +[0C8h 0200 4] ID Count : 000000FF +[0CCh 0204 4] Output Base : 00000000 +[0D0h 0208 4] Output Reference : 00000048 +[0D4h 0212 4] Flags (decoded below) : 00000000 + Single Mapping : 0 + +[0D8h 0216 4] Input base : 00000100 +[0DCh 0220 4] ID Count : 0000FEFF +[0E0h 0224 4] Output Base : 00000100 +[0E4h 0228 4] Output Reference : 00000030 +[0E8h 0232 4] Flags (decoded below) : 00000000 + Single Mapping : 0 Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20250628195722.977078-8-gustavo.romero@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01qtest/bios-tables-test: Add test for when ITS is off on aarch64Philippe Mathieu-Daudé2-0/+23
Arm64 GIC ITS (Interrupt Translation Service) is an optional piece of hardware introduced in GICv3 and, being optional, it can be disabled in QEMU aarch64 VMs that support it using machine option "its=off", like, for instance: "-M virt,its=off". In ACPI, the ITS is advertised, if present, in the MADT (aka APIC) table, while the ID mappings from the Root Complex (RC) and from the SMMU nodes to the ITS Group nodes are described in the IORT table. This new test verifies that when the "its=off" option is passed to the machine the ITS-related data is correctly pruned from the ACPI tables. The new blobs for this test will be added in a following commit. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20250628195722.977078-7-gustavo.romero@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01hw/arm/virt-acpi-build: Factor out create_its_idmapsGustavo Romero1-21/+40
Factor out a new function, create_its_idmaps(), from the current build_iort code. Add proper comments to it clarifying how the ID ranges that go directly to the ITS Group node are computed based on the ones that are directed to the SMMU node. Suggested-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Message-id: 20250628195722.977078-6-gustavo.romero@linaro.org [PMM: drop hardcoded tabs] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01hw/arm/virt-acpi-build: Improve comment in build_iortGustavo Romero1-6/+19
When building the Root Complex table, the comment about the code that maps the RC node to SMMU node is misleading because it reads "RC -> SMMUv3 -> ITS", but the code is only mapping the RCs IDs to the SMMUv3 node. The step of mapping from the SMMUv3 IDs to the ITS Group node is actually defined in another table (in the SMMUv3 node). So change the comment to read "RC -> SMMUv3" instead. Signed-off-by Gustavo Romero <gustavo.romero@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20250628195722.977078-5-gustavo.romero@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01hw/arm/virt: Simplify create_its()Philippe Mathieu-Daudé1-10/+7
No need to strstr() check the class name when we can use kvm_irqchip_in_kernel() to check if the ITS from the host can be used. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org> Message-id: 20250628195722.977078-4-gustavo.romero@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01hw/arm/virt: Simplify logic for setting instance's 'tcg_its' variableGustavo Romero1-6/+2
Because 'tcg_its' in the machine instance is set based on the machine class’s negated variable 'no_tcg_its', 'tcg_its' is the opposite of 'no_tcg_its' and hence the code in question can be simplified as: tcg_its = !no_tcg_its. Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20250628195722.977078-3-gustavo.romero@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01hw/intc/gicv3_its: Do not check its_class_name()Philippe Mathieu-Daudé2-19/+15
Since commit cc5e719e2c8 ("kvm: require KVM_CAP_SIGNAL_MSI"), the single implementation of its_class_name() no longer returns NULL (it now always returns a valid char pointer). Hence, update the prototype docstring and remove the tautological checks that use the its_class_name() returned value. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20250628195722.977078-2-gustavo.romero@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01arm/kvm: use fd instead of fdarray[2]Cornelia Huck1-4/+4
We have fd, so might as well neaten things up. Suggested-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com> Message-id: 20250617153931.1330449-15-cohuck@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01arm/cpu: Store id_mmfr0-5 into the idregs arrayEric Auger9-156/+140
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Sebastian Ott <sebott@redhat.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com> Message-id: 20250617153931.1330449-12-cohuck@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01arm/cpu: Store id_dfr0/1 into the idregs arrayEric Auger10-57/+48
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Sebastian Ott <sebott@redhat.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com> Message-id: 20250617153931.1330449-11-cohuck@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01arm/cpu: Store id_pfr0/1/2 into the idregs arrayEric Auger10-89/+82
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Sebastian Ott <sebott@redhat.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com> Message-id: 20250617153931.1330449-10-cohuck@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01arm/cpu: Store id_isar0-7 into the idregs arrayEric Auger10-241/+243
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Sebastian Ott <sebott@redhat.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com> Message-id: 20250617153931.1330449-9-cohuck@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01arm/cpu: Store aa64smfr0 into the idregs arrayEric Auger6-14/+9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Sebastian Ott <sebott@redhat.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com> Message-id: 20250617153931.1330449-8-cohuck@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01arm/cpu: Store aa64dfr0/1 into the idregs arrayEric Auger9-52/+43
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Sebastian Ott <sebott@redhat.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com> Message-id: 20250617153931.1330449-7-cohuck@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01arm/cpu: Store aa64mmfr0-3 into the idregs arrayEric Auger8-102/+95
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Sebastian Ott <sebott@redhat.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com> Message-id: 20250617153931.1330449-6-cohuck@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01arm/cpu: Store aa64pfr0/1 into the idregs arrayEric Auger8-91/+68
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Sebastian Ott <sebott@redhat.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com> Message-id: 20250617153931.1330449-5-cohuck@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01arm/cpu: Store aa64isar1/2 into the idregs arrayEric Auger8-56/+48
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Sebastian Ott <sebott@redhat.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com> Message-id: 20250617153931.1330449-4-cohuck@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01arm/cpu: Store aa64isar0/aa64zfr0 into the idregs arraysEric Auger8-62/+97
Also add kvm accessors for storing host features into idregs. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Sebastian Ott <sebott@redhat.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com> Message-id: 20250617153931.1330449-3-cohuck@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01arm/cpu: Add sysreg definitions in cpu-sysregs.hEric Auger4-0/+149
This new header contains macros that define aarch64 registers. In a subsequent patch, this will be replaced by a more exhaustive version that will be generated from linux arch/arm64/tools/sysreg file. Those macros are sufficient to migrate the storage of those ID regs from named fields in isar struct to an array cell. [CH: reworked to use different structures] [CH: moved accessors from the patches first using them to here, dropped interaction with writable registers, which will happen later] [CH: use DEF magic suggested by rth] Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Sebastian Ott <sebott@redhat.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com> Message-id: 20250617153931.1330449-2-cohuck@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01target/arm: Make RETA[AB] UNDEF when pauth is not implementedSolomon Tan1-0/+4
According to the Arm A-profile A64 Instruction Set Architecture, RETA[AB] should be decoded as UNDEF if the pauth feature is not implemented. We got this right in the initial implementation, but accidentally dropped the feature-check when we converted these insns to decodetree. Cc: qemu-stable@nongnu.org Fixes: 0ebbe9021254f ("target/arm: Convert BRA[AB]Z, BLR[AB]Z, RETA[AB] to decodetree") Signed-off-by: Solomon Tan <root@wjsota.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250616171549.59190-1-root@wjsota.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-01MAINTAINERS: add myself as reviewer for Apple Silicon HVFMads Ynddal1-0/+2
I've both publicly and private been digging around the Apple Silicon HVF code, and use it daily as part of my job. I feel I have a solid understanding of it, so I thought I'd step up and assist. I've added myself as reviewer to the common "HVF" as well, to be informed of changes that might affect the Apple Silicon HVF code, which will be my primary focus. Signed-off-by: Mads Ynddal <mads@ynddal.dk> Message-id: 20250617093001.70080-1-mads@ynddal.dk Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-06-30tcg: Fix constant propagation in tcg_reg_alloc_dupRichard Henderson1-1/+1
The scalar constant must be replicated for dup. Cc: qemu-stable@nongnu.org Fixes: bab1671f0fa ("tcg: Manually expand INDEX_op_dup_vec") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3002 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-30tcg/riscv: Fix typo in tgen_extractRichard Henderson1-1/+1
Fix the direction of the shift, introduced when converting the codebase to TCGOutOp* and small tgen_* helpers. Fixes: 5a4d034f3cb ("tcg: Convert extract to TCGOutOpExtract") Reported-by: Andrea Bolognani <abologna@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Andrea Bolognani <abologna@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-06-30tcg/optimize: Simplify fold_eqv constant checksRichard Henderson1-3/+1
Both cases are handled by fold_xor after conversion. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-30tcg/optimize: Simplify fold_orc constant checksRichard Henderson1-5/+5
If operand 2 is constant, then the computation of z_mask and a_mask will produce the same results as the explicit check via fold_xi_to_i. Shift the calls of fold_xx_to_i and fold_ix_to_not down below the i2->is_const check. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-30tcg/optimize: Simplify fold_andc constant checksRichard Henderson1-4/+5
If operand 2 is constant, then the computation of z_mask and a_mask will produce the same results as the explicit check via fold_xi_to_i. Shift the calls of fold_xx_to_i and fold_ix_to_not down below the i2->is_const check. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-30tcg/optimize: Simplify fold_and constant checksRichard Henderson1-4/+3
If operand 2 is constant, then the computation of z_mask and a_mask will produce the same results as the explicit checks via fold_xi_to_i and fold_xi_to_x. Shift the call of fold_xx_to_x down below the ti_is_const(t2) check. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-30tcg/optimize: Fold and to extract during optimizeRichard Henderson1-3/+30
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-30tcg/optimize: Use fold_and in do_constant_folding_cond[12]Richard Henderson1-0/+5
When lowering tst comparisons, completely fold the and opcode that we generate. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-30tcg/optimize: Build and use o_bits in fold_shiftRichard Henderson1-2/+4
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-30tcg/optimize: Build and use o_bits in fold_sextractRichard Henderson1-24/+6
This was the last use of fold_affected_mask, now fully replaced by fold_masks_zosa. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>